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Full text of "SGS Motion Control Application Manual"

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Technologs and Sen, ice 



MOTION CONTROL 
APPLICATION MANUAL 




THERMAL 
SHUTDOWN 






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Motion Control 
Application Manual 



January, 1987 



TABLE OF CONTENTS 


Page 


•j SGS IN THE WORLD 


4 


INTRODUCTION 


6 


PRODUCT SELECTOR GUIDE 


8 


1 

ALPHANUMERICAL INDEX 


13 


APPLICATION NOTES 

1 


21 


1 DATASHEETS: 

— Integrated circuits 

— Discrete Power 
-GS-D200 


311 


1 

PACKAGES 


1135 


SGS OFFICES 


1151 





IDENTITY 

Late in 1 957. SGS was founded around a team of 
researchers who were already carrying out pioneer work 
in the field of semiconductors. From that small nucleus, 
the company has evolved into a Group of Companies, 
operating on a worldwide basis as a broad range 
semiconductor producer, with bilings over 300 million 
dollars and employing over 9500 people. 

The SGS Group of Companies has now reached a total 
of 11 subsidiaries, located in Brazil, France. Germany, 
Italy, Malta, Malaysia, Singapore, Sweden. Switzerland, 
United Kingdom and the USA. 

To go with its logo, the company takes the motto 
"Technology and Service", underlining the. accent given 
to the development of state-of-the-art technologies and 
the corporate commitment to offer customers the best 
quality and service in the industry. 

SGS IN EUROPE 




A A MALTA 



• HEADQUARTERS 
A FACTORIES 



SALES OFFICES 
DESIGN CENTERS 



SGS IN NORTH AMERICA 





WALTHAM (MA) 

■ H-4 

POUGHKEEPSIE (NY) 



HAUPPAUGE (NY) 



NORCROSS(GA) 



FT. LAUDERDALE (FL) 



SGS IN ASIA/PACIFIC 



TOKYO 




* HEADQUARTERS 
A FACTORIES 



■ SALES OFFICES 
• DESIGN CENTERS 



TECHNOLOGY AND INNOVATION 
SOLVE YOUR MOTION CONTROL PROBLEMS 



Since the first high power ICs emerged at the 
end of the 1960s SGS has set the pace in 
power IC process technology, plastic power 
packages and innovative circuit design. 
Originally this technology know-how was 
applied to consumer circuits such as high 
power audio amplifiers and TV vertical 
deflection stages, so when real motor driving 
ICs emerged at the end of the seventies SGS 
already possessed a unique understanding of 
the problems involved and, more important, 
how they could be solved. 

A/ready in 1979, while other companies 
were still content to produce darlington 
arrays, SGS launched a switchmode DC 
motor driver, the L292, capable of delivering 
70W useful power to the load. The L292 was 
assembled in the SGS-developed Multiwatt™ 
package, now a much-copied industry 
standard power package. 

Since then the company has introduced 
many other world-beating power ICs for 
motor and solenoid driving applications: the 
L295 Dual Switchmode Solenoid Driver, the 
L298 Dual Bridge Motor Driver, the L272 
Dual Power Op Amp, the L6230 Brush/ess 
Motor Driver and many more. 

Continuing this tradition of innovation, today 
SGS has introduced new high power bridge 
driver ICs, the L6202 and L6203, which 
exploit DMOS output transistors to achieve 
very high efficiency and fast switching 
capability. 




Two L6203 DMOS bridge driver ICs and an L650 
current controller make a complete stepper mote 
drive system delivering 3A/phase with very hig 
efficiency. 

Based on a unique technology called Mult: 
power-BCD, which combines bipolar lineal 
CMOS logic and power DMOS, these ICs ar 
probably the most significant developmen 
in semiconductor technology since th 
dynamic RAM. Because of its high efficienc 
the L6202 can deliver 70W to the loac 
yet the device is assembled in a DIP packagi 
and the L6203 delivers an unheard-of 250IA 

Another SGS pacesetting product is th 
VB 100 intelligent duty cycle controller. Th x 
VIPower™ device combines a high vo/tagi 
high current Darlington with on-chip intell 
gence for duty cycle control and therm, 
protection. The same VIPower™ technolog 



is used for the VB010 self protected switch 
which features a 400V Power Darlington 
capable of 10A output current with built-in 
protection circuits. 

SGS has also kept ahead in POWER MOS 
transistors by exploiting high density cell 
structures. The SGSP322HD has a reduced 
chip area but equal overall performance to 
the original SGSP322 so offers a cost reduc- 
tion for the user. 




TO-240 — The unique SGS combination of ad- 
vanced chip technology in a truly "user friendly" 
package, gives the solution to meet all high power 
system requirements. 



tion you'll need to use them. The Motion 
Control Application Manual also contains a 
selection of SGS' innovative power supply 
products which will be useful in your 
system. 



Dependable Delivery 

Advanced technology and innovation are 
just two of the reasons for SGS' remarkable 
growth performance. The third is manufac- 
turing science — the ability to produce ad- 
vanced products in high volumes, depend- 
ably, and with competitive quality & re- 
liability. Just for bipolar linear and mixed 
bipolar /MOS ICs SGS has four 5" wafer 
fabs — in France, Italy and Singapore. 
Another two state-of-the-art 5" wafer fabs 
are dedicated to power transistor produc- 
tion. In addition, the companty has highly- 
automated assembly facilities in Italy, 
France, Malta, Malaysia and Singapore. 

SGS also has local design centers in all major 
semiconductor markets — USA, England, 
France, West Germany, Singapore and Italy 
— to speed the development of new products 
to satisfy the special needs of your applica- 
tion. And a worldwide network of sales 
offices and distributors means that SGS 
technology is never far away. 



Moving up in power, the SGS150MA010D1 
isolated TRANSPACK module containing 
SGS POWER MOS transistors is designed for 
high switching speed DC motor control 
applications. On resistance is as low as 
0.009Q, and the easy drive and rugged 
\DMOS technology make this module ideal 
'for high power applications. 

These advances do not stop with si/icon 
technology, SGS's established expertise in 
oackaging has led to the recent introduction 
of a fully isolated package for power transis- 
tors. Used in place of the SOT-93 (TO-218), 
the ISOWATT218^ M provides guaranteed 
'solation of 4k V DC and compliance with 
VDE specifications for creepage distance and 
clearance in electrical equipment. 

All of these products are included in this 
book, along with the application informa- 



g»3" 




New diffusion facilities give SGS the advantage in 
Service, Quality and cost. State-of-the-art 5" 
wafer fabs are used for both linear ICs and power 
transistors. 



PRODUCT SELECTOR 



(Integrated Circuits) 



Applications 



Type and Functions 



SOLENOID/HAMMER/ 
NEEDLE/RELAY 




L294 — Switch-Mode Solenoid Driver 

L295 — Dual Switch-Mode Solenoid Driver 

L601/2/3/4 - Darlington Arrays 

L702 - 2A Quad Darlington Array 

L3654S — Printer Solenoid Driver 

L5832 — Solenoid Controller 

L62T2 — High Current Solenoid Driver 

L6221A/N - Quad Darlington Switches 

L6222 — Quad Transistor Switch 

L6503 — Hammer Solenoid Controller 

L6504 - Solenoid Controller 

L7 150/52/80/82 - Quad Darlington Switches 

L9222 — Quad Inverting Transistor Switch 

L9305A/C - Dual High Current Relay Drivers 

L9306/C - Dual Relay Drivers 

L9335/6 - Solenoid Drivers 

L9342 -Six-Solenoid Driver 

ULN2001A/2A/3A/4A - Seven Darlington Arrays 

ULN2064B to ULN2071B - Quad Darlington Switches 

ULN2074B to ULN2077B - Quad Darlington Switches 

ULN2801A/2A/3A/4A/5A - Eight Darlington Arrays 

ULQ2001R/2R/3R/4R - Seven Darlington Arrays 



UNIPOLAR STEPPER 
MOTORS 




L297/A - Stepper Motor Controllers 

L702 - 2A Quad Darlington Switch 

L6100/1/2 - 100V-1 A Quad DMOS Power Switch 

L6506 — Current Controller for Stepping Motors 

L7 150/52/80/82 - Quad Darlington Switches 

ULN2064B to ULN2071B - Quad Darlington Switches 

ULN2074B to ULN2077B - Quad Darlington Switches 



BIPOLAR STEPPER 
MOTORS 




L297/A - Stepper Motor Controllers 

L298N - Dual Full Bridge Driver 

L6202 - 1.5A DMOS Full Bridge Driver 

L6203 - 3A DMOS Full Bridge Driver 

L6207 - Dual Full Bridge Driver 

L6209 - 3A Full Bridge Driver With Diodes 

L6210 - Dual Schottky Diode Bridge 

L6217/A — Stepper Motor Driver 

L6506 — Current Controller for Stepping Motors 

MC3479C - Stepper Motor Driver 

PBL3717A - Stepper Motor Driver 

GS-D200 - Switch-Mode Stepper Motor Driver (Complete Module) 



BRUSHLESS MOTORS 




L6230 — Bidirectional Three-Phase Brusheless DC Motor Driver 
L6231 — Three-Phase Brusheless DC Motor Driver 
L6233 — Phase Locked Frequency Controller 
TDA8116 - Four Phase Brusheless Motor Driver 



PRODUCT SELECTOR 



(Integrated Circuits) 



Applications 



DC MOTORS 




Type and Functions 



L290 — Tachometer Converter 

L291 — 5 Bit D/A Converter and Position Amplifier 

L292 - Switch-Mode Driver for DC Motors 

L149- 4A Linear Driver 

L165 — 3A Power Operational Amplifier 

L272/M - Dual Power Operational Amplifiers 

L2720/2 - Low Drop Dual Power Operational Amplifier: 

L293/E - Push-Pull Four Channel Drivers 

L293C - Push-Pull Four Channel/Dual H-Bridge Driver 

L293D - Push-Pull Four Channel Driver With Diodes 

L298N - Dual Full-Bridge Driver 

L9350 — Low Saturation Driver 

TDA7272 - Full Bridge DC Motor Regulator 

TDA8115 - Dual Motor Driver 



DISPLAYS 



M5450/1 - Led Display Drivers 
M5480/81/82 - Led Display Drivers 
L3654S — Printer Solenoid Driver 
L601/2/3/4 - Darlington Arrays 
ULN2001A/2A/3A/4A - Seven Darlington Arrays 
ULQ2001R/2R/3R/4R - Seven Darlington Arrays 



SPECIAL FUNCTIONS 



£? 
^ 



.11 



o 6- 



AM26LS31 - Quad High Speed Differential Line Driver 

AM26LS32/3 - RS422 and RS423 Quad Differential Line Receivers 

MC1488 - RS232C Quad Line Driver 

MC1489/A - Quad Line Receiver 

DAC0806/7/8 - 8 Bit D/A Converters 

AM6012/A - 12 Bit High Speed Multypling D/A Converters 

L6570A/B - 2-Channel Floppy Disk Read/Write Circuits 



T 



IT 



POWER SUPPLIES 




L200 — Adjustable Voltage and Current Regulator 

L296/P - High Current Switching Regulators 

L387A - Very Low Drop 5V Regulator 

L4901/2/3/4 - Dual 5V Regulators with Reset 

L4920/1 - Very Low Drop Adjustable Regulators 

L4941 - Very Low Drop 1A Regulator 

L4960/2 — Power Switching Regulators 

SG1524/1525/1527/2524/2525/2527/3524/3525/3527 - Regulating Pulse 

width modulator 

TDA4601 - Switch-Mode Power Supply Controller 

TDA8130/2 - Current Mode PWM Controllers 

TL7700 series — Supply Voltage Supervisors 

UC 1840/2840/3840- Programmable, Off-Line, PWM Controllers 

UC1842/3/4/5 - UC2842/3/4/5 - UC3842/3/4/5 - Current Mode PWM 

Controllers 



PRODUCT SELECTOR 



(Transistors, Diodes and TO-240 Modules 



3 PHASE BRIDGE INVERTER 




380V ~ 


■ ■ — 

220V ~ 


96V 


48V 


Type 


Nom. 
KVA 


Type 


Nom. 
KVA 


Type 


Nom. 
KVA 


Type 


Nom. 
KVA 


SGS30DA070D 
SGS25DB080D 
SGS15DB080D 
BUX98C 
BUX48C 

SGS35R120 


36 
30 
22 
13 
6 

30 


SGS50DA045D 

SGS40TA045D 

SGS30DB045D 

SGS30MA050D1 

SGSD310 

SGSD00030 

BUX98A 

BUX48A 
SGSP574/474 
SGSP579/479 

2N7059 

BUW42 

BUW32 

BUW22 
SGS60R40 


45 
36 
22 
18 

8 

7 

8 

4.5 

5 

3 

4 

6 

3.6 

2.2 
26 


SGS100DA025D 

BUR51 

2N7056 
SGSP577/477 
SGSP567/467 

SGS20R20 


20 
5.0 
2.5 
2.5 

1.0 

6.0 


SGS150MA010D1 

BUR50 
SGSP571/471 
SGSP561/461 

SGS20R10 


12 
3.5 
1.5 
1.0 

3.0 



SINGLE PHASE BRIDGE INVERTER 




380V ~ 


220V ~ 


96V 


48V 


Type 


Nom. 
KVA 


Type 


Nom. 
KVA 


Type 


Nom. 
KVA 


Type 


Nom. 
KVA 


SGS30DA070D 


30 


SGS50DA045D 


37 


SGS100DA025D 


20 


SGS150MA010D1 


12 


SGS25DB080D 


24 


SGS40TA045D 


30 


BUR51 


5 


BUR50 


3.5 


SGS15DB080D 


15 


SGS30DB045D 


15 


2N7056 


2.5 


SGSP57 1/471 


1.5 


BUX98C 


10 


SGS30MA050D1 


15 


SGSP577/477 


2.5 


SGSP561/461 


1.0 


BUX48C 


5 


SGSD310 
SGSD00030 
BUX98A 
BUX48A 
SGSP574/474 
SGSP579/479 
2N7059 
BUW42 
BUW32 
BUW22 


7 

6 

6 

3 

5 

2.5 

4 

5 

3 

1.8 


SGSP567/467 


1.0 






SGS35R120 


30 


SGS60R40 


26 


SGS20R20 


6.0 


SGS20R10 


3.0 



10 



PRODUCT SELECTOR (Transistors, Diodes and TO-240 Modules) 



DC MOTORS 




220V ~ 


96V 


48V 


28V 


Type 


Norn. 
KVA 


Type 


Nom. 
KVA 


Type 


Nom. 
KVA 


Type 


Rating, 
A 


SGS50DA045D 

SGS40TA045D 

SGS30MA050D1 

SGSP574/474 

SGSP579/479 

2N7059 
SGSD310 

BUX98A 

BUX48A 

BUW42 

BUW32 

BUW22 


15 

12 
4.0 
1.8 
1.5 
1.5 
4.0 
5.0 
2.5 
2.5 
1.5 
1.0 


SGS100DA025D 

BUR51 
SGSP577/477 
SGSP567/467 

2N7056 


10 
3.0 
1.0 
0.5 
1.0 


SGS150MA010D1 

BUR50 
SGSP57 1/471 
SGSP561/461 


3.5 
2.0 
0.7 
0.4 


SGSP592/492 
SGSP482/382 
SGSP422/322 
SGSP358 


25.0 

15.0 

6.5 

4.0 



STEPPER MOTORS 




200V 


96V 


48V 


28V 


Type 


Config. 
Rating, A 


Type 


Config. 
Rating, A 


Type 


Config. 
Rating, A 


Type 


Config. 
Rating,A 


BUR20 

BUV21 

BUV22 

BUX11 
SGSP573/473 
SGSP463/363 
SGSP516/316 


25.0 

12.0 

10.0 

6.0 

13.0 

6.5 

3.5 


BUR50 

BUV20 

BUX10P 

BDX53F 

BDX54F 

SGSP577/477 

SGSP467/367 

SGSP517/317 


35.0 

25.0 

10.0 

2.0 

-2.0 

13.0 

6.5 

3.5 


SGSD100 

SGSD200 
BDW93C 
BDW94C 
BDX53C 
BDX54C 

SGS132 

SGS137 

SGSP572/472 

SGSP562/362 

SGSP512/312 

SGSP352 


10.0 
-10.0 

5.0 
-5.0 

3.0 
-3.0 

4.0 
-4.0 
19.0 
10.0 

4.5 

3.0 


BDW93 

BDW94 
SGSP386 
SGSP592/492 
SGSP482/382 
SGSP422/322 
SGSP358 


5.0 
-5.0 
25.0 
25.0 
15.0 
6.5 
3.0 



11 



PRODUCT SELECTOR 



PART NUMBER IDENTIFICATION 



(Transistors, Diodes and TO-240 Modules) 



SGS DB 




types are 


SGS DA 




types are 


SGS TA 


D 


types are 


SGS MA 


D1 


types are 


SGSD 




types are 


SGSP5 




types are 


SGSP4 




types are 



TO-240 Darlington Transistor Half-bridge modules with fast freewheel diode. 

TO-240 Darlington Transistor Quarter-bridge modules with fast freewheel diode. 

TO-240 Transistor Quarter-bridge modules with fast freewheel diode. 

TO-240 Power Mos Transistor Quarter-bridge modules with normal freewheel diode. 

TO-3 and SOT-93 Darlington Transistors with inactive collector-emitter diode. 

TO-3 Power Mos Transistors. 

SOT-93 Power Mos Transistors. 



SEMI-CUSTOM TRANSPACK 

The existing standard Transpack range of power modules consists of 15 bipolar versions and 4 types 
containing POWER MOS devices. These types cover a large quantity of customer needs but the increase 
in sophistication of high power designs has led to numerous requests for minor variations to SGS 
standard types. 

With the introduction of the SGS Semi-Custom Series, customers can include unique design variations 
and end up with a high power module which is customised to their own needs. To support this new 
phase of high power modules SGS has identified 40 basic designs utilising advanced silicon manufac- 
tured on our high volume lines. The maximum ratings for each design are based on using the maximum 
number of chips within the chosen internal layout. 

For maximum flexibility SGS Semi-Custom Transpack modules can be configured to the customers 
own unique circuit design using SGS power devices, this option is limted only by some straightforward 
design rules, and the package pinning. 
Customer supplied silicon can also be included in this customised option. 



This Product Selector Guide illustrates only a small selection of products and package types available 
from SGS. Consult your local SGS sales office for further information. 

12 



ALPHANUMERICAL INDEX 



13 



ALPHANUMERICAL INDEX 



Type 



Functions 



Page 



AM26LS31 

AM26LS32 

AM26LS33 

AM6012 

AM6012A 

BUR50 

BUR50S 

BUR51 

BUR52 

BUV48 

BUV48A 

BUV48B 

BUV48C 

BUW22 

BUW22A 

BUW22AP 

BUW22P 

BUW32 

BUW32A 

BUW32AP 

BUW32P 

BUW42 

BUW42A 

BUW42AP 

BUW42P 

BUX48 

BUX48A 

BUX48B 

BUX48C 

BUX98 

BUX98A 

BUX98C 

BYW29-50 

BYW29-100 

BYW29-150 

BYW29-200 

DAC0806 

DAC0807 

DAC0808 

GS-D200 

L149 

L165 

L200 

L272 

L272M 

L290 

L291 

L292 

L293 

L293C 



QUAD HIGH SPEED DIFFERENTIAL LINE DRIVER 313 

RS422 AND RS423 QUAD DIFFERENTIAL LINE RECEIVER 317 

RS422 AND RS423 QUAD DIFFERENTIAL LINE RECEIVER 317 

12 BIT HIGH SPEED MULTIPLYING D/A CONVERTERS 321 

12 BIT HIGH SPEED MULTIPLYING D/A CONVERTERS 321 

HIGH CURRENT, HIGH SPEED, HIGH POWER NPN TRANSISTOR .... 889 

HIGH CURRENT, HIGH SPEED, HIGH POWER NPN TRANSISTOR .... 889 

HIGH CURRENT, HIGH SPEED, HIGH POWER NPN TRANSISTOR .... 895 

HIGH CURRENT, HIGH SPEED, HIGH POWER NPN TRANSISTOR .... 901 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 925 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 925 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 933 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 933 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 907 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 907 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 907 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 907 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 915 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 915 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 915 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 915 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 921 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 921 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 921 

HIGH VOLTAGE POWER SWITCHING PNP TRANSISTOR 921 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 925 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 925 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 933 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 933 

HIGH VOLTAGE FAST SWITCHING TRANSISTOR 939 

HIGH VOLTAGE FAST SWITCHING TRANSISTOR 939 

HIGH VOLTAGE FAST SWITCHING TRANSISTOR 941 

HIGH SWITCHING SPEED RECTIFIER 945 

HIGH SWITCHING SPEED RECTIFIER 945 

HIGH SWITCHING SPEED RECTIFIER 945 

HIGH SWITCHING SPEED RECTIFIER 945 

6 BIT D/A CONVERTERS 333 

7 BIT D/A CONVERTERS 333 

8 BIT D/A CONVERTERS 333 

SWITCH MODE BIPOLAR STEPPER MOTOR DRIVER MODULE 1115 

4A LINEAR DRIVER 345 

3A POWER OPERATIONAL AMPLIFIER 349 

ADJUSTABLE VOLTAGE AND CURRENT REGULATOR 355 

DUAL POWER OPERATIONAL AMPLIFIER 365 

DUAL POWER OPERATIONAL AMPLIFIER 365 

TACHOMETER CONVERTER 371 

5 BIT D/A CONVERTER AND POSITION AMPLIFIER 377 

SWITCH-MODE DRIVER FOR DC MOTORS 383 

PUSH-PULL FOUR CHANNEL DRIVER 395 

PUSH-PULL FOUR CHANNEL/DUAL H-BRIDGE DRIVER 403 

14 



ALPHANUMERICAL INDEX 



(continued) 



Functions 



Page 



PUSH-PULL FOUR CHANNEL DRIVER WITH DIODES 407 

PUSH-PULL FOUR CHANNEL DRIVER 395 

SWITCH-MODE SOLENOID DRIVER 411 

DUAL SWITCH-MODE SOLENOID DRIVER 417 

HIGH CURRENT SWITCHING REGULATOR 423 

HIGH CURRENT SWITCHING REGULATOR 423 

STEPPER MOTOR CONTROLLER 443 

STEPPER MOTOR CONTROLLER 443 

DUAL FULL-BRIDGE DRIVER 453 

VERY LOW DROP 5V REGULATOR 459 

DARLINGTON ARRAY 463 

DARLINGTON ARRAY 463 

DARLINGTON ARRAY 463 

DARLINGTON ARRAY 463 

2A QUAD DARLINGTON SWITCH 467 

LOW DROP DUAL POWER OPERATIONAL AMPLIFIER 471 

LOW DROP DUAL POWER OPERATIONAL AMPLIFIER 471 

PRINTER SOLENOID DRIVER 479 

DUAL 5V REGULATOR WITH RESET 483 

DUAL 5V REGULATOR WITH RESET AND DISABLE FUNCTIONS ... 493 

DUAL 5V REGULATOR WITH RESET AND DISABLE FUNCTIONS ... 503 

DUAL 5V REGULATOR WITH RESET 511 

VERY LOW DROP ADJUSTABLE REGULATOR 519 

VERY LOW DROP ADJUSTABLE REGULATOR 519 

VERY LOW DROP 1A REGULATOR 523 

2.5A POWER SWITCHING REGULATOR 529 

1.5A POWER SWITCHING REGULATOR 543 

SOLENOID CONTROLLER 555 

100V-1A. QUAD DMOS POWER SWITCH 567 

100V-1A, QUAD DMOS POWER SWITCH 567 

100V-1A, QUAD DMOS POWER SWITCH 567 

1.5A DMOS FULL BRIDGE DRIVER 571 

3A DMOS FULL BRIDGE DRIVER 579 

DUAL FULL BRIDGE DRIVER 587 

3A FULL BRIDGE DRIVER WITH DIODES 593 

DUAL SCHOTTKY DIODE BRIDGE 599 

HIGH CURRENT SOLENOID DRIVER 603 

STEPPER MOTOR DRIVER 609 

STEPPER MOTOR DRIVER 617 

QUAD DARLINGTON SWITCH 625 

QUAD DARLINGTON SWITCH 625 

QUAD TRANSISTOR SWITCH 629 

BIDIRECTIONAL THREE-PHASE BRUSHELESS DC MOTOR DRIVER . 633 

THREE-PHASE BRUSHLESS DC MOTOR DRIVER 641 

PHASE LOCKED FREQUENCY CONTROLLER 649 

HAMMER SOLENOID CONTROLLER 657 

SOLENOID CONTROLLER 663 

CURRENT CONTROLLER FOR STEPPING MOTORS 671 

2-CHANNEL FLOPPY DISK READ/WRITE CIRCUIT 677 

2-CHANNEL FLOPPY DISK READ/WRITE CIRCUIT 677 

15 



ALPHANUMERICAL INDEX 



(continued) 



Type 



Functions 



Page 



L7150 

L7152 

L7180 

L7182 

L9222 

L9305A 

L9305C 

L9306 

L9306C 

L9335 

L9336 

L9342 

L9350 

M5450 

M5451 

M5480 

M5481 

M5482 

MC1488 

MC1489 

MC1489A 

MC3479C 

MJE 13006 

MJE 13007 

MJE13007A 

PBL3717A 

SG1524 

SG1525A 

SG1527A 

SG2524 

SG2525A 

SG2527A 

SG3524 

SG3525A 

SG2527A 

SGS8R05 

SGS8R10 

SGS8R15 

SGS8R20 

SGS15DB070D 

SGS15DB080D 

SGS16DR05 

SGS16DR10 

SGS16DR15 

SGS16DR20 

SGS20R05 

SGS20R10 

SGS20R15 

SGS20R20 

SGS25DB070D 



50V QUAD DARLINGTON SWITCH 683 

50V QUAD DARLINGTON SWITCH 683 

80V QUAD DARLINGTON SWITCH 687 

80V QUAD DARLINGTON SWITCH 687 

QUAD INVERTING TRANSISTOR SWITCHES 691 

DUAL HIGH CURRENT RELAY DRIVER 695 

DUAL HIGH CURRENT RELAY DRIVER 695 

DUAL RELAY DRIVER 699 

DUAL RELAY DRIVER 699 

SOLENOID DRIVER 703 

SOLENOID DRIVER 703 

SIX-SOLENOID DRIVER 707 

LOW SATURATION DRIVER 713 

LED DISPLAY DRIVER 719 

LED DISPLAY DRIVER 719 

LED DISPLAY DRIVER 727 

LED DISPLAY DRIVER 733 

LED DISPLAY DRIVER 739 

RS232C QUAD LINE DRIVER 745 

QUAD LINE RECEIVER 751 

QUAD LINE RECEIVER 751 

STEPPER MOTOR DRIVER 757 

MOTOR CONTROL, SWITCHING REGULATOR NPN TRANSISTOR ... 947 

MOTOR CONTROL, SWITCHING REGULATOR NPN TRANSISTOR ... 947 

MOTOR CONTROL, SWITCHING REGULATOR NPN TRANSISTOR ... 947 

STEPPER MOTOR DRIVER 765 

REGULATING PULSE WIDTH MODULATOR 775 

REGULATING PULSE WIDTH MODULATOR 781 

REGULATING PULSE WIDTH MODULATOR 781 

REGULATING PULSE WIDTH MODULATOR 775 

REGULATING PULSE WIDTH MODULATOR 781 

REGULATING PULSE WIDTH MODULATOR 781 

REGULATING PULSE WIDTH MODULATOR 775 

REGULATING PULSE WIDTH MODULATOR 781 

REGULATING PULSE WIDTH MODULATOR 781 

HIGH SWITCHING SPEED RECTIFIER 957 

HIGH SWITCHING SPEED RECTIFIER 957 

HIGH SWITCHING SPEED RECTIFIER 957 

HIGH SWITCHING SPEED RECTIFIER 957 

TRANSPACK NPN POWER DARLINGTON MODULE 961 

TRANSPACK NPN POWER DARLINGTON MODULE 961 

HIGH SWITCHING SPEED RECTIFIER 969 

HIGH SWITCHING SPEED RECTIFIER 969 

HIGH SWITCHING SPEED RECTIFIER 969 

HIGH SWITCHING SPEED RECTIFIER 969 

HIGH SWITCHING SPEED RECTIFIER 973 

HIGH SWITCHING SPEED RECTIFIER 973 

HIGH SWITCHING SPEED RECTIFIER 973 

HIGH SWITCHING SPEED RECTIFIER 973 

TRANSPACK NPN POWER DARLINGTON MODULE 975 

16 



ALPHANUMERICAL INDEX 



(continued) 



Type 



Functions 



Page 



SGS25DB080D 

SGS30DA060D 

SGS30DA070D 

SGS30DB040D 

SGS30DB045D 

SGS30MA050D1 

SGS35MA050D1 

SGS35R120 

SGS40TA045 

SGS40TA045D 

SGS45R80 

SGS50DA045D 

SGS50DB040D 

SGS50DB045D 

SGS60R40 

SGS80DA020D 

SGS100DA025D 

SGS100MA010D1 

SGS150MA010D1 

SGS 10004 

SGS10004P 

SGS10005 

SGS10005P 

SGSD00030 

SGSD00031 

SGSD310 

SGSD311 

SGSID311 

SGSID312 

SGSIP464 

SGSIP465 

SGSIP466 

SGSIP468 

SGSIP469 

SGSIP473 

SGSIP474 

SGSIP475 

SGSIP476 

SGSIP477 

SGSIP478 

SGSIP479 

SGSIV48 

SGSIV48A 

SGSIV48C 

SGSIW32 

SGSIW32A 

SGSIW42 

SGSIW42A 

SGSP221 

SGSP222 



TRANSPACK NPN POWER DARLINGTON MODULE 975 

TRANSPACK NPN POWER DARLINGTON MODULE 983 

TRANSPACK NPN POWER DARLINGTON MODULE 983 

TRANSPACK NPN POWER DARLINGTON MODULE 991 

TRANSPACK NPN POWER DARLINGTON MODULE 991 

TRANSPACK N-CHANNEL POWER MOS MODULE 999 

TRANSPACK N-CHANNEL POWER MOS MODULE 1003 

HIGH SWITCHING SPEED RECTIFIER 1007 

TRANSPACK NPN POWER TRANSISTOR MODULE 1009 

TRANSPACK NPN POWER TRANSISTOR MODULE 1009 

HIGH SWITCHING SPEED RECTIFIER 1017 

TRANSPACK NPN POWER DARLINGTON MODULE 1019 

TRANSPACK NPN POWER DARLINGTON MODULE 1027 

TRANSPACK NPN POWER DARLINGTON MODULE 1027 

HIGH SWITCHING SPEED RECTIFIER 1035 

TRANSPACK NPN POWER DARLINGTON MODULE 1037 

TRANSPACK NPN POWER DARLINGTON MODULE 1045 

TRANSPACK N-CHANNEL POWER MOS MODULE 1051 

TRANSPACK N-CHANNEL POWER MOS MODULE 1055 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1059 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1059 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1059 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1059 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1063 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1063 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1069 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1069 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1069 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 1063 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1087 

HIGH SPEED SWITCHING POWER MOS 1087 

HIGH SPEED SWITCHING POWER MOS 1095 

HIGH SPEED SWITCHING POWER MOS 1099 

HIGH SPEED SWITCHING POWER MOS 1099 

HIGH SPEED SWITCHING POWER MOS 1099 

HIGH SPEED SWITCHING POWER MOS 1095 

HIGH SPEED SWITCHING POWER MOS 1103 

HIGH SPEED SWITCHING POWER MOS 1103 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 925 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 925 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 933 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 915 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 915 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 921 

HIGH VOLTAGE POWER SWITCHING NPN TRANSISTOR 921 

HIGH SPEED SWITCHING POWER MOS 1075 

HIGH SPEED SWITCHING POWER MOS 1075 

17 



ALPHANUMERICAL INDEX 



(continued) 



Type 



Functions 



Page 



SGSP321 

SGSP322 

SGSP363 

SGSP364 

SGSP365 

SGSP366 

SGSP367 

SGSP368 

SGSP369 

SGSP386 

SGSP387 

SGSP421 

SGSP422 

SGSP463 

SGSP464 

SGSP465 

SGSP466 

SGSP467 

SGSP468 

SGSP469 

SGSP473 

SGSP474 

SGSP475 

SGSP476 

SGSP477 

SGSP478 

SGSP479 

SGSP486 

SGSP487 

SGSP521 

SGSP522 

SGSP563 

SGSP564 

„GSP565 

SGSP566 

SGSP567 

SGSP568 

SGSP569 

SGSP573 

SGSP574 

SGSP575 

SGSP576 

SGSP577 

SGSP578 

SGSP579 

SGSP586 

SGSP587 

TDA4601 

TDA7272 

TDA8115 



HIGH SPEED SWITCHING POWER MOS 1075 

HIGH SPEED SWITCHING POWER MOS 1075 

HIGH SPEED SWITCHING POWER MOS 1079 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1079 

HIGH SPEED SWITCHING POWER MOS 1087 

HIGH SPEED SWITCHING POWER MOS 1087 

HIGH SPEED SWITCHING POWER MOS 1091 

HIGH SPEED SWITCHING POWER MOS 1091 

HIGH SPEED SWITCHING POWER MOS 1075 

HIGH SPEED SWITCHING POWER MOS 1075 

HIGH SPEED SWITCHING POWER MOS 1079 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1079 

HIGH SPEED SWITCHING POWER MOS 1087 

HIGH SPEED SWITCHING POWER MOS 1087 

HIGH SPEED SWITCHING POWER MOS 1095 

HIGH SPEED SWITCHING POWER MOS 1099 

HIGH SPEED SWITCHING POWER MOS 1099 

HIGH SPEED SWITCHING POWER MOS 1099 

HIGH SPEED SWITCHING POWER MOS 1095 

HIGH SPEED SWITCHING POWER MOS 1103 

HIGH SPEED SWITCHING POWER MOS 1103 

HIGH SPEED SWITCHING POWER MOS 1091 

HIGH SPEED SWITCHING POWER MOS 1091 

HIGH SPEED SWITCHING POWER MOS 1075 

HIGH SPEED SWITCHING POWER MOS 1075 

HIGH SPEED SWITCHING POWER MOS 1079 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1083 

HIGH SPEED SWITCHING POWER MOS 1079 

HIGH SPEED SWITCHING POWER MOS 1087 

HIGH SPEED SWITCHING POWER MOS 1087 

HIGH SPEED SWITCHING POWER MOS 1095 

HIGH SPEED SWITCHING POWER MOS 1099 

HIGH SPEED SWITCHING POWER MOS 1099 

HIGH SPEED SWITCHING POWER MOS 1099 

HIGH SPEED SWITCHING POWER MOS 1095 

HIGH SPEED SWITCHING POWER MOS 1103 

HIGH SPEED SWITCHING POWER MOS 1 103 

HIGH SPEED SWITCHING POWER MOS 1091 

HIGH SPEED SWITCHING POWER MOS 1091 

SWITCH-MODE POWER SUPPLY CONTROLLER 791 

FULL BRIDGE DC MOTOR REGULATOR 799 

DUAL MOTOR DRIVER 815 

18 



ALPHANUMERICAL INDEX 



.continued) 



Type 


Functions 


Page 


TDA8116 


FOUR PHASE BRUSHLESS MOTOR DRIVER 


819 


TDA8130 


CURRENT MODE PWM CONTROLLER 


823 


TDA8132 


CURRENT MODE PWM CONTROLLER 


829 


TL7700 series 


SUPPLY VOLTAGE SUPERVISORS 


835 


UC1840 


PROGRAMMABLE, OFF-LINE, PWM CONTROLLER ... 


839 


UC1842 


CURRENT MODE PWM CONTROLLER .... 


. . . 849 


UC1843 


CURRENT MODE PWM CONTROLLER . 


849 


UC1844 


CURRENT MODE PWM CONTROLLER . 


849 


UC1845 


CURRENT MODE PWM CONTROLLER .... 


849 


UC2840 


PROGRAMMABLE, OFF-LINE, PWM CONTROLLER 


839 


UC2842 


CURRENT MODE PWM CONTROLLER . 


849 


UC2843 


CURRENT MODE PWM CONTROLLER . . 


849 


UC2844 


CURRENT MODE PWM CONTROLLER 


.... 849 


UC2845 


CURRENT MODE PWM CONTROLLER . 


849 


UC3840 


PROGRAMMABLE, OFF-LINE, PWM CONTROLLER 


839 


UC3842 


CURRENT MODE PWM CONTROLLER 


849 


UC3843 


CURRENT MODE PWM CONTROLLER 


849 


UC3844 


CURRENT MODE PWM CONTROLLER . 


849 


UC3845 


CURRENT MODE PWM CONTROLLER . 


849 


ULN2001A 


SEVEN DARLINGTON ARRAY 


857 


ULN2002A 


SEVEN DARLINGTON ARRAY 


857 


ULN2003A 


SEVEN DARLINGTON ARRAY 


857 


ULN2004A 


SEVEN DARLINGTON ARRAY 


857 


ULN2064B 


50V-1.5A QUAD DARLINGTON SWITCH 


. . . . 861 


ULN2065B 


80V QUAD DARLINGTON SWITCH ... 


869 


ULN2066B 


50V QUAD DARLINGTON SWITCH .... 


861 


ULN2067B 


80V QUAD DARLINGTON SWITCH .... 


869 



ULN2068B 

ULN2069B 

ULN2070B 

ULIU2071B 

ULN2074B 

ULN2075B 

ULN2076B 

ULN2077B 

ULN2801A 

ULN2802A 

ULN2803A 

ULN2804A 

ULN2805A 

ULQ2001R 

ULQ2002R 

ULQ2003R 

ULQ2004R 

VB010 

VB100 

2N7056 

2N7059 



50V QUAD DARLINGTON SWITCH 861 

80V QUAD DARLINGTON SWITCH 869 

50V QUAD DARLINGTON SWITCH 861 

80V QUAD DARLINGTON SWITCH 869 

50V QUAD DARLINGTON SWITCH 861 

80V QUAD DARLINGTON SWITCH 869 

50V QUAD DARLINGTON SWITCH 861 

80V QUAD DARLINGTON SWITCH 869 

EIGHT DARLINGTON ARRAY 875 

EIGHT DARLINGTON ARRAY 875 

EIGHT DARLINGTON ARRAY 875 

EIGHT DARLINGTON ARRAY 875 

EIGHT DARLINGTON ARRAY 875 

SEVEN DARLINGTON ARRAY 881 

SEVEN DARLINGTON ARRAY 881 

SEVEN DARLINGTON ARRAY 881 

SEVEN DARLINGTON ARRAY 881 

HIGH VOLTAGE INTELLIGENT DARLINGTON 885 

HIGH VOLTAGE INTELLIGENT CONTROLLER 887 

HIGH SPEED SWITCHING POWER MOS 1107 

HIGH SPEED SWITCHING POWER MOS 1111 






19 



APPLICATION NOTES 



21 



APPLICATION NOTES INDEX 



Page 

NEW DEVELOPMENTS IN INTELLIGENT POWER TECHNOLOGY 25 

A HIGH EFFICIENCY, MIXED-TECHNOLOGY MOTOR DRIVER 33 

STEPPER MOTOR DRIVING 39 

CONSTANT-CURRENT CHOPPER DRIVE UPS STEPPER-MOTOR PERFORMANCE 53 

USING THE L6506 FOR CURRENT CONTROL OF STEPPING MOTORS 57 

HIGH-POWER, DUAL-BRIDGE ICs EASE STEPPER-MOTOR-DRIVE DESIGN 61 

INTRODUCING THE L297 STEPPER MOTOR CONTROLLER 69 

APPLICATIONS OF MONOLITHIC BRIDGE DRIVERS 83 

SWITCH-MODE DRIVERS FOR SOLENOID DRIVING 91 

SPEED CONTROL OF DC MOTORS WITH THE L292 SWITCH-MODE DRIVER 101 

A DESIGNER'S GUIDE TO THE L290/L291/L292 DC MOTOR SPEED/POSITION CONTROL 

SYSTEM 1 07 

DESIGNING WITH THE L296 MONOLITHIC POWER SWITCHING REGULATOR 127 

DESIGNING MULTIPLE-OUTPUT POWER SUPPLIES WITH THE L296 AND L4960 163 

DUAL REGULATORS SIMPLIFY MICRO SYSTEM SUPPLY DESIGN 173 

UC3842 PROVIDES LOW-COST CURRENT-MODE CONTROL 179 

A 25W OFF-LINE FLYBACK SWITCHING REGULATOR 191 

APPLYING THE UC1840 TO PROVIDE TOTAL CONTROL FOR LOW-COST, PRIMARY- 
REFERENCED SWITCHING POWER SYSTEMS 195 

50W OFF-LINE SWITCHING POWER SUPPLY USING THE UC3840 205 

A SECOND-GENERATION IC SWITCH MODE CONTROLLER OPTIMIZED FOR HIGH 

FREQUENCY POWER MOS DRIVE 217 

A DESIGNER'S GUIDE TO THE L200 VOLTAGE REGULATOR 227 

CONTROL OF A DC MOTOR USING TRANSPACK 243 

TRANSISTOR OVERSTRESS IN BRIDGE CIRCUITS FOR MOTOR CONTROL APPLICA- 
TIONS 265 

PARALLELING TRANSPACK MODULES 271 

ROBUSTNESS OF HIGH VOLTAGE POWER TRANSISTORS 275 

TECHNOLOGY RELIABILITY AND APPLICATIONS OF SGS HIGH VOLTAGE NPN TRAN 

SISTORS 279 

SECOND BREAKDOWN IN POWER TRANSISTORS 285 

SGS HIGH VOLTAGE FAST RECOVERY DIODES AND THEIR SWITCHING PERFORMANCE 291 

HANDLING AND MOUNTING ICs IN PLASTIC POWER PACKAGES 299 

DEVELOPMENTS IN SURFACE MOUNTING PACKAGES FOR POWER INTEGRATED 

CIRCUITS 303 



23 



NEW DEVELOPMENTS IN INTELLIGENT 
POWER TECHNOLOGY 



Recent developments in power IC technology greatly expand the capabilities of integrated 
circuits combining control circuits and high power drive stages. This note describes the new 
power processes, new packages and the latest generation of power ICs. 



those intelligent power technologies that have been 
developed from discrete transistor processes have a 
collector, or drain, contact on the lower surface of 
the die. A fundamental consequence of this struc- 
tural difference is that with processes of the first 
type it is possible to integrate any number of 
isolated power transistors and interconnect them in 
any configuration. SGS calls these Multipower pro- 
cesses. 

Where a bottom contact is used it is only possible 
to integrate a single power transistor, or several 
with common collectors (or drains), therefore 
configurations such as the H-bridge cannot be in- 
tegrated but higher current and voltage capability 
of several hundred volts is possible. SGS has named 
this type of process VIPower™ (Vertical Intelligent 
Power). Both technologies can be further sub- 
divided into those which are pure bipolar and 
mixed technologies containing a mixture of bipolar 
and MOS structures. In both fields significant pro- 
gress has been made recently. 



While chips integrating both signal and power ele- 
ments have been with us for several years, recent 
developments have greatly expanded the capa- 
bilities of these technologies. With the latest pro- 
cesses designers can integrate many circuits that 
were previously uneconomic or simply impossible. 
Moreover, the enlarged horizons of intelligent 
power technology — and packaging — are prompting 
new trends in the partitioning of systems. 

Not only are intelligent power ICs becoming more 
common, they are also becoming more intelligent, 
to the point where designers can aim to integrate a 
complete power subsystem. Moreover, the current 
and voltage capabilities of these technologies have 
increased dramatically, enlarging the field of appli- 
cations. 

Since system designers are often responsible for 
partitioning electronic systems and specifying new 
devices it is important for them to understand the 
capabilities of the latest technologies. This is now 
more true than ever, both because IC technology 
has advanced so rapidly and because the latest 
generation of power ICs have a much greater 
'system' content. 

THE NEW TECHNOLOGIES 

Intelligent power technologies have evolved from 
two earlier species: linear IC technology and dis- 
crete transistor technology. 

Processes of the first type are enhancements of the 
basic planar IC structure where all of the connec- 
tions are on the top surface of the chip. In contrast, 

Fig. 1 - Multipower-S 2 P 2 , a 60V bipolar process, combines linear, IIL logic, ICV PNP power transistors 
\and low leakage diodes. 



PURE BIPOLAR MULTIPOWER 
PROCESSES 

Just how far bipolar technology has advanced is 
illustrated by SGS' new Multipower-S 2 P 2 and 
Multipower-HDS 2 P 2 processes. 

Multipower-S 2 P 2 (figure 1 ) is a 60V process that 
integrates bipolar linear, IIL logic, NPN and PNP 
power transistors and a new low leakage diode 
structure. 



c c 



B E C 



p & \ A 



C E 



H K fl 




N H 




NPN 



ICU 



PNP 



LLD 



25 



One of the most important characteristics of this 
process is that it offers a new Isolated-Collector 
Vertical PNP (ICV PNP) structure which is much 
closer to discrete PNP transistors in performance 
terms than the usual lateral PNP type. These ICV 
PNP transistors provide, in fact, a current density 
of 0.8A/mm 2 at V sat = 1V — compared to 2A/mm 2 



for NPN types 
30MHz. 



and a cutoff frequency of 20 to 



The possibility of integrating high performance 
power PNP transistors on an intelligent power IC 
allows designers to choose any output configur- 
ation. Moreover, the ICV PNPs low voltage drop 
can be exploited for applications where drop-out 
is a critical parameter. Another advantage, specifi- 
cally for automotive applications, is that an ICV 
PNP output stage can withstand battery reversal 



indefinitely. 

Another important feature of Multipower-S 2 P 2 is 
the inclusion of a new low leakage diode structure 
that has a parasitic PNP gain about four orders of 
magnitude lower than conventional structures. This 
new structure is ideal for the recirculation diodes 
in high power ICs driving inductive loads such as 
motors and solenoids. 

The first device to be produced with this process is 
a relatively simple high side driver, the L9350, 
originally designed to the specification of a cus- 
tomer in the automotive electronics market (figure 
2). An ICV PNP output transistor is used in this 
device to obtain very low saturation, high gain 
(about 30 with 1 A output current) and the ability 
to withstand load dump transients. 



Fig. 2 - Designed primarily for automotive applications, the L9350 high side solenoid driver exploits 
Multipower-S 1 P 1 's ICV PNP structure to obtain very low saturation voltage. 

supplv 



SUBStRAtEQ3 




Another device realized with this technology is a 
single-chip alternator regulator (figure 3) which 
integrates for the first time all of the power and 
signal devices needed to regulate the output voltage 



of a car alternator. Perhaps the most interesting 
aspect of this IC is that it needs no external com- 
ponents. 



Fig. 3 - Another Multipower-S 1 P 2 
external components. 



design, the L9480 alternator regulator is a circuit which needs no 




26 



Multipower-HDS 2 P 3 (figure 4) is a similar pure 
bipolar process. Like Multipower-S 2 P 2 it integrates 
linear, ML, LLD and ICV PNP structures. In ad- 
dition it also offers ECL logic. 

But the most important characteristic of this pro- 
cess is high density. Dimensioned for 20V capa- 
bility, it is aimed at low voltage applications where 
more complex signal processing circuits are needed 
— up to 270 IIL gates can be shoehorned into one 
square millimeter of silicon. 

Multipower-HDS 2 P 2 is also characterized by an 



exceptionally high current density: 6A/mm 2 for 
NPN transistors; 2A/mm 2 for PNP (at V sat = 1V 
and H fe = 10). 

This process has been applied to produce a custom 
stepper motor control/drive chip, where the high 
density of the process allows translator and chop- 
per circuits to be integrated economically on the 
power drive chip. It is also used for a new 1.5A 
voltage regulator, the L4940, where the ICV PNP 
provides very low voltage drop and low quiescent 
current. 



Fig. 4 - Multipower HDS 2 P 2 is a 20V process characterized by very high density in the signal part (270 
IIL gates/mm 2 ) and exceptionally high current density. 

I B C C B E C CER( HKH 




^fl-ft 




IL 



NPN 



ICV 



MIXED MULTIPOWER TECHNOLOGY 

Another area where remarkable progress has been 
made is in mixed bipolar/MOS technology. Though 
several mixed technologies of the 'vertical' type are 
available, a much more significant development is 
SGS' Multipower-BCD process (figure 5), which 
combines linear, CMOS logic and DMOS power 
transistors without placing any limit on the num- 
ber and connection of the power devices. 

Thanks to the DMOS power transistors this process 
allows efficiencies above 95% and switching fre- 
quencies up to 500kHz. In addition, there are no 



PNP 



LLt 



secondary breakdown limitations, paralleling of 
devices is simpler and there is an intrinsic 'fast' 
recirculation diode in the power DMOS structure 
which is adequate for most applications. 
For intelligent power devices the very high ef- 
ficiency of power DMOS is an important advantage. 
The power output of a chip is limited by the maxi- 
mum dissipation allowed in the package. By reduc- 
ing dissipation in the chip it is possible to put 
power ICs in low cost packages with modest power 
handling capability. Alternatively, packaged in 
existing high power packages, DMOS chips can 
deliver hitherto unreachable power levels. 



Fig. 5 - A mixed technology, Multipower-BCD integrates linear, CMOS logic and power DMOS devices on 
the same chip. Unlike other mixed technologies it places no limit on the number or connection of the 
oower transistors. 

[) j '-j ; I j ^ ' : ^ . , '_ r n I '- B 5 G D 




27 



Morever, the saturation loss of a power DMOS 
transistor can be reduced by increasing the area. 
Designers therefore have the possibility of trading 
costly copper and aluminum, materials used in 
packages and heatsinks, for silicon, which tends to 
decrease in cost as wafer fabrication techniques are 
improved and automated. 

Another important way in which Multipower-BCD 
differs from pure bipolar technologies is that it 
allows the mixing of low voltage and medium 
voltage elements on the same chip: lateral DMOS 
transistors with a breakdown voltage of 60V can be 

Fig. 6 - A motor driver chip, the L6202, is the first product to be realized with the Multipower-BCD 
process. The DMOS H-bridge output of this chip delivers 1.5A at 54V but thanks to the high efficiency 
no heatsink is needed. 

OUT 1 OUT 2 
O 
L B00T1 c B0OT 2 



produced in an epitaxial layer dimensioned for 
20V linear and CMOS circuits. 

The first product to be developed using this pro- 
cess is the L6202 motor driver (figure 6), which 
uses four DMOS power transistors in a H-bridge 
output stage. 

Assembled in a powerdip package this device can 
deliver 1 .5A at 54V with no external heatsink. In 
the photograph, figure 7, the four DMOS power 
transistors can be clearly seen in the lower part of 
the die. 



Ih 



VOLTAGE 
REFERENCE 



L 



jio.sv 



W 



CHARGE 
PUMP 



rinEJch 



ts>Oiqi ! -<a 



THERMAL 
SHUTDOWN 



Fig. 7 - The four DMOS power transistors occupy about 2/3 of the L6202 die. 



t«ti 






I I ^ 

MKMjjja [(■ , ' ..CMP fSBR 




itsm 



33t!' 



28 



VERTICAL PROCESSES 

While the "Multipower" processes are more versa- 
tile SGS is also developing bipolar and mixed 
vertical technologies, called VIPower-M1 and 
VIPower-M2. 

VIPower-M1 (figure 8) combines 400V NPN power 
transistors and bipolar low voltage (up to 30V 
V ceo ) drive circuits, while VIPower-IV12 (figure 9) 
will offer 80V DMOS power transistors and mixed 
CMOS/bipolar drive circuits. 



Though these processes cannot be used for devices 
with bridge and half-bridge output stages, they 
offer higher voltage capability and VIPower-M2 
features a lower ON resistance than Multipower- 
BCD. 

VIPower-M2 is suitable for applications such as 
high current high side drivers and DC-DC conver- 
ters while VIPower-IVl1 is suitable for applications 
like high voltage solenoid drivers, motor drives and 
off-line power supplies. 



Fig. 8 - VIPower-Ml technology integrates 400V NPN power transistors and 30V drive circuitry. 

E B C EB B EC 

• • * ♦ • ••• 




POWER'COLLECTOR 

NPN POWER NPI 



PNP 



Fig. 9 - Another 'vertical' power process, VIPower-M2 combines 80V DMOS power transistors and mixed 
CMOS/bipolar drive circuits. 

5G 5&D 5&D C EB C E B S&D 

• • ••• *•• ••• j • • T • * 




D 



POWER DMOS 



CMOS 



PNP P-CH MOS 



[The first products proposed in VIPower-M1 are 
400V 5A to 10A NPN darlington switches (figure 
10) with direct logic compatible drive. In addition 
Dn chip thermal, overcurrent and overvoltage 



sensing can shutdown the power switch and 
provide a diagnostic output to inform the system 
microprocessor of the overload condition. 



29 



CHOOSING THE RIGHT PROCESS 

The choice of process depends on the output stage 
configuration, current, voltage and the complexity 
of the signal processing section. 

Mixed bipolar/DMOS is the best for lower current 
devices where the signal processing circuitry is very 
comples. Pure bipolar processes, in contrast, are 
better for low voltage, high current applications 
because the current density is much greater. How- 
ever future developments of Multipower-BCD are 
likely to erode this advantage in a few years. 

One area where mixed technology will not replace 
pure bipolar processes completely is automotive 
electronics. This is because of the high energy load 
dump transients which occur on the battery rail. 



To withstand these transients a DMOS technology 
must have a BV^j breakdown voltage greater than 
the peak dump voltage, while a bipolar NPN transis- 
tor can be turned off to take advantage of the 
BV C b breakdown voltage, which is much greater 
then the BV ceo breakdown voltage. 

Mixed bipolar/DMOS technology will become in- 
creasingly important in very complex power de- 
vices. In the near future the Multipower-BCD pro- 
cess will be applied to produce specialized periph- 
eral drivers, optimized for one load type. Multi- 
power-BCD is ideal for these applications because 
it offers high precision bipolar linear circuits (for 
signal conditioning etc), high density CMOS (for 
complex logic) and high efficiency DMOS (for the 
power stage). 



Fig. 10 - VIPower-M1 wi 
rectly to standard logic. 



II be used to produce a 400V /TO A NPN darlington switch which connects di- 



Cso 



_*tt 



tHERMAL 
S.O. 




POWER PACKAGE DEVELOPMENTS 

For a power ICthe package is extremely important, 
since it determines both the power capability and 
the cost. 

At present SGS assembles most high power ICs of 
the Multipower type in power-tab packages like 
the Pentawatt, Heptawatt and Multiwatt® (which 
are attached to a heatsink), or in special DIP 
packages with a leadframe designed to reduce 
thermal resistance. AM of these packages are 
'insertion' types. However, several trends have now 
emerged which call for the design of completely 
new power packages. 

Firstly, the increasingly widespread use of surface 
mounting techniques and automatic assembly has 
brought the need for surface mounting power 
packages. For medium power (up to 2W) one 
solution, which SGS already has in production, is a 
plastic chip carrier with a special leadframe. 



Derived from the 44-lead PCC, this package uses 
33 leads for connections and the other 11 leads to 
transfer heat to the substrate (figure 11). This 
package has a junction-case thermal resistance of 
less tha 7'C/W, allowing dissipation up to 2W. 

For higher power devices development is concen- 
trated on a new generation of packages. One 
package family being studied (figure 12) has a 
junction-case thermal resistance of less than 5'C/W, 
3-17 pins and a lead spacing of 50mils. These 
packages will have an SO-width body and gull- 
wing leads, allowing the use of SO package hand- 
ling equipment. The low thermal resistance of 
these packages is obtained by a copper heat 
spreader on the lower surface of the package. When 
the package is soldered in place the spreader is in 
contact with the substrate. Clearly the amount of 
power that can be dissipated in the device depends 
on the conductivity of the substrate. 



30 



Fig. 11 - The leadframe of a plastic chip carrier can be modified to reduce thermal resistance. This '33+11' 
lead configuration allows power dissipation up to 2W 

' ' t B .# «... 






Fig. 12 - For power dissipation above 2W new surface mounting packages are being developed. This type, 
compatible with SO-package handling equipment, has a thermal resistance of about 5°C/W. 




PCB 



Copper 



In view of this trend there is now considerable in- 
terest in high conductivity substrates and the 
various alternatives, such as a plastic board bonded 
to an aluminum or copper sheet. Piated-through 
holes in the PCB reduce the thermal resistance 
between the package and the metal sheet. 



Another development area is the inclusion of a 
copper heat spreader on the under-side of plastic 
chip carriers. These power chip carriers will, like 
many new packages, be pre-molded types, which 
eliminates stress on the die caused by polym- 
erization shrinkage of the molding resin. 



New packaging concepts are being studied for chips 
like the L9480 which need no external compo- 
nents. Since there is no need to mount such devices 
on a substrate they will probably be assembled in 
packages designed to be bolted to the load (figure 
13) and equipped with 'Faston'-type connectors. 



Fig. 13 - New packaging concepts are being studied 
for 'silicon-only' circuits where there is no point 
in mounting the device on a conventional substrate 
because there are no other components needed. 




Fig. 14 - In the ISOWATT-21 8 package the copper 
frame is completely surrounded by molding resin 
to isolate the device from the heatsink. 




31 



ISOLATED PACKAGES 

ICs produced using VIPower™ technology pose 
a different problem because the lower surface of 
the die is the collector (or drain) contact and 
because greater heat dissipation capability is 
needed. For these ICs SGS is developing multi- 
lead versions of the ISOWATT-218™ plastic 
package (figure 14) where a copper frame is 



completely surrounded by molding resin — even 
on the lower surface — to provide electrical 
isolation. Low thermal resistance is assured by 
the thickness and high thermal conductivity of 
the resin. 

One of the new packages in development is shown 
in figure 15. This packages will achieve better 
than 2.5'C/W thermal resistance and 2500V 
AC isolation. 



Fig. 15 - Isolated packages with higher pin counts are in development 




32 



A HIGH EFFICIENCY, MIXED-TECHNOLOGY 
MOTOR DRIVER 

A new mixed technology called Multipower-BCD allows the integration of bipolar linear 
circuits, CMOS logic and DMOS power transistors on the same chip. This note describes a 
H-bridge motor driver I C realized with this technology. 



The miniaturization and integration of complex 
systems and subsystems has led in recent years to 
the implementation of monolithic circuits inte- 
grating logic functions and power sections. 

For these applications SGS has developed a new 
technology called Multipower BCD which allows 
the integration on the same chip of isolated Power 
DMOS elements, bipolar transistors and C-MOS 
logic. 

Thanks to high efficiency, fast switching speed and 
the absence of secondary breakdown, this tech- 
nology is particularly suitable for fast, high current 



solenoid drivers and high frequency switching 
motor control. The free-wheeling diode intrinsic to 
the DMOS structure (necessary if the device 
drives an inductive load) and the great flexibility 
available in the choice of the logic and driving sec- 
tion components allow the complete integration of 
power actuators without further expense in silicon 
area-and a compact implementation of complex 
signal functions. 

This technology has been applied to produce a 
switching power driver — the L6202/3 — capable 
of delivering 4A per phase, which is suitable for 
speed and position control in D.C. motor appli- 
cations. 



Fig. 1 - A schematic cross section of Bipolar, C-MOS, DMOS structures (BCD) 






• • • • •♦• ••• 



C L b 5 & D 
T T T T T T 



'V3 



rftft^l in^iJ "uJtiH ^T^ wM ^ WVr^ a J 







N P H . P P - 
MOP 



r i 



33 



MULTIPOWER BCD TECHNOLOGY 

Multipower BCD technology combines the well 
known vertical DMOS silicon gate process, used for 
discrete POWER MOS devices, and the standard 
junction isolation, sinker and buried layer process. 
The architecture of the process is centred around 
the vertical DMOS silicon gate, a self aligned struc- 
ture, which guarantees short channel length (1.5/Lim) 
with consequent low Rds(ON) f° r tne device. 

In standard IC technologies the voltage capability 
is determined essentially by the thickness of the 
epitaxial layer and it is the same for signal and 
power components. But if the epi thickness is in- 
creased to allow the inclusion of high voltage 
transistors even the linear dimension of small signal 
transistors must be increased proportionally. In 
contrast MULTIPOWER BCD permits the realiz- 
ation of high voltage lateral DMOS structures in an 
epi-layer dimensioned for low voltage bipolar 
linear elements. Thus it is possible to mix on the 
same die very dense CMOS logic, high precision 
bipolar linear circuits, very efficient DMOS power 
devices and high voltage lateral DMOS structures. 



In this way the constraints which limit the com- 
plexity of signal processing circuits that can be in- 
tegrated economically on a high chip are greatly 
reduced. 

The active structures available in Multipower BCD 
technology are represented in fig. 1. 

Within the vertical DMOS is indicated an intrinsic 
diode that can operate as a fast free-wheeling 
diode in switch mode applications. In fact DMOS, 
as a result of the way by which it is realized, is 
almost a symmetrical bidirectional device. That is, 
it can operate with the electrical l-V characteristic 
shown in the 3rd quadrant of fig. 2; that is, as a 
controlled resistor of value decreasing inversely 
with the gate source voltage applied to the power 
to which it is associated, up to a minimum equal to 
the Rqs(on) °f tne device itself, shunted by the 
body-dram diode intrinsic to the structure that 
limits the negative excursion of Vrj S . Of the de- 
vices represented in fig. 1 the table 1 lists the 
electrical characteristics. 



Table 1 : DEVICES IN MULTIPOWER BCD TECHNOLOGY 



• Vertical DMOS 


BV DSS > 60V 


V TH a 3V 


f T > 1GHz 


• Lateral DMOS 


BV DSS > 100V 


V TH s 3V 


f T > 800MHz 


• P-channel with Drain Extension 


BV DSS > 85V 


V TH ^ 3V 


f T > 200MHz 


• Bipolar NPN 


LV CEO > 20V 


(3 =35 


f T > 300MHz 


• Bipolar PNP 


LV CEO > 20V 


(3 =20 


f T > 7MHz 


• C-MOS N and P-channel 


BV DSS > 20V 


V TH = 3V 





Fig. 2 - l-V characteristic of DMOS N-channel 
power device 









T 




■HKauiiiMi 


, l i L_ 


m/AM&m 


I SOU 

I- *« 

I «V 

T 2 

f V 






W'- 
T'A 


^HOM 






r 




■ ; 


Wri 


TV — ' 


— |. j ■» * 


/7*Z 


'A 


I 




, br.A 


ri 






\WmfA 






wvd 


. . j i i 


■.■ \ ! ■ i 


t 

* 25fhr; 







THE L6202& L6203 H-BRIDGE DRIVERS 

Using this technology a H-bridge IC has been 
realized which accepts TTL or C-MOS compatible 
signals and is suitable for high efficiency, high fre- 
quency switching control of DC and stepping 
motor. The power stage consists of four DMOS N- 
channel transistors with Rds(ON) — 0.3fi. 

When this device is supplied with the maximum 
voltage of 60V it can deliver a DC current of 1 .5A 
in a standard DIP. 16 (L6202) and up to 5A in a 
MULTIWATT package (L6203). 

The device can also operate with a peak current of 
8A for a time interval essentially determined by 
the time constant of heat propagation (< 200 msl. 

The system diagram representing the internal func- 
tion blocks and external components (outside the 
dashed line) is shown in fig. 3. 



34 



Fig. 3 - L6202-6203 BLOCK DIAGRAM 



OUT 1 0UT2 

9 9 



ENABLE 





C BOOT 
II 


1 




' c B 


OOT 2 
II 






11 




*s 9 




VOLTAGE 
REFERENCE 

f 10.5V 










CHARGE 
PUMP 

1 1 

i 1 


















1 




_£ 






1 


-0-|>is 


a l-<-C^^- 




















THERMAL 
SHUTDOWN 




l 







IN 2 



1 SENSE 



The integrated circuit has 3 Inputs: Enable, Input 
1, Input 2. When Enable is "low" all power devices 
are off; when it is "high" their conduction state is 
controlled by the logic signals Input 1 and Input 2 
that drive independently a single branch of the full 
bridge. When Input 1 (Input 2) is "high" DMOS 1 
(DMOS 1') is "on" and DMOS 2 (DMOS 2') is 
"off", when is "low" DMOS 1 (DMOS V) is "off" 
and DMOS 2 (DMOS 2') is "on". 

A thermal protection circuit has been included that 
will disable the device if the junction temperature 
reaches 150°C. When the thermal protection is 
removed the device restarts under the control of 
the Input and Enable signals. 

ON-OFF SYNCHRONIZATION CIRCUIT 

ON-OFF synchronization of the power devices 
located on the same leg of the bridge must prevent 
simultaneous conduction, with obvious advantages 
in terms of power dissipation and of spurious 
signals on the ground and on sensing resistors. 

Because of the very short turn-on, turn-off times 
characteristic of POWER MOS devices a dead time 
(time in which all power transistors are "off") of 
40 ns is sufficient to prevent rail-to rail shorts. The 
circuit that provides this time interval is shown in 



fig. 4 with the voltage waveforms that explain how 
it works. Let us suppose Enable = "high". Because 
of the delay times introduced by IIW1 and INV2, 
V2 and V3 are two waveforms contained one in 
the other and of polarity suitable to assure that the 
turn-on of a power transistor happens only after 
the turn-off of the other. The gate voltages V5 and 
V6 of DM1 and DM2 are represented in fig. 5. In 
fig. 3 we can see also the modality of operation of 
the Enable signal, charge pump and bootstrap 
circuits. 

Concerning POWER MOS driving, it must be noted 
that it is necessary to assure to all DMOS N-channel 
a gate-source voltage of about 10V to guarantee 
full conduction of the POWER MOS itself. While 
there are no particular problems for driving the 
lower POWER MOS device (its terminals is referred 
to ground) for the upper one it is necessary to pro- 
vide a gate voltage higher than the positive supply 
because it has the drain connected to the positive 
supply itself. 

This is obtained using a system that combines a 
charge pump circuit, that assures DC operation, 
with a boostrapping technique suitable to provide 
high switching requencies, The circuit that satisfies 
to all these requirements is represented in the 
schematic diagram of fig. 6. 



35 



Fig. 4 - A schematic representation of ON-OFF synchronism circuit 




S- 9353/1 



Fig, 5 - POWER MOS gate voltage waveforms 




In the description of this circuit we can assume 
that C B oot ' s absent and IN commutes from the 
"low" to the "high" level. 

In this condition, by means of D1, the circuit 
charges immediately the DMOS1 gate capacitance 
to V s while the charge pump, activated by the 
signals IN = "low", as it can be seen in fig. 7, must 
supply only a voltage or about 10V. 



guarantees a faster turn-on of the upper POWER 
MOS and consequently high commutation fre- 
quencies. 

In fact during the period in which DMOS2 is "on" 
CgooT ' s charged to a voltage of about 1 2V. 

When V out raises because DMOS2 is disactivated 
D2 and D1 became "off" while D3, that remains 



connects the gate circuit to C 



that 



In the switching operation it will be C E 



that 



BOOT 
raises higher than V s and makes DMOS1 full "on" 

in a very short time interval (20 ns). 

It must be noted that the switch M4 in the fig. 6 
circuit, driven by a complementary phase respect 
to M3 disconnects D4, D5 and D6 from 12V when 
IV15 goes "on" to assure the "turn-off" of DMOS1. 

PERFORMANCE 

One of the most important features is the very high 
efficiency achieved. 

To appreciate the benefits of low power dissipation, 
and consequently of high efficiency, of a circuit 
realized in DMOS technology we must refer to the 
equivalent bipolar solution and also consider 
separate DC and AC operation. 

Consider the typical Darlington power stage fre- 
quently used in integrated circuit and a DMOS 
power stages both represented in fig. 8. 



36 



Fig. 6 - Schematic representation of charge PUMP and BOOSTRAP circuit used to drive the gate of the 
upper DMOS device 

— V 




M2 



500 KHz psc . ] \ | I M3 



H 



J 




D2 



D4 D3 



Dl 



D5 



putnp 



< 



01 



M5 



V2 



12V 






5-9352 



1 




c 



BOOT 



D-M0S1 

— OUT 



D-M0S2 



Fig. 7 - Charge PUMP abilitation signal and gate Neglecting the power dissipation in the driving sec- 
voltage of DMOS upper device tion, in static conditions, the total dissipation of 

the two stages when they are "on" is in the case (a): 

P d(a) = < V CESAT1 f V BE2> * U. 
and in the case (b): 




r d(b) 



= R 



DS(ON) * 'l 



where l L is the load current. 

Because the saturation loss of a power DMOS 
transistor can be reduced by increasing the silicon 
area it is possible to satisfy the condition 



R 



DS-ON 



x I, < (V 



CESATl 



+ V 



BE2 



Fig. 8 
stages 




Darlington Bipolar and DMOS power 

t-L| ! n A n i r-^-i ( n A n 



(b) 




and then to obtain lower dissipation. 

Concerning to the driving section, an other essen- 
tial difference must be emphaisised. 

While in case !a) during the time in which the 
power is "ON" it is necessary to supply a current 
for maintaining Q1 saturated, in the case (b) power 
is dissipated only during the commutation of the 
gate voltage. 

About AC operation, it must be noted that the 
greatest advantage, always in terms of power dissi- 
pation, is due to the inherently fast turn-on, turn- 
off times of power MOS devices. In fact, if we 
suppose that the load is of inductive type and that 
the current waveform is triangular on the voltage 
commutation of the output, the total power dissi- 
pation is: 



5-9355 



Vc I, T 



S 'L ' COM. 'SWITCH 



37 



where: V s = Supply voltage, l L = Peak load current, 



Tr 



= T 



TURN-ON 



= T 



TURN-OFF. 



fswiTCH = Chopper frequency. 

Because T CO m. in DMOS case is <than in bipolar 
case at a fixed frequency we have a lower dissi- 
pation or at fixed dissipation we can tolerate 
higher switching frequency. 



Considering all these aspects, with a power device 
consisting of about 2200 cells we have realized 
DMOS power devices characterized by Rds(ON) 
0.312 and by switching times t r , t f of 50 ns. Other 
characteristics of the device when is configured as 
shown in fig. 9 are listed in table 2. 

Fig. 10 shows the supply current with no load, 
vs. switching frequency. 



Fig. 9 




5-9357 



Table 2: MAIN FEATURES OF L6202/L6203 



• 


V s (maximum supply voltage) 


= 


60V 


• 


I l (maximum output current) 


= 


1.5A DIP. 16 






= 


5A MULTIWATT package > 


• 


Efficiency rj 


— 


90% I l L = 1.5A 
| 'chopper = 50KHz 


• 


Power dissipation P d 


= 


1.5W ( V s = 54V 


• 


t d (turn-on, turn-off propagation delay) 


= 


100 ns 



Fig. 10 



(mA) 



20-- 



15-. 



10.. 



5-- 



50 



100 



f(KHz) 



150 



200 



250 



5-9356 



38 



STEPPER MOTOR DRIVING 

Dedicated integrated circuits have dramatically simplified stepper motor driving. To apply 
these ICs designers need little specific knowledge of motor driving techniques, but an under- 
standing of the basics will help in finding the best solution. This note explains the basics of 
stepper motor driving and describes the drive techniques used today. 



From a circuit designer's point of view stepper 
motors can be divided into two basic types: 
unipolar and bipolar. 

A stepper motor moves one step when the direc- 
tion of current flow in the field coil(s) changes, re- 
versing the magnetic field of the stator poles. The 
difference between unipolar and bipolar motors lies 
in the may that this reversal is achieved (Figure 1): 

Fig. 1a - BIPOLAR — with one field coil and two 
chargeover switches that are switched 
in the opposite direction. 

Fig. lb - UNIPOLAR - with two separate field 
coils and are chargeover switch. 






®T 



k 



— fffYY* ' 



u 



a) 



! 




T +vs 


Ui 



— rj 



'rrrtr^ i I rrr-frf 

^—.ij, — I I — hj^-Ul,- 



b) 



r : 



a 



Fig. 2 - ICs for unipolar and bipolar driving 



UNIPOLAR 





— r 


— i 


- 


"F>-^ 








k>--... t rr 




— * 


- 


— 





BIPOLAR 




39 



The advantage of the bipolar circuit is that there 
is only one winding, with a good bulk factor (low 
winding resistance). The main disapuantages are 
the two changeover switches because in this case 
more semiconductors are needed. 

The unipolar circuit needs only one changeover 
switch. Its enormous disadvantage is, however, 
that a double bifilar winding is required. This 
means that at a specific bulk factor the wire is 
thinner and the resistance is much higher. We 
will discuss later the problems involved. 

Unipolar motors are still popular today because 
the drive circuit appears to be simpler when 
implemented with discrete devices. However with 
the integrated circuits available today bipolar 
motors can be driver with no more components 
than the unipolar motors. Figure 2 compares 
integrated unipolar and bipolar devices. 



BIPOLAR PRODUCES MORE TORQUE 

The torque of the stepper motor is proportional 
to the magnetic field intensity of the stator wind- 
ings. It may be increased only by adding more 
windings or by increasing the current. 

A natural limit against any current increase is the 
danger of saturating the iron core, though this is 
of minimal importance. Much more important is 
the maximum temperature rise of the motor, due 
to the power loss in the stator windings. This 
shows one advantage of the bipolar circuit, which, 
compared to unipolar systems, has only half of 
the copper resistance because of the double cross 
section of the wire. The winding current may be 
increased by the factor v /~2 and this produces a 
direct proportional affect on the torque. At their 
power loss limit bipolar motors thus deliver about 
40% more torque (Fig. 3) than unipolar motors 
built on the same frame. 

If a higher torque is not required, one may either 
reduce the motor size or the power loss. 

Fig. 3 - Bipolar motors driver deliver more torque 
than unipolars 

TORQUE 



BIPOLAR 



40% 



UNIPOLAR 




log 



FREQUENCY 



CONSTANT CURRENT DRIVING 

In order to keep the motor's power loss within a 
reasonable limit, the current in the windings must 
be controlled. 



A simple and popular solution is to give only as 
much voltage as needed, utilizing the resistance 
(R|_) of the winding to limit the current (Fig. 4a). 
A more complicated but also more efficient and 
precise solution is the inclusion of a current ge- 
nerator (Fig. 4b), to achieve independence from 
the winding resistance. The supply voltage in 
Fig. 4b has to be higher than the one in Fig. 4a. 
A comparison between both circuits in the dy- 
namic load/working order shows visible differences. 

Fig. 4 - Resistance current I i miter (a) and current 
generator limiting 

L RL L 




I L = I C 



Fig. 5 - At high step frequencies the winding 
current cannot reach its setting value 
because of the continuous direction 



change 




t A 



t B 



It has already been mentioned that this power of 
the motor is, among others, proportional to the 
winding current. 

In the dynamic working order a stepper motor 
changes poles of the winding current in the same 
stator winding after two steps. The speed with 
which the current changes its direction in the 
form of an exponential function depends on the 
specified inductance, the coil resistance and on 
the voltage. Fig. 5a shows that at a low step rate 
the winding current l|_ reaches its nominal value 
V|_/R L before the direction is changed. However, 
if the poles of the stator windings are changed 
more often, which corresponds to a high step fre- 



40 



quency, the current no longer reaches its saturating 
value because of the limited change time; the 
power and also the torque diminish cleariy at 
increasing number of revolutions (Fig. 5), 



MORE TORQUE AT A HIGHER NUMBER 
OF REVOLUTIONS 

Higher torque at faster speeds are possible if a 
current generator as shown in Fig. 4b is used. 
In this application the supply voltage is chosen 
as high possible to increase the current's rate 
of change. The current generator itself limits only 
the phase current and becomes active only the 
moment in which the coil current has reached its 
set nominal value. Up to this value the current 
generator is in saturation and the supply voltage 
s applied directiy to the winding. 

Fig. 6, shows that the rate of the current increase 
now much higher than in Figure 5. Conse- 
quently at higher step rates the desired current can 
De maintained in the winding for a longer time. 
The torque decrease starts only at much higher 
speeds. 

Fig. 7 shows the relation between torque and speed 
n the normal graphic scheme, typical for the 
itepper motor. It is obvious that the power in- 
:reases in the upper torque range where it is 
normally needed, as the load to be driven draws 
most energy from the motor in this range. 



: ig. 6 - With a step current slew it is not a problem 
to obtain, even at high step frequencies 
sufficient current in windings. 



Fig. 7 - Constant current control of the stepper 
motor means more torque at high fre- 
quency. 



TORQUE 



k s~~ L= R L 
/ 


/ . 


f k. 


/ 


\ 





t ' ' 
1 > 

Ki\ i 


/ 

\ 1 




\i\J 

! \ \ 


\1 


S-9374 



CONSTANT CURRENT 




FREQUENCY 



EFFICIENCY - THE DECISIVE FACTOR 

The current generator combined with the high 
supply voltage guarantees that the rate of change 
of the current in the coil is sufficiently high. 

At the static condition or at low numbers of 
revolutions, however, this means that the power 
loss in the current generator dramatically increases, 
although the motor does not deliver any more 
energy in this range; the efficiency factor is ex- 
tremely bad. 

Help comes from a switched current regulation 
using the switch-transformer principle, as shown in 
Fig. 8. The phase winding is switched to the supply 
voltage until the current, detected across Rg, 
reaches the desired nominal value. At that moment 
the switch, formerly connected to +V S , changes 
position and shorts out the winding. In this way 
the current is stored, but it decays slowly because 
of inner winding losses. The discharge time of the 
current is determined during this phase by a 
monostable or pulse oscillator. After this time one 
of the pole changing switches changes back to +V S , 
starting an induction recharge and the clock-re- 
gulation-cycle starts again. 

Since the only losses in this technique are the 
saturation loss of the switch and that of the coil 
resistance, the total efficiency is very high. 

The average current that flows from the power 
supply line is less than the winding current due to 
the concept of circuit inversion. In this way also 
the power unit is discharged. This king of phase 
current control that has to be done separately 
for each motor phase leads to the best ratio be- 
tween the supplied electrical and delivered mech- 
anical energy. 

POSSIBLE IMPROVEMENTS OF THE 
UNIPOLAR CIRCUIT 

It would make no sense to apply the same principle 
to a stabilized current controlled unipolar circuit, 
as two more switches per phase would be necessary 
for the shortening out of the windings during the 
free phase and thus the number of components 
would be the same as for the bipolar circuit; and 
moreover, there would be the well known torque 
disadvantage. 



41 



From the economic point of view a reasonable 
and justifiable improvement is the "Bi-Level- 
Drive" (Fig. S). This circuit concept works with 
two supply voltages; with every new step of the 
motor both windings are connected for a short 
time to a high supply voltage. This considerably 
increases the current rate of change and its be- 
haviour corresponds more or less to the stabilized 
power principle. After a pre-determined the 
switch opens, a no a lower supply voltage is con- 



nected to the winding thru a diode. 

This kind of circuit by no means reaches the 
performance of the clocked stabilized power 
control as per Fig. 8, as the factors: distribution 
voltage oscillation, B.e.m.f., thermal windinc 
resistance, as well as the separate coil currem 
regulation are not considered, but it is this circuit 
that makes the simple unipolar R/L-contro 
suitable for many fields of application. 



Fig. 8 - With switch mode current regulation efficiency is increased. 
■V s 



M 




s SWITCHED 



<3r 



MONO 
FLOP 



REF«~i^^ 



/ 




, V uW^V SWITCHED 



5-9376 



Fig. 9 - At every new step of the motor, it is possible to increase the current rate with a bilevel circui, 

START 
VOLTAGE 





mtm .1 



START 
VOLTAGE 



I STOP 
, VOLTAGE 



S-9377 



42 



ADVANTAGES AND DISADVANTAGES 
OF THE HALF-STEP 

An essential advantage of a stepper motor oper- 
ating at half-step conditions is its position resolu- 
tion increased by the factor 2. From a 3.6 degree 
motor you achieve 1.8 degrees, which means 200 
steps per revolution. 

This is not always the only reason. Often you are 
forced to operate at half-step conditions in order 
to avoid that operations are disturbed by the 
motor resonance. These may be so strong that the 
motor has no more torque in certain step fre- 
quency ranges and looses completely its position 
Fig. 10). This is due to the fact that the rotor of 
the motor, and the changing magnetic field of the 
stator forms a spring-mass-system that may be 
stimulated to vibrate. In practice, the load might 
deaden this system, but only if there is sufficient 
frictional force. 

Fig. 10 - The motor has no more torque in 
certain step frequency ranges with full 
step driving. 
TORQUE 



FULL STEP 
RESONANCE 




HALF STEP 
RESONANCE 



|n most cases half-step operation helps, as the 
bourse covered by the rotor is only half as long 
pnd the system is less stimulated. 

The fact that the half-step operation is not the 
Nominating or general solution, depends on certain 
disadvantages: 



The dynamic loss is higher the nearer the load 
moment comes to the limit torque of the motor. 
This effect decreases at higher numbers of revolu- 
tions. 



TORQUE LOSS COMPENSATION IN THE 
HALF-STEP OPERATION 

It's clear that, especially in limit situations, the 
torque loss in half-step is a disadvantage. If one has 
to choose the next larger motor or one with a 
double resolution operating in full-step because 
of some insufficient torque percentages, it will 
greatly influence the costs of the whole system. 

In this case, there is an alternative solution that 
does not increase the coats for the bipolar chopp- 
ing stabilized current drive circuit. 

The torque loss in the half-step position may be 
compensated for by increasing the winding current 
by the factor \f 2 in the phase winding that re- 
mains active. This is also permissible if, according 
to the motor date sheet, the current limit has 
been reached, because this limit refers always to 
the contemporary supply with current in both 
windings in the full-step position. The factor ^/~2 
increase in current doubles the stray power of the 



Fig. 11 



Half step driving with shaping allows to 
increase the motor's torque to about 
95% of that of the full step. 



FULL STEP 
HALF STEP 




HALF STEP 
WITH-SHAPING 



— log S-9379 



HALF 
STEP 



- the half-step system needs twice as many clock- 
pulses as the full-step system; the clock-fre- 
quency is twice as high as with the full-step. 

- In the half-step position the motor has only 
about half of the torque of the full-step. 

: or this reason many systems use the half-step 
iperation only if the clock-frequency of the motor 
6 within the resonance risk area. 



- 


r^ 


i_r 


J"L 


TJ" 





HALF STEP 
WITH SHAPING 



43 



active phase. The total dissipated power is like 

that of the full-step because the non-active phase 

does not dissipate power. 

The resulting torque in the half-step position 

amounts to about 90% of that of the full-step, 

that means dynamically more than 95% torque 

compared to the pure full-step; a neglectable 

factor. 

The only thing to avoid is stopping the motor at 



limit current conditions in a half-step position 
because it would be like a winding thermal phase 
overload concentrated in one. 

The pest switch-technique for the haif-step phase 
current increase will be explained in detail later on 
Fig. 11 shows the phase current of a stepping 
motor in half-step control with an without phase 
current increase and the pertinent curves of stap 
frequency and torque. 



Fig. 12 - Only two signals for full step driving are necessary while four (six if three-state is needed on the 
outputs stages) for half step. 



FULL 


STEP 


~1_.. ._ 








r~ 




i_ 


\ 








_ . _ L 


r 




















































ILB 





















4> 



-0- 



ILA 



ILB 



HALF STEP 




ILA 



X 



I 1 

_L_-I_ 



ILB_ 




" A TJ J 



44 



DRIVE SIGNALS FOR THE MICRO 
ELECTRONIC 

A direct current motor runs by itself if you supply 
if with voltage, whereas the stepping motor needs 
the commutation signal in for of several sep- 
arated but linkable commands. In 95% of the 
applications today, the origin of these digital 
commands is a microprocessor system. 

In its simplest form, a full-step control needs 
only two rectangular signals in quadrature. Ac- 
cording to which phase is leading, the motor 
axis rotates clockwise or counter-clockwise, 
whereby the rotation speed is proportional to the 
clock frequency. 

In the half-step system the situation becomes 
more complicated, The minimal two control 
signals become four control signals. In some 
conditions as many as six signals are needed, if 
he Tri-state-command for the phase ranges 
without current, necessary for high motor speeds, 
may not be obtained from the 4 control signals. 
Fig. 12 shows the relationship between the phase 
:urrent diagram and the control signal for full 
and half-step. 

Since all signals in each mode are in defined 
'elations with each other, it is oossible to generate 



them using standard logic. However, if the pos- 
sibility to choose full and half-step is desired, a 
good logic implementation becomes quite ex- 
pensive and an application specific integrated 
circuit would be better. Such an application 
specific integrated circuit could reduce the number 
of outputs required from a microprocessor from 
the 6 required to 3 static and dynamic control 
line. 

A typical control circuit that meets all these re- 
quirements is the L297 unit (Fig. 13). 
Four signals control the motor in all operations: 

1. CLOCK: The clock signal, giving the 

stepping command 

Puts the final level signals in 
a defined start position 

Determines the sense of rota- 
tion of the motor axis 

Desides whether to operate in 
full or in half-step. 

Another inhibit input allows the device to switch 
the motor output into the Tri-state-mode in order 
to prevent undesired movements during undefined 
operating conditions, such as those that could 
occur during. 



BESET: 
DIRECTION 



4. HALF/FULL: 



: ig. 13 - The L297 avoids the use of complicated standard logic to generate both full and half-step 
driving signals together with chopper current control. 

5V Q36V 

r I 



D1 <o DS - 2A Fast diodes ! V F «= 1-2V 6> I - 2A 
| trr < 200 ns 

iwiTCH-MODE CURRENT REGULATION 

The primary function of the current regulation 
:ircuit is to supply enough current to the phase 
bindings of the motor, even at high step rates. 

The functional blocks required for a switchmode 
:urrent control are the same blocks required in 
Witching power supplies; flip-flops, comparators; 
md an oscillator are required. These blocks can 
lasily be included in the same IC that generates the 
ihase control signals. Let us considerthe implemen- 
ation of chopper current control in the L297. 

'he oscillator on pin 16 of the L297 resets the two 

|ip-flops at the start of each oscillator period. The 




flip-flop outputs are then combined with the 
outputs of the translator circuit to form the 6 
control signals supplied to the power bridge 
(L298). 

When activated, by the oscillator, the current in 
the winding will raise, following the L/R time 
constant curve, until the voltage across the sense 
resistor (pin 1, 15 of L298) is equal to the re- 
ference voltage input, (pin 15, L297! the com- 
parator then sets the flip-flop, causing the output 
of the L297 to change to an equiphase condition, 
thus effectively putting a short circuit across the 
phase winding. The bridge is activated into a 
diagonally conductive state when the oscillator 
resets the flip-flop at the start of the next cycle. 



45 



Using a common oscillator to control both current 
regulators maintains the same chopping frequency 
for both, thus avoiding interference between 
the two. 

The functional block diagram of the L297 and the 
power stage (L298) are shown in Figure 14 alone 
with the operating wave forms. 

An important characteristics of this circuit imple- 



mentation is that, during the reset time, the flip 
flops are kept reset. The reset time can be selectee 
by selecting the impedance of the R/C network o 
pin 16. In this way, the current spike and noisi 
across the sense resistors that may occur durinj 
switching will not cause a premature setting o 
the flip-flop. Thus the recovery current spike o 
the protection diodes can be ignored and a filte 
in the sense line is avoided. 



Fig. 14 - Two ICs and very few external components provide complete microprocessor to bipolar steppe, 
motor interface. 





THE RIGHT PHASE CURRENT FOR 
EVERY OPERATING CONDITION 

The Chopper principle of the controller unit 
reveals that the phase current in the motor wind- 
ings is controlled by two data: the reference 
voltage at pin 15 of the controller and the value 
of the sense resistance at pins 1 and 15 of the 
L298, that is l L = V REF /R S . By changing V REF 
it is very easy to vary the current within large 
limits. The only question is for which purpose and 
at which conditions. 

More phase current means more motor torque, 
but also higher energy consumption. 



An analysis of the torque consumption for dil 
ferent periods and load position changes show 
that there is no need for different energies. 

There is a high energy need during the acceleratioi 
or break phases, whereas during continuous ope 
ration or neutral or stop position less energy ha 
to be supplied. A motor with its phase curren 
continuously oriented at the load moment li mil 
even with the load moment lacking, consume 
needlessly energy, that is completely transforms 
into heat. 

Therefore it is useful to resolve the phase curren 
in at least two levels controllable from the pre 
cessor. Fig. 18 shows a minimal configuratio 



46 



with two resistance and one small signal transistor is sufficient for all imaginable causes. 

as changeover switch for the reference input. 

With another resistance and transistor it is possible Fig. 16 shows a optimal phase current diagram 

to resolve 2 Bits and consequently 4 levels. That during a positioning operation. 

Fig. 15 - Because of the set-dominant latch inside the L297 it is possible to hide current spikes and noise 
across the sense resistors thus avoiding external filters. 



VREF4 




Fig. 16 - More energy is needed during the acceleration and break phases compared the continuous 
operation, neutral or stop position. 



EF> 
STOP 


ACCELER. 


TRANSPORT 


DECEIER. 


STOP 










I ■ 











HIGH MOTOR CLOCK RESETS IN THE 
HALF-STEP SYSTEM 

In the half-step position one of the motor phases 
has to be without current. If the motor moves 
from a full-step position into a half-step position, 
|this means that one motor winding has to be com- 
pletely discharged. From the logic diagram this 
means for the high level bridge an equivalent 
status of the input signals A/B, for example in the 
HIGH-status. For the coil this means short circuit 
(Fig. 17 up) and consequently a low reduction 
pf the current. In case of high half-step speeds 
the short circuit discharge time constant of the 
ahase winding is not sufficient to discharge the 



current during the short half-step phases. The 
current diagram is not neat, the half step is not 
carried out correctly (Fig. 17 center). 

For this reason the L297 controller-unit generates 
an inhibit-command for each phase bridge, that 
switches the specific bridge output in the half- 
step position into Tri-state. In this way the coil 
can start swinging freely over the external re- 
covery diodes and discharge quickly. The current 
decrease rate of change corrisponds more or less 
to the increase rate of change (Fig. 17 below). 

In case of full-step operation both inhibit-outputs 
of the controller (pin 5 and 8) remain in the 
HIGH-status. 



47 



Fig. 17 - The inhibit signal turns off immediately the output stages allowing thus a faster current decay 
(mandatory with half-step operation). 



INHIBIT 



11 I 



IL 



'^>- 



VS HS VS HS VS 



IL 




t*** 



IL 






|«^ 




Fig. 18 - With this configuration it is possible to obtain half-step with shaping operation and therefort 
more torque. 

A i ■ T 1 



L297 
CONTROLLER 



[NH. 1 




MORE TORQUE 
POSITION 



IN THE HALF-STEP 



A topic that has already been discussed in detail. 
So we will limit our considerations on how it is 
carried out, in fact quite simply because of the 
reference voltage controlled phase current re- 
gulation. 

With the help of the inhibit-signals at outputs 
5 and 8 of the controller, which are alternatively 
active only when the half-step control is pro- 
grammed, the reference voltage is increased by 



the factor 1.41 with a very simple additional 
wiring (Fig, 18), as soon as one of the two inhibit- 
signals switches LOW. This increases the current 
in the active motorphase proportionally to the 
reference voltage and compensates the torque loss 
in this position. Fig. 19 shows clearly that the 
diagram of the phase current is almost sinusoidal, 
in principle the ideal form of the current graph. 

To sum up we may say that this half-step version 
offers most advantages. The motor works with 
poor resonance and a double position resolution 
at a torque, that is almost the same as that of 
the full-step. 



Fig. 19 - The half-step with shaping positioning is achieved by simply changing reference voltages. 

—J 1 A 



L 



~u u — lt 



i_ 



INHIBIT 1 
B 



J L 



u u U 



J L 



^LfinjTJUirLJTn 



INHIBIT 2 


REFERENCE 



ifh r£k 



HF 



II 



l 
1.4 

1 • 


r^ H" 1 


i 


IT 1 hi" 

S-9 389 



PHASE CURRENT 



12 



SETTER GLIDING THAN STEPPING 

If a stepper motor is supposed to work almost 
iliding and not step by step, the form of the 
ihase current diagram has to be sinusoidal. 

Phe advantages are very important : 

no more phenomena of resonance 

drastic noise reduction 

connected gearings and loads are treated with 



the position 
further. 



resolution may be increased 



However, the use of the L297 controller-unit de- 
scribed until now is no longer possible of the more 
semplicated form of the phase current diagram the 
Controller may become simpler in its functions. 

Fig. 20 shows us an example with the L6505 unit. 
This IC contains nothing more than the clocked 
phase current regulation which works according to 



49 



the same principle as L297. The four control 
signals emitting continuously a full-step program 
are now generated directly by the microprocessor. 
In order to obtain a sinusoidal phase current course 
the reference voltage inputs of the Controller are 
modulated with sinusoidal half-waves. 

The microprocessor that controls the direction 
of the current phase with the control signals also 
generates the two analog signals. 

For many applications a microprocessor with dedi- 
cated digital to analog converters can be chosen. 
Eliminating the need for separate D/A circuits. 



About 5 bit have proved to be the most suitable 
suddivision of the current within one full-step. A 
higher resolution brings no measurable advantages. 
On the contrary, the converter clock frequency is 
already very high in case of low motor revolutions 
and very difficult to process by the processor- 
software. It is recommended to reduce the D/A 
resolution at high step frequencies. 

In case of higher motor revolutions it is more 
convenient to operate only in full-step, since 
harmonic control is no longer an advantage as 
the current has only a triangular waveform in 
the motor winding. 



Fig. 20 - L6506 unit gives the possibility to modulate separately the two reference voltage inputs it 
order to obtain a sinusoidal phase current. 



jP I 



DAC 

I 

I- — - 

I 

| DAC 



-L_* 



X^ 



r 



LOGIC 



L6506 






a 



CONTROLLER 



L298N 



P1 



P2 




REF 



REF 



50 



PRECISION OF THE MICRO STEP 

Any desired increase of the position resolution 
between the full step position has its physical 
limits. Those who think it is possible to resolve a 
7.2° - stepper motor to 1.8° with the same precision 
as a 1.8° - motor in full-step will be received, as 
there are several limits: 

The rise rate of the torque diagram corresponding 
to the twisting angle of the rotor for the 7.2° - 
motor is flatter by a factor of 4 then for the 
original 1.8" - motor. Consequently with fric- 
tion or load moment, the position error is larger 



(Fig. 21). 

For most of the commercial motors there isn't 
a sufficiently precise, linear relationship between 
a sinusoidal-current-diagram and an exact micro 
step angle. The reason is a dishomogeneous mag- 
netic field between the rotor and the two stator 
fields. 

Above all, problems have to be expected with 
motors with high pole feeling. However, there 
are special stepper motors in which an optimized 
micro step operation has already been considered 
during the construction phase. 



Fig. 21 - Better resolution is achieved with low degree motor but more torque is delivered with high 
degree motor. 



7 2 'MOTOR 




TORQUE 



CONCLUSIONS 

The above described application examples of 
modern integrated circuits show that output and 
efficiency of stepper motors may be remarkably 
increased without any excessive expense increase 



like before. 

Working in limit areas, where improved electronics 
with optimized drive sequences allow the use of 
less expensive motors, it is even possible to obtain 
a cost reduction. 



51 



CONSTANT-CURRENT CHOPPER DRIVE UPS 
STEPPER-MOTOR PERFORMANCE 

Pulse width-modulated drive improves motor torque 
and speed yet adds no complexity to circuit 



Designers opting to use a fractional-horsepower 
stepper motor in applications such as computer 
printers can improve the motor's efficiency and 
its torque and speed characteristics by using a 
constant-current pulse-width-modulated (PWM) 
chopper-drive circuit. What's more, for high-power 
drives, dedicated control chips and a constant-cur- 
rent chopper drive can be as simple to use as direct 
drive. 

A basic problem for a directly driven stepper is 
that the motor winding's time constant (L/R) 
causes the current to increase slowly in the winding 
during each pulsed input. It may, therefore, never 
reach full-rated value, especially at high speed, 
or high pulsing rates, unless the voltage (V s ) across 
the terminals is high. In the simplest stepper drive 
(see Fig. 1a), transistor or Darlington switches 



sequentially activate the windings to drive the 
motor (see box, "Stepper motor basics"). 

This type of drive performs poorly because the 
supply voltage must be low so that the steady- 
state current is not excessive. As a result, the 
average winding current - and hence the torque - 
is very low at high drive motor speed. 

Often, this problem is overcome by introducing a 
series resistance, thereby increasing the overall 
value by a factor of four - giving an L/4R ratio - 
and also by increasing the supply voltage (see 
Fig. 1b). This arrangement reduces the motor's 
time constant, which improves torque at high step 
rates. However such an approach is inefficient, 
because the series resistor constitutes a substantial 
waste of power. 



Fig. 1 - Common unipolar stepping drives (a) produce insufficient torque output because their supply 
voltage must be kept low to limit current. Adding series resistance to an L/4R ratio (b) and 
raising the supply voltage proportionately improves torque output, especially at high step rates. 



a) 




b) 

MOTOR 
WINDINGS 



L/fl 



SWITCHES 



ELEPRi: : LIB 




4R 



53 



Fig. 2 - A pu Ise-width-modu latea ', or chopper, 
drive overcomes most of the problems 
of the simpler direct drive or even linear 
constant-current drives. 



OSCILLATOR ] 




\ MOTOR 
< WINDING 












FLIP 1 






FLOP 
















COMPARATOR 


~?refI 


j SENSE 
RESISTOR 



S-9A01 



circuit - not only solves the L/R time-constant 
problem but cuts power dissipation too {see Fig. 2) 

A four-phase bifilar/hybrid unipolar stepper motor 
could use a quad Darlington like the SGS L7180 
as a chopper driver and a chip like the SGS L6506 
as a current controller (see Fig. 3). The quad Dar- 
lington can drive motors at up to 1 .4A/phase - 
which is suitable for a carriage motor in a medium- 
size printer. 

The L6506, which contains al! the chopper cir- 
cuitry, is simple to use. An external RC network 
sets the oscillator frequency, and a voltage divider 
(or trimmer) sets the reference voltages, and hence 
the phase currents. Normally an oscillator fre- 
quency of over 20KHz is chosen to avoid motor 
noise. The maximum usable frequency depends on 
the L/R time constant of the motor. 

Control signals for the four-phase inputs can be 
provided by a micro-computer chip or a simple 
repetitive sequence from a logic circuit. Note 
that the L6506 contains just two independent 
chopper-control loops - sufficient for a four-phase 
unipolar stepping motor because opposing wind- 
ings never energize together, 



CONSTANT CURRENT IS BEST 

Introducing a feedback loop to control the winding 
current is a better solution. Linear constant-cur- 
rent control is possible but is rarely used because 
of high power losses in the power stage. However, 
a pulse-width-modulation scheme - a chopper 



DRIVING BIPOLAR MOTORS 

Bipolar stepper motors, preferred for their better 
torque/weight ratio, however, are normally driven 
by H-bridge output stages. They enable a single- 
polarity supply to drive each motor winding end 
sequentially to achieve a polarity-revei-sal effect 
on the windings. 



Fig, 3 - A simple chopper drive for a unipolar stepping motor, can be assembled with just two chips: a 
quad Darlington output driver IC and a constant-current feedback controller IC. 




54 



STEPPER-MOTOR BASICS 

In computer-peripheral office-equipment ap- 
plications, the most popular stepper motors are 
permanent-magnet types with two-phase bi- 
polar windings or bifilar-wound unipolar 
windings. Stripped to the essentials, both types 
consist of a permanent-magnet rotor sur- 
rounded by stator poles carrying the windings. 

A two-pole motor would have a step angle of 
90" , However, most motors have multiple poles 
to reduce the step angle to a few degrees. 

A bipolar permanent-magnet stepper motor has 
a single winding for each phase - and the 
current must be reversed to reverse the stator 
field. Bifilar/ hybrid unipolar motors, however, 
have two windings wound in opposite direc- 
tions for each phase, so that the fieid can be 
reversed with a singie-poiarity drive. Unipolar 
motors were once popular because the drive 
was simpler. But with today's duai bridge 



(H-bridge) ICs, it is just as easy to drive a bi- 
polar motor. 

In the most popular drive technique - two- 
phase-on - both phases are always energized, 
and the rotor poles are aligned is stator poier 
between steps. In another method - called the 
wave drive - one phase is energized at a time. 

A third technique combines the two sequences 
and drives the motor one half-step at a time. 
Half-stepping is very useful because motor 
mechanically designed for very small step 
angles are much more complex - and costly - 
to built. It is more economical to use a 100- 
step motor in naif steps ratner than a 200-step 
motor in full step. 

Recently designers have started microsteppmg, 
or driving the motor at one-quarter stepping 
rather or less. This type of operation can obtain 
fine step control without using mechanically 
complex motors with small step angles. 



A two-phase bipolar motor needing up to 1 A/ 
phase can be driven by a single IC - the SGS 
L298 dual bridge (see Fig. 4). It contains two H- 
bridges with all the necessary level shifters and 
gates to directly interface low-level input logic 
signals. 



As before, a complete chopper drive can be built 
by adding a current-controller chip and the necess- 
ary protective diodes, an RC network to define the 
oscillator frequency and a reference-voltage divider 
to set the current level. Four-phase signals to the 
controller are provided by a controlling micro- 



Fig. 4- A dual-bridge IC provides a simple power-stage design solution for a bipolar stepper motor, 

ENABLE </ f VS 



RESET 
IN 1 



9nF 




SURGE 
SUPPRESSOR DIODES 



ilfit SURGE 

.SUPPRESSOR DIODES 



' fl fl SENSIN 
K V UresISTO 



G 
RS 



VREF 



55 



computer or by another dedicated controller 
chip - the SGS L297 stepper-motor controller. 

Containing an internal translator circuit controlled 
by step-and-direction inputs, the L297 motor 
controller (see Fig. 5) allows operation in three 
modes: two-phase-on, half-step and wave-drive. 

The normal two-phase-on mode is selected by a 
low level on the half/full input when the device 
has been reset to start. 

Half-step drive is selected by a high level on the 
half/full step input. To initialize the wave-drive 
mode, the user disables the output stage (brings 
enable low), resets the device, steps the translator 
one step, brings half/full low, and then reenables 
the outputs. 

The L297 also lets the designer select either phase 



or inhibit chopping. Phase chopping provides lower 
ripple and is suitable four unipolar motor, whereas 
inhibit chopping returns energy to the supply and 
is better for bipolar motors. 

In applications such as printer-paper feed, the 
motor is often at rest. Since the full torque is not 
usually necessary to hold the motor in position, 
designers can save power by switching the current 
to a lower level between runs. With an L297 or 
L6506 control chip, this task can be done by 
simply switching the reference input between 
two levels. 

Where several chopper drives are used in the same 
system, they should be synchronized prevent 
intermodulation effects. This is done by con- 
necting the sync pins to one another and omitting 
the oscillator RC network on all but one device. 



Fig. 5 - Controlled by step, direction, and mode inputs, the SGS L297 stepper-motor controller chip 
performs some of the functions of a controlling microcomputer. 



CW/CCR" 

STEP 

H ALF/FUL L 
BESET 

CONTROL 

ENABLE 



+ 5 vl 
22K I) 

.3nF = 



J TRANSLATOR 



IH 



OUTPUT 
LOGIC 



L297 



<£ 



L298 



fe 



fc 



fe- 



;;;;;;;; 



X 



MOTOR 
WINDINGS 



(<aA/PHASE) 



1 



MU]° 



HANDLING HIGH CURRENT 

For current drives greater than 2A/phase, the two 
bridges in an L298 IC can be paralleled by con- 
necting inputs to the corresponding outputs. 
However, for a more equal distribution of the load 
and chip heating, driver 1 should be paralleled with 
driver 4, and driver 2 with driver 3. Additionally, 
total current should be derated by 0.5A to allow 
for the maximum possible imbalance between the 
current in each bridge. Thus two L298s can drive 
motors rated at 3.5A/phase. 

A different configuration for microstepping 
stepper motors is employed in the SGS PBL3717A 
control circuit. It contains all of the control and 



power circuitry for one phase of a motor. An 
H-bridge output stage can drive motors rated at 
up to 1 A/phase. Two of these devices are needed 
to drive a two-phase bipolar motor. 

The output current level from the PBL3717A 
is set both by an analog-reference input and two 
logic inputs {\ 1 and In), which select one of three 
preset current levels (the fourth combination dis- 
ables the outputs stage). This feature implements 
the microstepping, in which several current levels 
are used to obtain very small step angles for even 
more precise control (but at the expense of a less 
regular torque). Unlike the L297 and L6506, the 
PBL3717A has a constant off-time chopper driver 
which is ideal for microstepping. 



56 



USING THE L6506 FOR CURRENT CONTROL 
OF STEPPING MOTORS 



The L6506 is a linear integrated circuit designed 
to sense and control the current in stepping motors 
and other similar devices. When used in conjunc- 
tion with power stages like the L293, L298N, or 
L7180 the chip set forms a constant current drive 
for inductive loads and performs all the interface 
functions from the control logic through the power 
stage. 

The L6506 may be used with either two phase 
bipolar or four phase unipolar motor configura- 
tions. The circuit in Figure 1 shows the L6506 
used in conjunction with the L298N in a 2 phase 
bipolar stepper motor application. The circuit in 
Figure 2 implements a similar 4 phase unipolar 
application. 



CURRENT CONTROL LOGIC 

In these two circuits, the L6506 is used to sense 
and control the current in each of the load wind- 



ings. The current is sensed by monitoring the 



voltage across a sense resistor (R s 



J and using 



a Pulse Width Modulated control to maintain the 
current at the desired value. 

An on-chip oscillator drives the dual chopper and 
sets the operating frequency. An RC network on 
pin 1 sets the operating frequency, which is given 
by the equation : 



f 



1 



0.69 R1 C1 
for R1 > 10Kn 



The oscillator provides pulses to set the two flip- 
flops, which in turn cause the outputs to activate 
the power actuator. Once the outputs have been 
activated the current in the load starts to increase, 
limited by the inductive characteristic of the load. 



Fig. 1 - Application circuit for Bipolar 2 phase stepper motor 




ENABLE B OUTPUT! 
1NPUT1 

0UTPUT2 

OUTPUT3 

OUTPUT4 

SENS! 5ENS2 GND 



D3 

~t ~tr T ~X 



D5 



D6 



D7 



ir ~x ir ~^r 



D7 



IN4935 



IN4935 



' OPTIONAL COMPONENTS 



57 



Fig. 2 - Application circuit for unipolar 4 phase stepper motor 

vs 




OPTIONAL COMPONENTS 



When the current in the load winding reaches the 
programmed peak value, the voltage across the 
sense resistor (R sense ) is equal to reference voltage 
input (V ref ) and the corresponding comparator 
resets its flip-flop. This interrupts the drive and 
allows the current to decay through a recirculating 
path until the next oscillator pulse occurs. The 
peak current in each winding is programmed by 
selecting the value of the sense resistor and V ref 
and is given by the equation : 



V, 



ref 



'peak 



(2) 



Fig. 3 - Input signal for stepper motor drive 



FULL STEP MODE 



The minimum output pulse width is determined 
by the pulse width of the oscillator, or other 
signal applied to the sync input. The internal 
oscillator is designed to provide narrow pulses to 
the sync input but the pulse width should be 
considered carefully. In some applications it is 
desirable to set the pulse width of this sync pulse 
to be just longer than the turn on delay time of 
the actuator stage. This may be useful in systems 
where the switching noise or recovery current of 
the catch diodes, which passes through the sense 
resistor, causes the comparator to sense a current 
above the peak current. By making the sync pulse 
wide enough to hold the flip-flop set at the time 
the switching transient occurs will cause the device 
to ignore this false data. 

When the internal oscillator is used the pulse width 
can be modified by changing the value of the 
capacitor on pin 1 . 

Increasing the capacitance will widen the pulse 
width. 



HALF STEP MODE 



The L6506 may be used with either a bridge driver, 
as shown in Figure 1 , for bipolar motors or a quad 
darlington array, as shown in Figure 2, for 4 phase 
unipolar motors. For eigher configuration, half 
step may be implemented using the 4 phase inputs 
with the input waveforms shown in Figure 3, 

The recirculation path for the motor current is 
through a catch diode for unipolar motors, or a 
catch diode and one of the lower transistors of 
the bridge for bipolar motors, Both of these im- 
plementations produce a low ripple current since 



58 



L6505 



the voltage across the motor during the recircula- Fig. 5 - Synchronizing multiple devices 
tion time is much less than the power supply volt- 
age. Figure 4 shows the ripple current for bipolar cc 
motor applications using the L6506 and the L298. 

When implementing a half step drive, both outputs 
of the L6506 will be low during the half step of 
one phase. This means a very long time is required 
for the current in the "off" winding to decay 
when driving bipolar motors. 

Alternately, the power stage (L298) may be 
inhibited to put the output in the state and achieve 
a faster current decay. 

Since separate V re f inputs are provided for each 
channel, each of the loads may be programmed 
independently allowing the device to be used to 
implement microstepping or applications with 
different peak and hold currents. In this type of 
application, changing the reference voltage (V ref ) 
will change the load current, effectively imple- 
menting a transconductance amplifier. 



R/C 



osc 

SYNC 



MASTER 



r 



R/C 



L6505 



OSC 
SYNC 



Fig. 4 - Ripple current in Bipolar motors 




SYNCHRONIZING MULTIPLE DEVICES 

Ground noise problems in multiple configurations 
can be avoided by synchronizing the oscillators. 
This may be done by connecting the sync pins of 
each of the devices with the oscillator output of 
the master device and connecting the R/C pin of 
the unused oscillators to ground as shown in 
Figure 5. The devices may be synchronized to 
external circuits by applying synchronizing pulses 
to the sync pins. It should be noted, however, 
that the input pulse sets the minimum on time 
of the outputs and will therefore set a minimum 
output average current. 



SELECTING THE OSCILLATOR COM- 
PONENTS 

When selecting the values for the external com- 
ponents for the oscillator one of the primary con- 
siderations is the operating frequency. In addition 
there is another important consideration for these 
components. 



SLAVE 

S-9345 

In many applications the reverse recovery current 
of the free wheeling diodes and of parasitic el- 
ements in the power stage will flow through the 
sensing resistor in addition to the load current. 
Also there is sometimes noise generated in the 
system when the power stage is switched on. 
These two sources of error can fool the current 
limiting stage and make it appear to operate at a 
subharmonic of the desired frequency. With the 
proper selection of the oscillator components 
this behavior can be avoided. 

The design of the L6506 is such that the flip- 
flops used in the device are set dominant so that 
whenever the sync input is low the Q output of 
the flip-flop will be high even if the reset is ap- 
plied by the comparator at the same time. This 
characteristic of the flip-flops can be used to make 
the current sensing immune to the recovery cur- 
rents and noise spikes that occur when the power 
devices switch. If the sync pulse is longer than the 
turn on delay time of the power stage, as shown in 
Figure 6, these two sources of errors will be 
ignored. 



Fig. 6 - Load current and sync pulse 



A3 2,2 U DLY 24 ?fj* ! 


A 
J ' 





\ 
5G0*rtl 10mj J.5 


|00n» 



59 



To select the proper values for the oscillator com- 
ponents a more detailed equation for the operating 
frequency and duty cycle of the oscillator is re- 
quired. The required equations can be derived 
from the equivalent circuit for the oscillator 
section shown in Figure 7. 

As can be seen from figure 7, the full equation for 
the operating frequency includes not only the 
external resistance and capacitance but the internal 
discharge resistor as well. The full equation for the 
operating frequency is: 



1 



0.69 C RI + 



R1 Ri 
R1 + Ri 



(3) 



The equations for the active time of the sync 
pulse (T2), the inactive time of the sync signal 
(T1) and the duty cycle can also be found by 
looking at the figure 7 and are : 



T2 = 0.69 C1 



R1 Ri 
R1 + Ri 



<4> 



For a typicai application using the L298, which 
has a maximum turn on delay of 2.5ms, with the 
L6506 consider the following operating points: 

f = 25KHz 

T1 + T2 = 40ms 

T2 min = 3ms 



From equation 6 : 



DC 



From equation 7 : 



3/^s 
40ms 



0.075 



R1 



1 



0.075 



-2 ) 700 = 7.9Kn 



From equation 8 : 



C1 



37ms 



(0.69) (7.9K) 



6.7nF 



T1 = 0.69 R1 C1 
T2 



DC = 



T1 + T2 



(5) 
(6) 



By substituting equations 4 and 5 into equation 6 
and solving for the value of R1 the following 
equations for the external components can be 
derived : 



R1 



= bH 



(7) 



Fig. 7 - Oscillator circuit and waveforms 





5SS 






t 



C1 = 



T1 



0.69 R1 



Looking at equation 4 it can easily be seen that 
the minimum pulse width of T2 will occur when 
the value of Ri is at its minimum and the value of 
R1 at its maximum. Therefore, when evaluating 
equation 7 the minimum value for Ri of 70012 
(1Kn - 30%) should be used to guarantee the 
required pulse width. 




60 



HIGH-POWER, DUAL-BRIDGE ICs 
EASE STEPPER- MOTOR-DRIVE DESIGN 

In addition to simplifying design problems, a family of dedicated chips improves stepper- 
motor drive-circuit reliability by significantly reducing the component count. 



The L293, L293E and L298N dual-bridge ICs (see 
box, "Inside the dual-bridge ICs") significantly 
reduce the problems encountered in the design of 
stepper-motor drive circuitry. They can, for ex- 
ample, simplify the design and increase the effi- 



ciency of constant--current choppers. And with a 
single chip replacing the transistors and predriver 
stages, circuit performance improves. Best of all, 
the devices have applications in complex as well as 
basic driver networks. 



Fig. 1 - The simplest stepper-motor drive technique is the basic L/R configuration. Adding series resistors 
and raising the supply to make an L/4R drive improves torque at high steps rates but reduces efficiency. 




it :; :r 



4 x 1N4935 



<20!»30mH 



2-PHASE 

BIPOLAR 

STEPPER 

MOTOR 

(300 mA/PHASE) 



Ai it Ai it 4x 1N4935 



NOTES. 

DIODE REVERSE RECOVER TIME ST..) s200nSEC. 
FOR L/4R DRIVE, ADD 60S! 6W RESISTOR 
IN SERIES WITH EACH WINDING AND 
RAISE SUPPLY VOLTAGE TO 24V. 



SIMPLEST DESIGN IS AN L/R DRIVE 

The simplest motor-drive configuration (Fig. 1) 
consists of a ,uC that performs the translator func- 
tion in software (see box, "Generating switching 
sequences") and drives the motor through a L293 
dual bridge. Only eight external components are 
required; these are diodes that protect the device's 
output transistors against inductive spikes gener- 
ated when a winding de-energizes. 

The L293 handles 1A continuous (for higher cur- 



rent use an L298N). However, if you plan to run 
the motor continuously with two phases on, 
dissipation will be the limiting factor. 

You can improve the performance of this basic 
L/R drive by increasing the series resistance and 
raising the supply voltage to restore the original 
phase current. At high speeds, torque improves, 
but efficiency decreases. Normally, you increase 
each winding's resistance by a factor of four 
through the addition of a 3R series resistance, 
resulting in the L/4R drive. 



INSIDE THE DUAL-BRIDGE ICs 

The L293, L293E and L298N (figure) contain 
two power-transistor bridges, predriver stages, 
control logic and protection circuitry. There's a 
control input for each bridge and an enable 
input for each half bridge; inputs connect 
directly to fiCs, CMOS or TTL. The ICs inte- 
grate level shifters with a separate logic-supply 
pin. For current sensing, the L293E and L298N 
have external emitter connections. 

A single package drives a 2-phase bipolar step- 
per motor, challenging the assumption held by 
many that unipolar motors are easier to drive. 



You can use a bipolar motor — simpler and less 
expensive than a unipolar motor — without 
building complex power stages. Furthermore, 
you don't have to worry about simultaneous 
conduction of a half bridge's source and sink 
transistors — a basic problem with discrete- 
component bridge circuits. Chip design makes it 
impossible for both transistors to be on at the 
same time. 

Designers should also discard the mistaken idea 
that constant-current chopper drivers are com- 
plicated and expensive. You can build one with 
two bridge ICs and a few passive components. 



Dual-bridge driver ICs reduce the parts count of bipolar stepper motors and simplify design. The 
schematic of the L298IM is functionally similar to those of the L293 and L293E. 



EN.O- 




Type 


io 


'O(PEAK) 


v s 


PACKAGE 


SENSING CONNECTIONS 


L293 


1A 


1.5A 


36V 


16DIP 


- 


L293E 


1A 


1.5A 


36V 


20 DIP 


ONE PER HALF BRIDGE 


L298N 


2A 


2.5A 


46V 


MULT I WATT 15 


ONE PER BRIDGE 



62 



MULTIPLE SUPPLIES BOOST 
PERFORMANCE 

A dual-level supply also improves the performance 
of a basic L/R circuit. A high supply voltage yields 
good torque characteristics when the motor is 
running. A lower-than-rated voltage provides some 
holding torque when the motor is at rest, thereby 
saving power when the motor is idle. 

Fig. 2 shows a suitable voltage-switch circuit. R x 
sets the holding current, which can be low because 
a permanent magnet or hybrid stepper motor pro- 
vides some holding torque at zero current. However, 
make certain the L293's motor-supply input never 
goes below the logic-supply voltage. While there's 
no danger of damaging the device, it's impossible 
to drive the output transistors correctly under such 
conditions. 

The dual bridge's enable inputs offer a means of 
extending the chip's flexibility. For example, you 
can connect them directly to the logic supply — no 
resistors are needed — to enable the chip perma- 
nently. As an alternative, use the enable inputs to 
disable the motor during the power-on reset 
sequence. 

In wave-drive and half-step modes, use the enable 
inputs to increase torque at high speeds. When a 
winding de-energizes, flux collapse is a function of 
the current-decay rate. During this decay, the de- 



energized winding opposes the efforts of the next 
winding in sequence, partially cancelling the torque. 
You can minimize this effect by disabling a bridge 
only when the winding it drives is turned off; 
because the A i/A t of an inductor equals E/L, dis- 
abling the bridge accelerates the current decay. 
This action discharges the winding's stored energy 
through its supply and maintains the terminal 
voltage E at V s plus two diode drops, If you were 
to leave the bridge enabled, the current would flow 
to ground through one diode and one transistor, 
and it would lower the terminal voltage. This 
scheme doesn't apply with drives with two phases 
on because no winding ever de-energizes. 

Fig. 2 - Switching the supply to a lower voltage 
when the motor is idle saves current without 
compromising driving power 




OPEN 
COLLECTOR 
[NVERTER 



Fig. 3 - Maintaining a constant-average phase current this fixed-ripple chopper provides improved per- 
formance and efficiency V fief controls the phase current 




2-PHASE 

BIPOLAR 

STEPPER 

MOTOR 

(280 mA/PHASE 



63 



GENERATING SWITCHING 
SEQUENCES 

In addition to selecting a motor and deter- 
mining power-stage design, you must also 
decide how to generate the switching sequences 
that step the motor. Programming a y.C or using 
a special piece of hardware called a translator 
accomplishes this task. 

Software translation is more economical, and it 
is the first choice for large-volume products. 
Fig. A shows a basic step procedure la) that 
you can integrate into a routine lb); the routine 
executes a clockwise rotation of N steps at a 
fixed rate. The step rate is defined by a soft- 
ware loop, but you can also use programmed 
timer in terrup ts. 

Fig. A - A mC can generate the phase sequence 
(a) for a stepper motor. A routine (b) expands 
a single-step routine into are that executes a 
move of N steps 



f CLOCKWISE "\ 
^STEP ROUTINE^ 



PHASE 

SEQUENCE 

LOOKUP 

TABLE 



/beyond\ 

< END OF . 
V TABLE?/ 


.YES 






1 


NO 




RESTORE 
POINTER TO 
TOP OF TABLE 


' 


„ 












FETCH NIBBLE 
FROM TABLE 




1 




OUTPUT TO 
MOTOR PORT 




i 






( COM 


LETE 


) 



/fa0VE N STEP3\ 
V ROUTINE J 



b) 




A simpler approach uses the software equi- 
valent of a shift register. For example, you can 
load a 99 (hex) into a register and take the 
phases from bits to 3. A Rotate Left instruc- 
tion yields a clockwise step; a Rotate Right 
instruction causes a counterclockwise move. 

When software translation ties up your y.C, 
lighten the load by adding a hardware translator. 
In applications involving unidirectional motors, 
this logic circuit (Fig. B) requires only one 
pulse for each step; you 'II also need a direction 
signal (b) if your motor rotates in both direc- 
tions. By adding a 7408 to a 2-phase translator, 
you can satisfy a wave-drive application (c), 
while the addition of two OR gates provides 
fast turnoff in wave-drive mode. 

Fig. B - Built a simple 2-phase hardware trans- 
lator using a dual flip-flop, for single (a) or 
bidirectional (b) rotation. Add some extra 
ICs for wave-drive signals (c) and to provide 
fast turn-off (d) 



a) 



b) 




n=)t> 



x> 



D 



-• OD 



_™ 



CP ^ Q 



C) 




d) 




64 



Often a mC controls the translator, setting the 
direction line and providing a pulse for each 
step. Software is thus simplified, and if you use 
a programmed interrupt scheme, the tiC is free 
to handle other tasks. Fig. C describes an ab- 
solute-positioning routine for a step with a 
direction-control translator; Fig. D outlines 
how programmed timer interrupts are used to 



Fig. C - For use with a hardware 
| translator this a absolute-positioning 
1 routine sets the direction line and 

sends the appropriate number of 

step pulses. 



relieve the burden on the nC. 
Two special cases call for hardware translation. 
The first is in a system for which you have 
already designed in control circuitry to provide 
step and direction signals. The second case 
involves single-quantity and small-run applica- 
tions, in which the cost of a few ICs is a small 
price to pay for simplified software. 



NOTES 

ENTER vV'TH DESIRED PCS JIOK 
CURRENT POSITION IS iN REGISTER 
OB MEMORY LOCAHON 




SUBTRACT CURRENT 

FROM DESIRED LOCATION 

TO FIND DISTANCE 




Fig. D - To set a motor step rate, 
used programmed timer interrupts 
in place of software timing loops. 



( INITIALIZATION 
V. ROUTINE 


) 


1 


SET DIRECTION 
LINE 


. 


INITIALIZE 

TIMER 

INTERRUPTS 


1 


r COMPLETE 


) 



(_ INTERRUPT- ") 



T'MEP 
INTERRUPT 
SERVICE 



DECREMENT 

STEPSTO-GO 

COUNT 




DE-INITIALIZE 

TIMER 
INTERRUPTS 



65 



CHOPPER CIRCUIT OFFERS MORE 
ENHANCEMENTS 

Adding a chopper circuit to maintain a constant- 
average phase current improves performance and 
efficiency. Fig. 3 shown a simple constant-current 
drive that employs a dual bridge, dual comparator 
and a few passive components. This circuit requires 
an L293E, because this dual-bridge IC offers 
access to the lower emitter connections, thus 
letting you Insert current-sensing resistors. 

Operation of this fixed-ripple chopper drive is 
straightforward. When the mC or translator acti- 
vates a bridge, the increasing load current raises the 
voltage across the sensing resistor until it equals the 
comparator's reference voltage. The comparator 
then switches, clamping the translator signals 
through the diodes to deactivate the bridge. As the 
current decays, the voltage across the sensing re- 
sistor decreases until it equals the comparator's 
lower threshold. The comparator switches again, 
allowing the mC or translator to activate a bridge 
and restart the cycle. As long as the translator 
drives the biidge, this sequence repeats to provide a 
constant-average phase current with fixed ripple. 

V ref adjusts the lower current limit, while the com- 
parator's hysteresis sets the rippie, and hence the 
peak current. Although a aivider establishes the 
value of V ref in this case, you can employ the 



dual-supply design approach and switch V re f to a 
lower value when the motor is idle. In addition, use 
of a D/A converter establishes V re! for micro- 
stepping applications. This drive circuit, with its 
fixed-ripple current characteristics, is well suited 
for such service. 



FIXED-FREQUENCY CHOPPER IS 
MOTOR INDEPENDENT 

Fig. 3's drive has some disadvantages. First, the 
chopper frequency depends on motor characte- 
ristics, and these parameters vary from unit to unit. 
In addition, it's impossible to synchronize the 
choppers, and this shortcoming can cause trouble 
on the ground plane. 

Using a flip flop/comparator arrangement (Fig. 4) 
to develop a fixed-frequency chopper overcomes 
these problems. In this circuit, the NE555 timer 
generates negative pulses that reset the flip flops to 
enable the phase-control signals from the trans- 
lator. If these signals are set to energize a winding, 
the current in that winding rises until the voltage 
across the sensing resistor switches the comparator, 
thus setting the flip flop. This disables the phase 
signals and deactivates the bridge. Current in the 
winding falls until the next clock pulse resets the 
flip flop, and the sequence repeats to maintain a 
constant current. 



Fig. 4 - This fixed-frequency constant-current chopper driver enables the synchronization of several 
drives, thus minimizing potential ground-plane problems. 




I^I-l 



66 



Fig. 5 - A special translator-chopper control circuit cuts the drivers components count to the minimum 




z 1 "ir 



CONTROLLER IC REDUCES 
COMPONENT COUNT 

If you're using a hardware translation and constant- 
current choppers, you can further reduce the com- 
ponent count by using a controller chip such as the 
L297 — a 20-pin DIP that houses a translator and a 
dual fixed-frequency chopper circuit. Under the 
control of step and direction inputs, the L297 
generates normal, wave-drive and half-step se- 
quences. 

As shown in Fig. 5, the controller connects directly 



to a dual bridge. External component requirements 
are minimal: and RC network to set the chopper 
frequency and a resistive divider to establish the 
comparator reference voltage (V re fi. 

To accommodate motors with a phase current as 
great as 3.5A, replace the single dual-bridge IC 
with two devices configured in parallel (input to 
input, enable to enable, etc) to form a single bridge. 
It's extremely important that you pair the half 
bridges — 1 with 4 and 2 with 3 — to ensure op- 
timum current sharing. 



Reprinted from EDN. 11/24/83 

©1986 Cahners Publishing Company Division 
of Reed Publishing USA. 



67 



INTRODUCING THE L297 
STEPPER MOTOR CONTROLLER 

The L297 integrates all the control circuitry required to control bipolar and unipolar stepper 
motors. Used with a dual bridge driver such as the L298N forms a complete micropro- 
cessor-to-bipolar stepper motor interface. Unipolar stepper motor can be driven with an 
L297 plus a quad darlington array. This note describes the operation of the circuit and 
shows how it is used. 



The L297 Stepper Motor Controller is primarily 
intended for use with an L298N or L293E bridge 
driver in stepper motor driving applications. 

It receives control signals from the system's con- 
troller, usually a microcomputer chip, and provides 
all the necessary drive signals for the power stage. 
Additionally, it includes two PWM chopper circuits 
to regulate the current in the motor windings. 

With a suitable power actuator the L297 drives two 
phase bipolar permanent magnet motors, four 
phase unipolar permanent magnet motors and four 
phase variable reluctance motors. Moreover, it 
handles normal, wave drive and half step drive 
modes. (This is all explained in the section "Stepper 
Motor Basics"). 

Two versions of the device are available: the regular 



L297 and a special version called L297A. The 
L297A incorporates a step pulse doubler and is 
designed specifically for floppy-disk head posi- 
tioning applications. 

ADVANTAGES 

The L297 + driver combination has many ad- 
vantages: very few components are required (so 
assembly costs are low, reliability high and little 
space required), software development is simplified 
and the burden on the micro is reduced. Further, 
the choice of a two-chip approach gives a high 
degree of flexibility - the L298N can be used on 
its own for DC motors and the L297 can be used 
with any power stage, including discrete power 
devices (it provides 20mA drive for this purpose). 



Fig. I - In this typical configu- 
ration an L297 stepper 
motor controller and L298 
dual bridge driver combine 
to form a complete micro- 
processor to bipolar step- 
per motor interface. 



^TEP CLOCK _ 
HALF/FULL STEP 



HOPPER M0CE_ 
HOME 



■\ CHOPPEI 
LJ RATE 



PHASE A 
PHASE B 



SEJUE l 
SENSE < 



o 9 



tUL 



: | STEPPER 

i ; MOTOR 



+ *** 



t> n cep» en , 



69 



For bipolar motors with winding currents up to 
2.5A the L297 should be used with the L298N; for 
winding currents up to 1A the L293E is recom- 
mended (the L293 will also be useful if the chopper 
isn't needed). Higher currents are obtained with 
power transistors or darlingtons and for unipolar 
motors a darlington array such as the L7180 is 
suggested. The block diagram, figure 1, shows a 
typical system. 

Applications of the L297 can be found almost 
everywhere. . . . printers (carriage position, daisy 
position, paper feed, ribbon feed), typewriters, 
plotters, numerically controlled machines, robots, 
floppy disk drives, electronic sewing machines, 
cash registers, photocopiers, telex machines, 
electronic carburetors, telecopiers, photographic 
equipment, paper tape readers, optical character 
recognisers, electric valves and so on. 

The L297 is made with SGS' analog/digital com- 
patible l 2 L technology (like Zodiac) and is as- 
sembled in a 20-pin plastic DIP. A 5V supply is 
used and all signal lines are TTL/CMOS compatible 
or open collector transistors. High density is one 
of the key features of the technology so the L297 
die is very compact. 



THE L298N AND L293E 

Since the L297 is normally used with an L298 or 
L293E bridge driver a brief review of these devices 
will make the rest of this note easier to follow. 

The L298N and L293E contain two bridge driver 
stages, each controlled by two TTL-level logic 
inputs and a TTL-level enable input. In addition, 
the emitter connections of the lower transistors are 
brought out to external terminals to allow the con- 
nection of current sensing resistors (figure 2). 

For the L298N SGS' innovative ion-implanted high 
voltage/high current technology is used, allowing it 
to handle effective powers up to 200W (46V 
supply, 2.5A per bridge). A separate 5V logic 
supply input is provided to reduce dissipation and 
to allow direct connection to the L297 or other 
control logic. 

In this note the pins of the L298N are labelled with 
the pin names of the corresponding L297 terminals 
to avoid unnecessary confusion. 

The L298N is supplied in a 15-lead Multiwatt® plas- 
tic power package. It's smaller brother, the func- 
tionally identical L293E, is packaged in a Powerdip 
— a copper frame DIP that uses the four center 
pins to conduct heat to the circuit board copper. 



Fig. 2 - The L298N contains two bridge drivers (four push pull stages) each controlled by two logic 
inputs and an enable input. External emitter connections are provided for current sense 
resistors. The L293E has external connections for all four emitters. 



OUT? 





T 



7CH < >^<^ 



"Tt>-<>-0: 



7CK >t<3-; 



4- 



£>-<>■ -err' 



D 
fNH~2 



6 

SENSE 2 



STEPPER MOTOR BASICS 

There are two basic types of stepper motor in com- 
mon use: permanent magnet and variable reluc- 
tance. Permanent magnet motors are divided into 
bipolar and unipolar types. 



Bipolar motors 

Simplified to the bare essentials, a bipolar per- 



manent magnet motor consists of a rotating per- 
manent magnet surrounded by stator poles car- 
rying the windings (figure 3). Bidirectional drive 
current is used and the motor is stepped by swit- 
ching the windings in sequence. 

For a motor of this type there are three possible 
drive sequences. 

The first is to energize the windings in the sequence 
AB/CD/BA/DC (BA means that the winding AB is 



70 



Fig. 3 - Greatly simplified, a bipolar permanent 
magnet stepper motor consist of a rotating 
magnet surrounded by stator poles as 
shown. 




energized but in the opposite sense). This sequence 
is known as "one phase on" full step or wave drive 
mode. Only one phase is energized at any given 
moment (figure 4a). 

The second possibility is to energize both phases 
together, so that the rotor always aligns itself bet- 
ween two pole positions. Called "two-phase-on" 
full step, this mode is the normal drive sequence 
for a bipolar motor and gives the highest torque 
(figure 4b). 

The third option is to energize one phase, then two, 
then one, etc., so that the motor moves in half step 
increments. This sequence, known as half step 
mode, halves the effective step angle of the motor 
but gives a less regular torque (figure 4c). 

For rotation in the opposite direction (counter- 
clockwise) the same three sequences are used, 
except of course that the order is reversed. 

As shown in these diagrams the motor would have 
a step angle of 90°. Real motors have multiple 
poles to reduce the step angle to a few degrees but 
the number of windings and the drive sequences 
are unchanged. A typical bipolar stepper motor is 
shown in figure 5. 



Fig. 4 - The three drive sequences for a two phase bipolar stepper motor. Clockwise rotation is shown. 
Fig. 4a - Wave drive (one phase on) 







Fig. 4b - Two phase on drive 







Fig. 4c - Half step drive 










71 



Fig. 5 - A real motor. Multiple poles are normally 
employed to reduce the step angle to a 
practical value. The principle of operation 
and drive sequences remain the same. 



FM ROTOR — 



STATOR A ~tV 




J^ 



Unipolar motors 

A unipolar permanent magnet motor is identical to 
the bipolar machine described above except that 
bifilar windings are used to reverse the stator flux, 
rather than bidirectional drive (figure 6). 

This motor is driven in exactly the same way as a 
bipolar motor except that the bridge drivers are 
replaced by simple unipolar stages — four darling- 
tons or a quad darlington array. Clearly, unipolar 
motors are more expensive because thay have twice 
as many windings. Moreover, unipolar motors give 
less torque for a given motor size because the 
windings are made with thinner wire. In the past 
unipolar motors were attractive to designers 
because they simplify the driver stage. Now that 
monolithic push pull drivers like the L298 are 
available bipolar motors are becoming more 
popular. 

All permanent magnet motors suffer from the 
counter EMF generated by the rotor, which limits 
the rotation speed. When very high slewing speeds 
are necessary a variable reluctance motor is used. 



Fig. 6 ■ 



A unipolar PM motor uses bifilar windings 
to reverse the flux in each phase. 



ni 




Variable reluctance motors 

A variable reluctance motor has a non-magnetized 
soft iron rotor with fewer poles than the stator 
(figure 7). Unipolar drive is used and the motor is 
stepped by energizing stator pole pairs to align the 
rotor with the pole pieces of the energized winding. 

Once again three different phase sequences can be 
used. The wave drive sequence is A/C/B/D; two- 
phase-on is AC/CB/BD/DA and the half step se- 
quence is A/AC/C/BC/B/BD/D/DA. Note that the 
step angle for the motor shown above is 15°C, 
not 45° . 

As before, practical motors normally employ 
multiple poles to give a much smaller step angle. 
This does not, however, affect the principle of 
operation or the drive sequences. 

Fig. 7 - A variable reluctance motor has a soft 

iron rotor with fewer poles than the 

stator. The step angle is 75° for this 
motor. 




GENERATING THE PHASE SEQUENCES 

The heart of the L297 block diagram, figure 8, is 
a block called the translator which generates 
suitable phase sequences for half step, one-phase-on 
full step and two-phase-on full step operation. 
This block is contr olled by two mode inputs — 
direction (CW/CCW) and HALF/FULL - and a 
step clock which advances the translator from one 
step to the next. 

Four outputs are provided by the translator for 
subsequent processing by the output logic block 
which implements the inhibit and chopper func- 
tions. 

Internally the translator consists of a 3-bit counter 
plus some combinational logic which generates a 
basic eight-step gray code sequence as shown in 
figure 9. All three drive sequences can be generated 
easily from this master sequence. This state se- 
quence corresponds directly to half step mode, 
selected by a high level on the HALF/FULL input. 



72 



The output waveforms for this sequence are shown 
in figure 1 0. 



Note that two other signals, INH1 and INH2 are 
generated in this sequence. The purpose of these 
signals is explained a little further on. 

The full step modes are both obtained by skipping 
alternate states in the eight-step sequence. What 
happens is that the step clock bypasses the first 
stage of the 3-bit counter in the translator. The 
least significant bit of this counter is not affected 



therefore the sequence generated depends on the 
state of the translat or wh en full step mode is 
selected (the HALF/FULL input brought low). 

If full step mode is selected when the translator is 
at any odd-numbered state we get the two-phase- 
on full step sequence shown in figure 1 1 . 

By contrast, one-phase-on full step mode is ob- 
tained by selecting full step mode when the trans- 
lator is at an even-numbered state (figure 12) . 



Fig. 8 



The L297 contains translator (phase sequence generator), a dual PWM chopper and output 
control logic. 



HA. F. 'FULL 
S'EO 



DIRECTION 
ICW/CCW) 



OUTPUT LOGIC 







a s — * — s q 



R >— — C R 



> 





-O ENABLE 
-O CONTROL 



6^6 

SENS ' V re) SENS 2 



Q S-S6 38 

osc 



Fig. 9 - The eight step 
master sequence 
of the translator. 
This corresponds 
to half step mode 
Clockwise rota- 
tion is indicated. 



100! 1000 




3 >-»j i, j- 

1 "T J 

0001 2 

oioi ! i |» A 8 •» 


»i 5 ! .10!0 
6 0010 

— i 7 


HOME 0100 


0110 



Fig. 10- The output waveforms corresponding to the half step 
sequence. The chopper action in not shown. 



nnnrrinrTTnnnnnr 



i_r 



i_ 



i_r 



i_r 



i_ 



i_r 



i__r 



73 



Fig. 11 - State sequence and output waveforms for the two phase on sequence. INH1 and INH2 
remain high throughout. 




1 357135713 57 

nnnrTinnnnnnnnr 
i i L_j — L__r 

I I I I I L_ 



oioiTG H E7 oho 

HOME^-- -^ D 



1 I L 



i r 



i r 



Fig. 12 - State sequence and output waveforms for wave drive lone phase on). 

2 4 6 8 2 4682466 

clock TTTTTTTTTTTTT" 

* _n n n r 




_t~l 



j~l 



m h h 



_n 



_n_ 



n 



_n_ 



_n 



J~~L_ 




INH1 AND INH2 

In half step and one-phase- on fu ll ste p mod es two 
other signals are generated: INH1 and INH2. These 
are inhibit signals which are coupled to the L298N's 
enable inputs and serve to speed the current decay 
when a winding is switched off. 

Since both windings are energized continuously in 
two-phase-on full step mode no winding is ever 
switched off and these signals are not generated. 

To see what these signals do let's look at one half 
of the L298N connected to the first phase of a two- 
phase bipolar motor (figure 13). Remember that 
the L298N's A and B inputs determine whichjran- 
sistor in each push pull pair will be on. INH1, on 
the other hand, turns off all four transistors. 

Assume that A is high, B low and current flowing 
through Q1 , Q4 and the motor winding. If A is 
now brought low the current would recirculate 
through D2, Q4 and R s , giving a slow decay and in- 



creased dissipation in R,. If , on the other hand, A 
is brought low and ll\)H1 is activated, all four 
transistors are turned off. The current recirculates 
in this case from ground to V s via D2 and D3, 
giving a faster decay thus allowing faster operation 
of the motor. Also, since the recirculation current 
does not flow through R s , a less expensive resistor 
can be used. 

Exactly the same thing happens with the second 
winding, the ot her half of the L298 and the signals 
C, D and INH2. 



The INH1 and INH2 signals are generated by OR 
functions: 



A + B ■■ 



INH1 



C + D = INH2 



However, the output logic is more complex because 
the inhibit lines are also used by the chopper, as 
we will see further on. 



74 



Fig 13 - When a winding is switched off the inhibit input is activated to speed current decay. If this were 
not done the current would recirculate through D2 and Q4 in this example. Dissipation in R s 
is also reduced. 

v s 

•'I 
I 



rzOfo 



aO- 




DRIVE CURRENT ►- 

RECIRCULATION ►- 



OTHER SIGNALS 

Two other signals are connected to the translator 
block: the RESET input and the HOME output. 

RESET is an asynchronous reset input which 
restores the translator block to the home position 
(state 1, ABCD = 0101). The HOME output (open 
collector) signals this condition and is intended to 
be ANDed with the output of a mechanical home 
position sensor. 

Finally, there is an ENABLE input connected to 
the o ut put lo gic. A low level on this input brings 
INH1, INH2, A, B, C and D low. This input is 
useful to disable the motor driver when the system 
is initialized. 



LOAD CURRENT REGULATION 

Some form of load current control is essential to 
obtain good speed and torque characteristics. 
There are several ways in which this can be done — 
switching the supply between two voltages, pulse 
rate modulation chopping or pulse width modu- 
lation chopping. 

The L297 provides load current control in the 
form of two PWM choppers, one for each phase of 
a bipolar motor or one for each pair of windings 
for a unipolar motor. (In a unipolar motor the A 
and B windings are never energized together so 
thay can share a chopper; the same applies to C 
and D). 

Each chopper consists of a comparator, a flip flop 
and an external sensing resistor. A common on- 
chip oscillator supplies pulses at the chopper rate 
to both choppers. 



In each chopper (figure 14) the flip flop is set by 
each pulse from the oscillator, enabling the output 
and allowing the load current to increase. As it 
increases the voltage across the sensing resistor in- 
creases, and when this voltage reaches V ref the flip 
flop is reset, disabling the output until the next 
oscillator pulse arrives. The output of this circuit 
{the flip flop's Q output) is therefore a constant 
rate PWM signal. Note that V ref determines the 
peak load current. 



Fig. 14 - Each chopper circuit consists of a comp- 
arator, flip flop and external sense resis- 
tor. A common oscillator clocks both 
circuits. 



"innr 




T'LOAD 



"LTLr 




75 



PHASE CHOPPING AND INHIBIT 
CHOPPING 

The chopper can act on eithe r the phas e line s 
(ABCD) or on the inhibit lines INH1 and INH2. 
An input named CONTROL decides which. Inhibit 
chopping is used for unipolar motors but you can 
choose between phase chopping and inhibit chop- 
ping for bipolar motors. The reasons for this choice 



are best explained with another example. 

First let's examine the situation when the phase 

lines are chopped. 

As before, we are driving a two phase bipolar 
motor and A is high, B low (figure 15). Current 
therefore flows through CM , winding, Q4 and R s . 
When the voltage across R s reaches V re f the 
chopper brings B high to switch off the winding, - 



Fig. 15 - Phase chopping. In this example the current X is interrupted by activating B, giving the recir- 
culation path Y. The alternative, de-activating A, would give the recirculation path Z, increas- 
ing dissipation in R s . 



A 
O- 



7D«i 



1 I 1 ^ T 

ijrjv-— "i 



-t 



"-+-* — j 



INHI 

o— 



to=@ 



^ 



OJ 






1 1 



The energy stored in the winding is dissipated by 
current recirculating through Q1 and D3. Current 
decay through this path is rather slow because the 
voltage on the winding is low (V CEsat Q1 + V D3 ) 
(figure 16). 

Why is B pulled high, why push A low? The reason 



is to avoid the current decaying through R s . Since 
the current recirculates in the upper half of the 
bridge, current only flows in the sensing resistor 
when the winding is driven. Less power is therefore 
dissipated in R s and we can get away with a 
cheaper resistor. 



Fig. 16 - Phase chopping waveforms. The example shows AB winding energized with A positive with 
respect to B. Control is high. 



^CHOPPER OSC. PERIOD 




NOTE THAT CURREN T !\ 
SENSE RESISTOR IS 
TERMIT T ENT 



THROUGH q! AND 03 



76 



This explains why phase chopping is not suitable 
for unipolar motors: when the A winding is driven 
the chopper acts on the B winding. Clearly, this is 
no use at all for a variable reluctance motor and 
would be slow and inefficient for a bifiiar wound 
permanent magnet motor. 



The alternative is to tie the CONTROL input to 
groun d so that the chopper acts on INH1 and 
INH2. Looking at the same example, A is high and 
B low. Q1 and Q4 are therefore conducting and 
current flows through Q1 , the winding, Q4 and R s 
(figure 17). 



Fig. 17 - inhibit chopping. The drive current (Q1 , winding, Q4) in this case is interrupted by activating 
INH1. The decay path through D2 and 03 is faster than the path Y of figure 15. 



-D<& 



TO' 



3>0 



—>t - ♦ 



-T ! 



_ .j .^l 



®fO 



L If 1 



DRIVE CURRENT 

RECIRCULATION 



In this case when the voltage across R 5 re aches 
V REF the chopper flip fiop is reset and INH1 
activated (brought low). INH1, remember, turns 
off all four transistors therefore the current recir- 
culates from ground, through D2, the winding and 
D3 to V s . Discharged across the supply, which can 
be up to 46V, the current decays very rapidly 
(figure 18). 

The usefulness of this second faster decay option 
is fairly obvious; it allows fast operation with 
bipolar motors and it is the only choice for uni- 
polar motors. But why do we offer the slower 
alternative, phase chopping? 

The answer is that we might be obliged to use a 
low chopper rate with a motor that does not store 
much energy in the windings. If the decay is very 
fast the average motor current may be too low to 
give an useful torque. Low chopper rates may, for 
example, be imposed if there is a larger motor in 
the same system. To avoid switching noise on the 
ground plane all drivers should be synchronized 
and the chopper rate is therefore determined by 
the largest motor in the system. 

Multiple L297s are synchronised easily using the 
SYNC pin. This pin is the squarewave output of 
the on-chip oscillator and the clock input for the 
choppers. The first L297 is fitted with the oscil- 
lator components and outputs a squarewave signal 



on this pin (figure 19). Subsequent L297s do not 
need the oscillator components and use SYNC as a 
clock input. An external clock may also be injected 
at this terminal if an L297 must be synchronized to 
other system components. 



Fig. 18- Inhibit chopper waveforms. Winding AB 
is energized and CONTROL is low. 




11 



Fig. 19- The chopper oscillator of multiple L297s 
are synchronized by connecting the 
SYNC inputs together. 




THE L297A 

The L297A is a special version of the L297 devel- 
oped originally for head positioning in floppy disk 
drives. It can, however, be used in other appli- 
cations. 



Compared to the standard L297 the differences are 
the addition of a pulse doubler on the step clock 
input and the availability of the output of the 
direction flip flop (block diagram, figure 20). To 
add these functions while keeping the low-cost 
20-pin package the CONTROL and SYNC pins are 
not available on this version (they are not needed 
anyway). The chopper acts on the ABCD phase 
lines. 

The pulse doubler generates a ghost pulse inter- 
nally for each input clock pulse. Consequently the 
translator moves two steps for each input pulse. 
An external RC network sets the delay time bet- 
ween the input pulse and ghost pulse and should 
be chosen so that the ghost pulses fall roughly 
halfway between input pulses, allowing time for 
the motor to step. 

This feature is used to improve positioning accu- 
racy. Since the angular position error of a stepper 
motor is noncumulative (it cancels out to zero 
every four steps in a four step sequence motor) 
accuracy is improved by stepping two or four steps 
at a time. 



Fig. 20- The L297A, includes a clock pulse doubler and provides an output from the direction flip 
flop (DIR - MEM). 



HALF/FULL r 
STEP u ~ 

RESET O— 

ccw/ccw o— 



A 1NH1 B C 1NH2 D 

9 T T T ? T 



TRANSLATOR 



OUTPUT LOGIC 




DOUBLER GND 



6 6 

HOME SENS 1 V ref SENS 2 



APPLICATION HINTS 

Bipolar motors can be driven with an L297, an 
L298N or L293E bridge driver and very few external 
components (figure 21). Together these two chips 
form a complete microprocessor-to-stepper motor 
interface. With an L298N this configuration drives 



motors with winding currents up to 2.5A; for 
motors up to 1A per winding an L293E is used. If 
the PWM choppers are not required an L293 could 
also be used (it doesn't have the external emitter 
connections for sensing resistors) but the L297 is 
underutilized. If very high powers are required the 
bridge driver is replaced by an equivalent circuit 



78 



Fig. 21 - This typical application shows an L297 and L298N driving a bipolar stepper motor with phase 
currents up to 2 A 



Q5V 



3.3nF 31 



GND 
CW/CCW 



±1 



CLOCK 



Vref 



L297 



6 
7 
20 9 

10 5 

15 8 

11 1 3 13 U 



Q36V 



s. 



t T T 

D2|_ D3 



L298N 

12 13 



CONTROL I t IHOME 
SYNC. 



R S1 R S2 = °- 5n 



D4 
t t % ii 



t A A A 



STEPPER 

MOTOR 

WINDINGS 



H 



D1 to D8 = 2 Fast Diodes 



V F < 1 ,2V <s> I = 2A 
trr < 200 ns 



made with discrete transistors. For currents up to 
3.5A two L298N's with paralleled outputs may be 
used. 

For unipolar motors the best choice is a quad 
darlington array. The L702 can be used if the 
choppers are not required but an L7150 or L7180 



emitter connections which are connected to 
sensing resistors (figure 22). Since the chopper acts 
on the inhibit lines, four AND gates must be added 
in this application. 

Also shown in the schematic is a zener diode in 
series with the suppression diodes. This serves to 



is preferred. These quad darlingtons have external increase the voltage across which energy stored in 



Fig. 22 - For unipolar motors a quad darlington array is coupled to the L297. Inhibit chopping is used 
so the four AND gates must be added. 




^-®| Hgf 



m 



L7150/2 
L7160/2 



^ 




79 



the winding is discharged and therefore speed the 
current decay. 

in all applications where the choppers are not used 
it is important to remember that the sense inputs 
must be grounded and V REF connected either to 
V s or any potential between V s and ground. 



The chopper oscillator frequency is determined by 
the RC network on pin 16. The frequency is 
roughly 1/0.7 RC and R must be more than 10KO. 
When the L297A's pulse doubler is used, the delay 
time is determined by the network R d C d and is 
approximately 0.75 R d C d .R d should be in the 
range 3 kn- 100 kn (figure 23). 



Fig. 23 - The clock pulse doubler inserts a ghost pulse t seconds after the input dock pulse. R d C d i 
closen to give a delay of approximately half the input clock period. 




To 



"U~"n_r 



"LT 



PULSE 

DOUBLER 

OUTPUT 



U U LT 



PIN FUNCTIONS - L297 



NAME 



FUNCTION 



SYNC 



Output of the on-chip chopper oscillator. 
The SYNC connections of all L297s to be synchronized 
are connected together and the oscillator components 
are omitted on all but one. If an external clock source 
is used it is injected at this terminal. 



GND 



HOME 



INH1 



Ground connection. 



Open collector output that indicates when the L297 is 

in its initial state (ABCD = 0101). 

The transistor is open when this signal is active. 

Motor phase A drive signal foi power stage 



Active low inhibit control for driver stages of A and B 
phases. When a bipolar bridge is used this signal can be 
used to ensure fast decay of load current when a winding 
is de-energized. Also used by chopper to regulate load 
current if CONTROL input is low. 



Motor phase B drive signal for power stage. 



80 



PIN FUNCTIONS- L297 (continued) 



11 CONTROL 



N° 


NAME 


FUNCTION 


7 


C 


Motor phase C drive signal for power stage. 








8 


INH2 


Active low inhibit control for drive stages of C and D 
phases. Same functions as INH1. 


9 


D 


Motor phase D drive signal for power stage. 




ENABLE 




10 


Chip enable input. When low (inactive) INH1, INH2, A, 
B, C and D are brought low. 



Control input that defines a ction of chopper. 

When low chopper acts on INH1 and INH2; when high 

chopper acts on phase lines ABCD. 



12 V, 



5V supply input. 



13 SENS-, 



Input for load current sense voltage from power stages 
of phases C and D. 



14 SENS! 



Input for load current sense voltage from power stages 
of phases A and B. 



15 V r , 



Reference voltage for chopper circuit. A voltage applied 
to this pin determines the peak load current. 



16 OSC 



An RC network (R to V cc , C to ground) connected to 
this terminal determines the chopper rate. This terminal 
is connected to ground on all but one device in synchron- 
ized multi - L297 configurations, f = 1/0.69 RC, 
R> 10k.Q. 



CW/CCW 



Clockwise/counterclockwise direction control input. 
Physical direction of motor rotation also depends on 
connection of windings. 

Synchronized internally therefore direction can be 
changed at any time. 



CLOCK 



Step clock. An active low pulse on this input advances 
the motor one increment. The step occurs on the rising 
edge of this signal. 



HALF/FULL 



Half/full step select input. When high selects half step 
operation; when low selects full step operation. One- 
phase-on full step mode is.obtained by selecting FULL 
when the L297's translator is at an even-numbered state. 
Two-phase-on full step mode is set by selecting FULL 
when the translator is at an odd numbered position. 
(The home position is designated state 1 ). 



PIN FUNCTIONS - L297(continued) 



NAME 



FUNCTION 



20 



RESET 



Reset input. An active low pulse on this input restores 
the translator to the home position (state 1, ABCD = 
0101). 



PIN FUNCTIONS - L297A 

Pin function of the L297A are identical to those of the L297 except for pins 1 and 1 1 . 



N° 



NAME 



FUNCTIONS 



OOUBLER 



An RC network connected to this pin determines the 
delay between an input clock pulse and the correspond- 
ing ghost pulse. 



11 



DIR-MEM 



Direction Memory. Inverted output of the direction 
flip flop. Open collector output. 



Fig. 24 - 


Connection diagrams 


















W 












SYNC | 


1 


20 


] RESET 


DOUBLER ( 


1 


2 


j RESET 




GND | 


2 


19 


] HALF/FULL 


GND f 


2 


1 9 


JhaLF/FuTT 




HOME | 


3 


18 


] CLOCK 


HOME [ 


3 


1 8 


J CLOCK 




A I 


<• 


17 


1 cw/ccw 


A [ 


4 


■7 


1 CW/CCW 




1NH 1 1 


5 L297 


16 


1 OSC 


[NHl [ 


5 L297A is 


1 OSC 




B 1 


6 


1 5 


] v ref 


B [ 


5 


1 b 


J v ref 




C | 


' 


1 i. 


] SENS 1 


C [ 


7 


1 A 


] SENS 




1NH 2 1 


e 


1 3 


] SENS 2 


1NH 2 [ 


8 


1 3 


1 SENS 2 




D 1 


9 


1 2 


] V S 


D [ 


9 


1 2 


] v s 




enable] 


10 


1 1 


] CONtROL 


ENABLE [ 


10 




] DIR-MEM 



82 



APPLICATIONS OF MONOLITHIC 
BRIDGE DRIVERS 

-ligh power monolithic bridge drivers are an attractive replacement for discrete transistors 
>nd half bridges in applications such as DC motor and stepper motor driving. This appli- 
ation guide describes three such devices - the L293, L293E and L298 - and presents 
Practical examples of their application. 



Fhe L293, L293E and L298 each contain four 
Dush-pull power drivers which can be used in- 
dependently or, more commonly, as two full 
5ridges. Each driver is controlled by a TTL-level 
ogic input and each pair of drivers is equipped 
with an enable input which controls a whole bridge. 
Ml three devices feature a separate logic supply 
nput so that the logic can be run on a lower 
;upply voltage, reducing dissipation. This logic 
;upply is internally regulated. 

\dditionally, the L293E and L298 are provided 
vith external connections to the lower emitters of 



each bridge to allow the connection of current 
sense resistors. The L293E has separate emitter 
connections for each channel; the L298 has two, 
one for each bridge. 

Figure 1 shows the internal structure of the L293, 
L293E and L298. The L293 and L293E are 
represented as four push pull drivers while the in- 
ternal schematic is given for the L298. Though 
they are drawn differently the L293E and L298 
are identical in structure; the L293 differs in that it 
does not have external emitter connections. 



ig. I - The L293, L293E and L298 contain four push pull drivers. Each driver is controlled by a logic 
input and each pair (a bridge) is controlled by an enable input. Additionally, the L293E has 
external emitter connections for each driver and the L298 has emitter connections for each 
bridge. 





83 



Fig. 1 (continued) 




Thel_293 is packaged in a 12 +4 lead POWERDIP 
package (a 16-pin DIP with the four center leads 
used to conduct heat to the PC board copper) and 
handles 1A per channel (1.5 peak) at voltages up 
to 36V. 

The L293E, also rated at 1A/36V, is mounted in a 
16+4 lead POWERDIP package. A 15-lead 
MULT I WATT plastic power package is used for 
the L298N which handles up to 2A per channel at 
voltages to 46V. 

All three devices includes on-chip thermal protec- 
tion and feature high noise immunity. The high 
switching speed makes them particularly suitable 
for switch mode control. 



Fig. 2 - For higher currents outputs can be pa- 
ralleled. Take care to parallel channel 1 
with channel 4 and channel 2 with 
channel 3. 




PARALLELING OUTPUTS 

Higher output currents can be obtained by paralle 
ing the outputs of both bridges. For example, th 
outputs of an L298N can be connected in paralle 
to make a single 3.5A bridge. To ensure that th 
current is fairly divided between the bridges the 1 
must be connected as shown in figure 2. In othe 
words, channel one should be paralleled wit 
channel four and channel two paralleled witl 
channel three. Apart from this rule the connectio 
is very straightforward — the inputs, enables, oul 
puts and emitters are simply connected togethei 

The outputs of an L293 or L293E can also b 
paralleled — in this case too channel 1 must b 
paralleled with channel 4 and channel 2 wit 
channel 3. 

But if two bridges are needed this is not a gooi 
idea because an L298N may be used. However, 
only one bridge is required an L293 connected as 
single bridge may be cheaper than an underutilize 
L298N. 



SHORT CIRCUIT PROTECTION 

L293 and L298N drivers can be damaged by shorl 
circuits from the output to ground or to the supply 
Short circuits to ground are by far the most con 
mon and can be protected against by the circu 
shown in figure 3. 

When the output is short circuited the input 
pulled low after a delay of roughly 10 jus, a perioj 
determined by the RC time constant. The uppi 
transistor of the output stage is thus turned of 
interrupting the short circuit current. When tr 
short is removed the circuit recovers automatical! 
This is shown by the waveforms of figure 4. 

Note that if the short circuit is removed while \) 
is high the output stays low because the capacit 
C is charged to V !H . The system is reset by tl 
falling edge of V1, which discharges C. 



84 



Fig. 3 



This circuit protects a driver from out- 
put short circuits to ground. 

R=K>KU 



Fig. 5 - For rotation in one direction DC motors 
are driven by one channel and can be 
connected to supply or ground. 




SHORT CIRCUIT 



Fig. 4 - Waveforms illustrating the short circuit 
protection provided by the circuit of 
fig. 3. 



r 



v 



r 




Vinh 


A 


M1 


B 


M2 


H 


H 


Fast motor 
stop 


H 


Run 


H 


L 


Run 


L 


Fast motor 
stop 


L 


X 


Free running 
motor stop 


X 


Free running 
motor stop 



L = Low H= High X= Don't care 



Fig. 6 - A bridge is used for bidirectional drive 
of DC motors. 



DC MOTOR DRIVING 

In applications where rotation is always in the 
same sense a single driver (half bridge) can be used 
to drive a small DC motor. The motor may be con- 
nected either to supply or to ground as shown in 
figure 5. 

The only difference between these two alternatives 
is that the control logic is inverted — a useful fact 
o remember when minimising control logic. 

Each device can drive four motors connected in 
this way. The maximum motor current is 1 A for the 
L293 and 2A for the L298N. However if several 
notors are driven continuously care should be 
:aken to avoid exceeding the maximum power 
Jissipation of the package. 

Each motor in this configuration is controlled by 
ts own logic input which gives two alternatives: 
un and fast stop (the motor shorted by one of the 
:ransistors). 

The enable/inhibit inputs also allow a free running 
riotor stop by turning off both transistors of the 
iriver. Since these inputs are common to two 
:hannels (one bridge) this feature can only be used 
'hen both channels are disabled together. 

\ full bridge configuration is used to drive DC 
notors in both directions (figure 6). Using the 
ogic inputs of the two channels the motor can be 




INPUTS 


FUNCTION 


Vinh = 


H 


C= H; 


D = L 


Turn right 


C= L; 


D = H 


Turn left 


C« D 


Fast motor stop 


Vinh = 


L 


C= X; 


D = X 


Free running 
motor stop 



L = Low 



H = High 



X = Don't care 



made to run clockwise, run anticlockwise or stop 
rapidly. 

Again, the enable/inhibit input is used for a free 
running stop — it turns off all four transistors of 



85 



the bridge when low. A very rapid stop may be 
achieved by reversing the current, though this 
requires more careful design to stop the motor 
dead. In practice a tachometer dynamo and closed 
loop control are usually necessary. Like the 
previous circuit, this configuration is suitable for 
motors with currents up to 1A (L293/L293E) 
or 2A (L298N). 

The motor speed in these examples can be con- 
trolled by switching the drivers with pulse width 
modulated squarewaves. This approach is particu- 
larly suitable for microcomputer control. 

For unidirectional drive with a single channel the 
PWM control signal can be applied to either the 
channel input or the appropriate enable input. In 
both cases the recirculation path is through the 
suppression diode and motor, giving a fairly slow 
decay. From a practical point of view it is prefer- 
able to control the channel input because the 
circuit response is faster. This is very convenient 
because each channel has an independent input. 

The situation is different for bidirectional motors 
driven by a bridge. In this case the two alternatives 
have different effects. If the channel inputs are 
driven by the PWM signal, with suitable logic, the 



recirculation path is through a diode, the motor 
and a transistor (figure 7a), giving a slow decay. On 
the other hand, if the enable input is controlled 
the recirculation path is from ground to supply 
through two diodes and the winding. This path 
gives a faster decay (figure 7b). 

Figure 8 shows a practical example of PWM motor 
speed control. This circuit includes the oscillator 
and modulator and allows independent regulation 
of the speeds of the two motors. The channel 
inputs are used to control the direction. 

An interesting feature of this circuit is that it takes 
advantage of the threshold of the enable/inhibit 
input to economise on comparators. The TBA820M 
audio amplifier generates triangle waves, the DC 
level of which is varied from to 5V by means of 
P1 and P2. 

Since the switching threshold of the L293's enable/ 
inhibit inputs is roughly 2V the duty cycle of the 
output current (and hence the motor speed) is 
controlled by the setting of the potentiometer. 

In this circuit the switching frequency is set by R1/ 
C1 and the amplitude of the oscillator signal is set 
by the divider R2/R3. 



Fig. 7a - If the current shown by the solid line is interrupted by bringing A low the current recirculate: 
round the dotted path. Decay is slow. 




Fig. 7b - If the enable input is brought low to interrupt the current indicated by the solid line the curi 
rent recirculates from ground to V s and the decay is faster. 



^O. T 




86 



Fig. 8 - This circuit illustrates PWM control of the motor speed. The speed of each motor is controlled 
independently. 

1 , 



'Ml ' 'M2 =300mA 




^ ^ 



~^b. 



71= 



*= 
*= 



<5>- 



— t 




STEPPER MOTOR DRIVING 

Monolithic bridge drivers are extremely useful for 
stepper motor driving because they simplify the 
use of bipolar motors. This is an important point 
since a bipolar stepper motor costs less than an 
equivalent unipolar motor (it has fewer windings) 
and gives more torque per unit volume, other 
things being equal. 

The basic configuration for bipolar stepper motor 
driving is shown in figure 9. In this example it is 
assumed that a suitable translator (phase sequence 
'generator) is connected to the four channel inputs. 

Either an L293 or an L298N can be used in this 
circuit; an L293E would be wasted compared to 
an L293 because load current regulation, and 
hence the sense resistor connection, is not used. 
But load current regulation is highly desirable to 
sxploit the performance characteristics of the 
motor. Using an L293E or L298N this can be im- 
plemented by adding an LM339 quad comparator 
ss shown in figure 10. 

This is another circuit that requires an external 
iranslator but it provides independent PWM 
;hopper regulation of the current in each winding. 

Rooking at motor phase one, the comparator out- 
)ut is initially high, enabling the bridge through 
>in 1 . 

The current in the motor winding rises until the 
toltage across the sensing resistor R2 produces a 
'oltage at the inverting input of the comparator 
iqual to the voltage on the non-inverting input 
370 mV). This value is produced by the divider 
?10/R11 and by the hysteresis determined by R6 
nd R8. 



At this point the comparator switches, disabling 
the bridge. The current in the winding recirculates 
through D5 and D6 until the voltage across R2 falls 
below the lower threshold of the comparator. The 
comparator then switches again and the cycle 
repeats. 



Fig. 9 - A single device can be used to drive a 
two phase bipolar stepper motor. 




87 



Fig. 10- Two comparators provide chopper current regulation in this bipolar stepper motor drive 
circuit. 




The peak current in each winding is determined by 
V ref (in this case it is0.5A) and the switching rate 
— and hence the average current — depends on the 
hysteresis of the comparator and R4C4. With the 
component values shown the switching frequency 
is roughly 20 kHz. 

The figure 10 circuit uses only half of the LM339 
quad comparator. With the addition of a few extra 
passive components we can take advantage of the 
spare comparators to implement short circuit 
protection. Figure 11 shows how this is done. 

As before, comparators 1 and 2 regulate the cur- 
rent in the windings but in this case the connection 
is different because the inhibit/enable inputs are 
used for the short circuit protection. The PWM 
choppers act on the channel inputs through the 
four clamp diodes D9, D10, D1 1 and D12. This is a 
simple trick which allows us to use the channel 
inputs both for the step sequencing and the 
choppers. 

Comparators 3 and 4 realize the short circuit pro- 
tection function. Again looking at phase one, com- 
parator 3 operates as a flip flop. Its output is con- 
nected to the bridge enable inputs (pins 1 and 1 1) 
and is normally high, enabling the drivers. If the 
output current (sensed by RS1) reaches double 
the nominal value the comparator CP3 switches, 
inhibiting the two bridges. 

The comparator remains in this state until the V ss 



supply (5V! is interrupted. The outputs of com- 
parators 3 and 4 are ORed together so that a short 
circuit on one phase disables both bridges. 

For this circuit V A should be less than 300 mV 
(V A is the voltage on the + input of CP1). From 
the value chosen for V A and the desired phase 
current the sense resistor RS1 (and RS2) is chosen. 
The current ripple should be at least 30 mA to 
avoid spurious triggering of CP1 and CP2. 

The component values indicated are for a motor 
with a resistance of 37 n/phase, inductance of 
80 mH/phase and a current of 280 mA/phase. 
V ref is 243 mV giving V A = 274 mV when the out- 
put is high and 243 mV when the output is low. 
Since RS1 = 1 n the current is the winding reaches 
274 mA peak and has a ripple of roughly 30 mA. 
The switching frequency depends on the hysteresis 
of the comparators and the motor characteristics. 
For this example the frequency is about 15 kHz. 

Stepper motor drive circuits can be simplified using 
the L297 stepper motor controller which contains 
a translator to generate the phase sequences plus a 
dual PWM chopper to regulate the phase currents. 

The L297 connects directly to the L293E or 
L298N as shown in figure 12. This example drives 
a bipolar stepper motor with winding currents up 
to 2.5A. For lower currents an L293E is used and 
more powerful motors can be driven by two 
L298N's with paralleled bridges, giving up to 3.5A. 



In this configuration the motor is controlled peak winding current in the motor. The choppers 

through the L297. A ste p cloc k moves the motor in the L297 can operate on the phase lines or the 

one increment, the CW/ CCW i nput controls the inhibit lines, depending on the state of the logic 

direction and the HALF/FULL input selects half input called CONTROL. 

step or normal operation. The input V ref is con- For a more detailed description of the L297 see 

nected to a suitable voltage reference and sets the "Introducing the L297 Stepper Motor Controller". 

Fig. 1 1 - With a quad comparator both current regulation and short circuit protection can be obtained. 



V'1 O- 



xY!*£ 



v 2 



IC 2 C1 



— Ov 4 




-Ov 3 



89 



Fig. 12 - An L297 stepper motor controller and a L298N driver together from a complete micropro- 
cessor-to-stepper motor interface. This circuit drives bipolar stepper motors with winding 
currents up to 2 A. 



Q5V 



Q36V 




"51"S2 = " = " 

Dl toD8 = 2A FAST DIODES 



90 



SWITCH-MODE DRIVERS FOR SOLENOID DRIVING 

This design guide describes the operation and applications of the L294 and L295 switch- 
mode solenoid drivers. Integrating control circuitry and power stage on the same chip, these 
devices replace complex discrete circuits, bringing space and cost savings. 



Many applications, particularly in computer per- 
ipherals, require a high power, fast solenoid driver 
circuit. In the past these circuits have been realised 
with discrete components because the high powers 
required precluded the use of monolithic tech- 
nology. 

SGS has overcome this problem with a new high 
power bipolar technology that uses an innovative 
implanted isolation technique. This technology is 
used to fabricate two switchmode solenoid driver 
chips, the L294 and L295, which both incorporate 
high power output stages and control circuitry. 
Both circuits are designed for efficient switchmode 



operation and are mounted in SGS' Multiwatt® 
plastic package. 

THE L294 SOLENOID DRIVER 

The L294 is designed for solenoid driving applica- 
tions where both very high speed and high current 
are essential; needle and hammer driving in printer 
mechanisms, for example. It delivers 4A with 
supply voltages up to 46V, handling effective 
powers up to 180W. 

Shown in figure 1 , the L294 is controlled by a TTL 
- level logic input and the peak load current is 



Fig. 7 - Internal block diagram of the L294 switchmode solenoid driver. 




91 



programmed by a reference voltage applied to the 
pin labelled V|. 

Internal switchmode control circuitry regulates the 
solenoid current by turning the output stage on 
and off repeatedly to keep the load current bet- 
ween the programmed peak value, l p , and a lower 
limit of 0.9 l p . 

Other features of the L294 include thermal shut- 
down, output short circuit protection, overdriving 
protection and a latched diagnostic output. This 
output indicates fault conditions such as a short 
circuit solenoid. 



CIRCUIT OPERATION 

In most applications the L294 is used with a fixed 
reference voltage (V,) and the solenoi d is con- 
trolled by negative -going pu lses on the ENABLE 
input. When the ENABLE input is active (low 
level), the output stage is enabled and the load 
current rises as shown in figure 2. 

The load current is sensed by an external resistor 
(R s ) in the emitter of the sink stage. Through the 
op amp and transconductance amplifier (OTA), 
the sensed voltage charges an external RC network 
(R1C1 (which determines the switching character- 
istics of the device. 

The voltage across this RC network is compared 
with the voltage V,, which fixes the output peak 
current. When the current has reached the pro- 
grammed peak value this comparator switches, 
turning off the output source stage and closing a 
switch which reduces the voltage on the non-in- 
verting input to 0.9 Vj. The load current now 
recirculates in D1. The voltage on pin 8 falls with a 
time constant determined by R1C1 or the load 
characteristics, whichever is the longest. In other 



word. R1C1 sets the minimum recirculation time 
constant. 

When the voltage across R1C1 has fallen to the 0.9 
Vj threshold the comparator switches on, turning 
the output stage back on and restoring the V, com- 
parison threshold. 

The output source stage is switched in this way, 
regulating the load current, until the ENABLE 
input goes high again. At this point the output 
stage is disabled — both source and sink — and the 
load current recirculates through D1 and D2 to 
ensure a fast decay. By varying the voltage V, the 
peak load current can be programmed to any 
value in the range 0.6A to 4A. This feature can be 
exploited to implement two-level current control 
if the fixed reference is replaced by a switched 
reference as shown in figure 3. 



Fig. 2 - Output current waveforms of the L294. 
The output current in regulated by switch- 
ing between a peak value, In, and a lower 
limit of 0.9 l n . 



OUTPUT 
CURRENT 



. *- 

t 
♦ 

i »■ 

La U J t 



Fig. 3 - Two level current control can be implemented by switching Vj between two values. 




92 



Fig. 4 - On-time limiter waveforms. After a period 
defined by C2 the output is disabled 
regardless of the state of ENABLE, pro- 
tecting against overdriving. 




PROTECTION 

To protect the load and the L294 from overdriving 
an on-time limiter inhibits the output stage in- 

Fig. 5 - Standard solenoid driving application of 
the L294. Pin 7 must be connected to a 
suitable reference voltage to set the peak 
current. .„„ , u 

330 A t— - 



o.imfTc c5|;oouf 




D1 
D2 



c -- R1 n -k 1 h Ri 

" nF "T" k"U "TT.7 Uo.2n 

3A Fast Diode 1 
1 A Fast Diode 



S - 53 11 

trr < 200ns 



dependently of the ENABLE input if the duration 
of the input pulse exceeds a period set by the ex- 
ternal capacitor C2 (figu re 4). This circuit is reset 
by taking the ENABLE input high. The on-time 
limiter can be disabled by grounding pin 3. 

Protection against overheating is incorporated in 
the form of a thermal shutdown circuit which 
disables the output stage when the junction tem- 
perature exceeds 150°C. The circuit restarts when 
the temperature has fallen about 20°C. 

The L294 is also protected against short circuits to 
ground, to supply and across the load. Triggered 
when the source stage current exceed 5A or the 
sink stage current exceed 1V/R S , the short circuit 
protection block inhibits the output stage and sets 
a flip flop which is supplied by a separate supply 
voltage V ss . This flip flop is connected to the 
diagnostic output and signals that all is not well — 
a shorted solenoid, for example. The diagnostic 
flip flop is reset by removing the supply V s . 
A LED can be connected to the diagnostic output 
as shown in figure 5. If the diagnostic function is 
not required the V ss supply can be omitted. The 
short circuit protection, however, still functions, 
even without V„. 



USING THE L294 

The basic application circuit for the L294 is shown 
in figure 5; a suggested layout is given in figure 6. 
The circuit is complete except for the source of V,. 
In most cases this will be provided by a simple 
resistive divider dimensioned to set the desired 
peak current. With a 0.2 S7 sense resistor as shown, 
the L294 has a transconductance of 1A/V for V, 
above 600 mV. The device will not work with V, 
less than 450 mV and operation is not guaranteed 
for V, between 450 mV and 600 mV. 

The on-time limiter delay — set by C2 — is ap- 
proximately 1 20 000 x C2. Pin 3 must be grounded 
if the on-time limiter isn't used. 

Switching frequency depends partly on the timing 
network R1C1 and partly on the load charac- 
teristics. 



Fig. 6 - Suggested printed circuit board layout for the application circuit of figure 5. 




6 6 6 

Vj EN GND LOAD 



93 



R1C1 determines the minimum value of tj (see 
figure 2), which is given by x 1 > 0.1 x R1C1. CI 
must be in the range 2.7 — 10 nF to ensure stab- 
ility of the amplifier OTA. R1 must be at least 
10 kn to give sufficient gain for OTA. The stan- 
dard application circuit of figure 5 has a switching 
frequency of about 10 kHz. 

The recirculation diodes should be fast types and 
rated at 3A (D1) and 1A (D2). If the full 4A capa- 
bility of the L294 is not used these can be reduced. 

A high initial peak and low holding current can be 
obtained with the circuit shown in figure 7a. This 
example supplies a current peak for about 10 ms. 

The peak current, Ioex* ' see fi9 ur e 7a) is found 
from: 

V z R2 1 

' n,rv 5~~ ' ~r7~ ' R1 +H2 



'OEX~ 



V z is the zener voltage. The zener and R5 can be 
omitted if a regulated 5V supply is available for 
point A. 



The holding current, 



, is found from: 



(R2//R4) 



1 



hold 



R1 + (R2 // R4) 



The duration of the peak is determined by R3C1 
and is increased by raising R3 or C1 . 

Typical component values are listed in the table 
below: 





"OEX=4A 


l 0EX = 2.5A 




l HOLD= 1A 


'HOLD =0 - 5A 


R1 


10 kn 


io kn 


R2 


47 kn 


27 kn 


R3 


150 kn 


150 kn 


R4 


2.7 kn 


1 .5 kn 


R5 


0.2 n dw) 


0.27 n (0.5W) 


D1 


3A 


1.5A 


D2 


0.5A 


0.5A 


C1 


0.2 mF 


0.2 mF 



Fig. 7a - Application circuit for two level 
current control. This circuit gen- 
erates a high peak current for a 
period determined by R3C1 then 
a lower holding current. 




Fig. 7b - Output current waveform ob- 
tained with the circuit of fig. 7a. 




1 V^n 



m 



94 



Figura 8 — Pin functions of the L294. 



10 
11 



FUNCTION 



Solenoid supply voltage V s (12-46V). 

Output, source stage. 

On-time limiter time constant. A capaci- 
tor to ground sets delay period ( 1 20 000 x 
C2 seconds). On-time limiter is disabled 
by grounding this pin. 

Supply input (5V) for diagnostic flip 
flop. 

Diagnostic output, open collector. Signals 
intervention of latched short circuit 
protection. Reset by removing pin 1 
supply. 

Ground. 

Vj reference input. Peak output current 
is proportional to Vj. Transconduc- 
tance is 1A/V for R s = 0.2 P. and 
V, > 600 mV. 

Timing. A parallel RC network from this 
pin to ground sets the minimum recir- 
culation time constant. 
The capacitor must be 2.7-10 nF to 
ensure stability. 
The resistor must be greater than 10 kn. 



ENABLE. TTL-compatible logic input 
that controls the solenoid current. The 
solenoid is driven when this input is at a 
low level. The on-time limiter overrides 
enable. 

Connection for load current sense 
resistor. 



Output, sink stage. 



THE L295 DUAL SWITCHMODE DRIVER 

The L295 is a dual switchmode solenoid driver 
which handles up to 2.5A per channel at voltages 
up to 46V — a total effective power handling of 
220W. Compared to the L294 it offers a more 
economical solution when 2.5A is sufficient 
because there are two drivers per chip. Like the 
L294 it features switchmode regulation of the 
output current and thermal shutdown. Addition- 
ally it has a separate logic supply input so that 
the logic can be run at a lower voltage, reducing 
dissipation. 

Intended for inductive load driving, the L295 is 
particularly suitable for solenoids and stepper 
motors. One L295 drives two solenoids and two 



L295s can drive the four phases at a unipolar 
stepper motor or the two phases of a bipolar 
stepper motor in bridge configuration. 

Each channel of the L295 is controlled by a 
TTL-level digital input and the peak load current 
is programmed, independently for each channel, 
by a voltage reference input. A chip enable input 
is also provided to disable both channels together. 



INSIDE THE L295 

Internally the L295 (figure 9) bears little re- 
semblance to the L294. Looking at channel one, 
when the V| N1 input goes high the output tran- 
sistors _Q1 and Q2 are switched on (the enable 
input EN is assumed to be active, i.e. low). 
The current in the load then rises exponentially, 
as shown in figure 10, until the voltage across the 
external sense resistor R S i reaches the current 
program reference voltage V re f2. 

The comparator COMP1 switches and sets the 
flip flop FF1 which turns off the source transis- 
tor Q1 . The load current now recirculates through 
D2-Q2-R S1 and decays. 

What happens next is determined by the oscilla- 
tor components R and C on pin 9. If these com- 
ponents are present the flip flop is reset by the 
next clock pulse before the current decays very 
far. The output stage is therefore turned on 
again and the load current rises. 

When it reaches the peak value COMP1 switches 
again, setting the flip flop and disabling the out- 
put stage. This process is repeated, regulating the 
load current until V inl goes low. The output 
stage is then disabled and the current falls off 
rapidly, recirculating through D1 and D2 
(figure 10). 

If the oscillator components are omitted and pin 
9 grounded the current simply decays slowly 
until V in:1 goes low. The output stage is then 
disabled and the load current recirculates through 
D1 and D2. This case is illustrated by the wave- 
forms of figure 11. Note that in this case the 
peak current level is controlled. 

Unlike the L294, the switching frequency of the 
current regulation loop is determined by the 
oscillator components R and C (the L294 is also 
affected by the load). Typically, the switching 
frequency will be 10-30 kHz. Another difference 
between the two devices is that the L294 gives a 
constant ripple, the L295 does not. 



TWO LEVEL CONTROL 

Since the peak load current is programmed by 
the reference voltage (for each channel), two 
level current control can be obtained by switch- 
ing between two reference voltages. A high V ref 
is selected initially to give a high initial current 
peak. Then, after a suitable interval, V ref is re- 
duced to give the lower holding current (figure 
12). Two level current control is very useful for 
solenoids which require a high initial current 
peak for fast actuation. 



95 



Fig. 9 - Interna/ block diagram of the L295 dual switchmode driver. 



Ada 



^H 



THERMAL 
SHUTDOWN 



VOLTAGE 
REGULATOR 



> 



-I 
DRIVER 



LOGIC 
CIRCUITS 



> 



Q H 
FF2 




OSCILLATOR 




rd-^-L 



K°< 



R Q 
FF1 
S 


— -*■ 


LOGIC 
CIRCUITS 


~~| 










> 


Li 

DRIVER 





-K a2 




Ov re12 



"X 



01 A 



2j k 



Oen Ov, 



nl s SB 59 



Fig. 10 - Waveforms illustrating normal operation Fig. 1 1 - When the oscillator components are 
of the L295. omitted and pin 9 grounded the L295 

delivers a simple current peak to the 
load. 




ON 
OFF 






















ON 
OFF 




































s - se 62 




96 



Fig. 12 ■ 



Two level current control is obtained by 
switching V re f between two values. 



Figure 13 - Pin functions of the L295. 




L295 APPLICATION HINTS 

The basic application circuit of the L295 is shown 
in figure 14. A suitable layout is given in figure 15. 

Suitable values for the oscillator components, R 
and C, can be found from the nomogram, figure 
16. The value for the reference voltages depends on 
the desired peak current and is equal to l p R s ; it 
must be in the range 0.2V to 2V. 
If the V ref inputs are left open circuit the L295 
assumes an internal default value of 2.5V giving a 
peak current of 2.5/R s amperes. 

The L295 can also be used to drive unipolar step- 
per motors. For a four phase motor two devices 
are used, connected as shown in figure 17. This 
circuit provides switchmode regulation of the load 
current with a chopper rate of about 25 kHz. The 
enable inputs (EN, connected together) enable/ 
disable the whole circuit and the channel inputs 
v inl ■ ■ ■ v in4 are driven by a suitable translator 
circuit. Phases 1 and 2 must not be energised to- 
gether because they share the same sense resistor. 
The same applies to channels 3 and 4. However, 
'two phase on' drive is still possible for bifilar 
motors where phases one and two represent one 
winding and 3 & 4 the other, and also for variable 
reluctance motors with phase 1 adjacent to phase 
3 etc, 

Two L295s could also be used to drive a bipolar 
stepper motor in systems where a translator 
already exists. 



9 
10 
11 

12 



13 

14 
15 



FUNCTION 



Solenoid supply voltage, V s (12-46V). 

Channel one output, source stage. 

Channel one output, sink stage. 

Rsi- Sense resistor connection, channel 
one. 

V refl . A voltage on this pin sets peak 
current of channel one. If this pin is left 
open or connected to V ss a default V ref 
of 2.5V is assumed. An externally 
applied V ref must be in the range 0.2 
to 2V. 

V inl . Logic input for channel one. 
Driver is active when V inl is high and 
EN low. 

EN. Chip enable (active low). When high 
both channels are disabled. 

Ground. 

Oscillator timing network. This pin is 
grounded to produce a single peak. 

V 5S . Logic supply voltage, internally 
regulated. (4.75 - 10V). 

V jn2 . Logic input for channel two. 
Driver is active when V jn2 is high and 
EN low. 

V ref2 . Voltage input, controls peak cur- 
rent of channel two. If left open or con- 
nected V 5 an internal 2.5V reference 
is assumed. 

An externally applied V ref must be in 
the range 0.2 to 2V. 

Rs2- Sense resistor connection, channel 
two. 

Channel two output, sink stage. 

Channel two output, source stage. 



97 



Fig. 14- Typical application circuit of the L295. R1 LI and R2L2 are solenoids. 

ay,F <? <? 



jHfcr 



li Di 




iiol 



3 12 11 7 6 5 <i 




v ret1 T ' 5 "- 




R3| C3 



lO.luF I22QUF 



D2, D4 = 2A High speed diodes 



}* 



r < 200ns 



D 1 , D3 = 1 A H igh speed diodes 
Fig. 15- Suggested printed circuit board layout for the circuit of figure 14. 



\ L295 \ 

\i: ' n n 

irH~ UUUUUUUiJ^ ft 
SI R S2[ 



+ 
C 2 



c 



2 U u 



ICi 



02 



D1 



fU 



u 



U 



R 3 D 4 



3 

-- — CD-, 



O 



6 



o 



o 



o 



i v "6 OUT 'H < ! > v r.t'i L v ^6 v -»6 v " 6 

GND V s 0UT 1L EN 0UT 2H 0UT 2L GND 



Fig. 16 - Nomogram for the selection of values for 
the oscillator components, RC. 




98 



Fig. 17 - Two L295s, connected as shown, can be used to drive a four phase unipolar stepper motor. 




D6X 

JPHASE2 PHASE4r 




2 :1ilf^ 



D1 : D3 ,D5, D7 :1AFAST DIODES D2 , 34,DS, D8 : 2 A FAST DIODES 



99 



SPEED CONTROL OF DC MOTORS 
WITH THE L292 SWITCH-MODE DRIVER 

Power dissipation in DC motor drive systems can be reduced considerably with an L292 
switchmode driver. This application guide describes two speed control systems based on this 
device; one voltage controlled and one controlled by a 6-bit binary word. Both examples 
are designed for 60W motors equipped with tacho dynamos. 



The L292 is a monolithic power IC which func- 
tions effectively as a power transconductance am- 
plifier, It delivers a load current proportional to an 
input voltage, handling up to 2A at 18-36V with a 
bridge output stage. Completely self-contained, it 
incorporates internal switchmode circuitry and all 
the active components to form a current feedback 
loop. 

The L292 is designed primarily for use with an 
L290 and L291 in DC motor servopositioning 
applications. However, the L292 can be useful in a 
wide range of applications as the two examples 
here show. The first is a simple tachometer feed- 
back circuit, the speed of which is controlled by a 
DC voltage; direction is controlled by the polarity 
of this voltage. The second circuit is controlled 
digitally and includes an L291 D/A converter. 



SYSTEM WITH DC CONTROL 

In this system the control quantity is a dc voltage 
variable between 



+ v iM and - V iM 

Since the quantity under control is the speed of 
the motor, it is required that it varies linearly in 
function of the control voltage. 
A simplified circuit diagram of the system is shown 
in fig. 1. 

The current l 1 , proportional to the set voltage V,, 
and the current l 2 , proportional to the speed of 
the motor, are fed to the sum point of the error 
amplifier. Assuming that the motor does not drain 
current, the system is in a steady-state condition 
whenever lj = -l 2 ; as a matter of fact, in this case 
the output from the error emplifier V is OV. 
During transients, the voltage V Q will assume a 
value V = - R3 (lj + l 2 ) and consequently, since 
the L292 integrated circuit operates as a trans- 
conductance (G m ), a mean current l„= C-.... ■ \/„ 



will flow in the motor determining an acceleration 
proportional to it. 

Fig. 1 - Simplified circuit diagram of DC control 
system 

R2 




Calculation of R1, R2, R3 

Let us call: 

V iM the maximum control voltage value 

n M the maximum speed allowed for the motor 

Kg voltage constant of the dynamo 

By imposing that the balance condition be met in 
correspondance to the maximum rotation speed 
the following equation is obtained: 

i _ i V iM K g 

S 1 - - l 2 ■ 



n 



M 



R1 



R2 



Since R2 is the impedance which the tachometer 
dynamo is loaded on to and its value is recom- 
mended by the manufacturer, it is possible from 
the previous relationship to determine the value 
of FS1. 

Resistor R3 determines the system gain. It's best to 
keep the gain as high as possible (and consequently 
R3 as high as possible) to obtain a high response 
speed of the system, even for small variations in 
the control voltage. On the other hand, an ex- 
cessive gain would cause excessive overshoot 
around the balance conditions at the end of tran- 
sients. Consequently, a trade-off must be made 



101 



ing the final gain. The value for R3 should be 
theoretically determined by studying the transfer 
function, by knowing the electrical and mechanical 
constants of the motor as well as the load applied 
to it. 

A complete diagram of the circuit actually realized 
is shown in fig. 2, while fig. 3, shows the charac- 
teristic n = f (Vj) obtained. 

Resistor R2 drawn in the simplified circuit diagram 
has been split here in two parts and, in addition, a 
capacitor has been interposed to ground to filter 
the signal coming from the tachometer dynamo. 

The curve n. 1 in fig. 3 refers to the operation of 
the motor in no-load condition, with a current 
drain of 200 mA; the curve n. 2 refers to a motor 
loaded so as to drain a current of 1A. By disre- 
garding the discontinuity around the origin, it can 
be noted that the characteristics are linear over the 
whole control voltage range. 

By analyzing the curves around the origin, it can be 
noted that the motor stands still as long as the 
input signal does not exceed a certain threshold 



level, which is as much higher as the current 
drained by the motor is higher. 

Let us call G m the transconductance of L292, and 
I the starting current of the motor; the voltage 
which must be available at the input of L292 in 
order that the motor starts turning is: 

I . ■.,_ ^ _ „-,„ mA 



V 



with G m = 220 



V 



(typical value) 



V; 



V n 



The corresponding control voltage will be: 

R1 = _l , _R1_ 

R3 G m ' R3 

and it is as much lower as the gain of the error 
amplifier is higher. 

The presence of a control voltage interval in which 
the motor stands still, can be useful when it is 
required that, for a certain position of potentio- 
meter P1 (see fig. 2), the motor speed be zero. 
An other method to hold the motor still is to use 
the inhibits of L292, for instance by grounding 
pin 13. 



Fig. 2 - Complete circuit diagram 




T (^ 510 fl 5'Qi l 



I K g ,l.l5mV,turns;mm 



D1 -r D4 



f V F «1, 
] trr < 20' 



2V @ I = 2A 
200 ns 




It can be noted from fig. 3 that, by keeping the 
control voltage V, constant, the speed varies ac- 
cording to the motor current drain. 
Let us call Al the current variation; the voltage 
variation required at the input of L292 is 



AV„- 



A I 



Fig. 3 



Output characteristics of the circuit in 
fig. 2 



since the control voltage is constant, to generate 
this A V it is necessary that the rotation speed 
be varied by a quantity A n such as to have: 

R3 _ , „ _ A I 



A n 



A n : 



R2 



AV n = 



R2 



R3 




6 e io Vj(v) 



102 



In this case too, the variation A n is as much lower 
as the error amplifier gain is higher. With the circuit 
shown in fig. 2 A n is approximately 30turns/min. 
with A I = 800 mA, A n = 0.037 turns/mA.min 
approx. 

It is possible to adopt a circuit which prevents the 



variation in the number of turns in function of 
motor current. The problem is to "sense" the cur- 
rent flowing through the motor and to send a 
current proportional to it to the sum point of the 
error amplifier. The complete circuit which in- 
cludes, beside the voltage feed-back loop, also a 
current feed-back loop, is illustrated in fig. 4. 



Fig. 4 - Complete circuit with current feedback 



5 L292 




T.2K/1 ! 3.3 Kjl 






lii 



(£..(£ 



! i ; 510 A 5TC.fl 



C2j D,J 



D1 + D4 



Vp < 1,2V @ I =2A 
trr < 200 ns 



In the integrated circuit L292, a current propor- 
tional to the mean current drained by the motor 
flows between pin 5 and pin 7. 
An operational amplifier amplifies the voltage drop 
provoked by this current across a 510 n resistor 
and sends a current to the sum point which is 
consequently proportional to the mean current in 
the motor, the value of which can be made vary by 
acting on potentiometer P2. By properly adjusting 
P2, a condition can be achieved in which the speed 
does not change when the current drained by the 
motor varies. 



Fig. 5 - Output characteristic of the 
fig- 4 



circuit in 



The discontinuity around the origin, which was 
present in the previous circuit (fig. 2), is practically 
negligible in the circuit shown in fig. 4. 



The characteristic n = f (V,) relevant to the circuit 
of fig. 4 is shown in fig. 5, and this characteristic 
does not substantially change over the whole range 
of currents allowed by the L292 (up to 2A). 
In the circuit described above if the motor stall 
condition is requested, it is preferable to act on the 
inhibits of the integrated circuit L292, for instance 
by grounding pin 13, instead of adjusting potentio- 
meter P1 : as a matter of fact, the exact position of 
this potentiometer is difficult to obtain, since the 
characteristic crosses the axis Vj in one only point 
(this means that n is only for a very narrow 
interval of V,). 



SYSTEM WITH DIGITAL CONTROL 

In this system the speed information is given to the 
circuit by a binary code made up of 5 information 
bits plus one sign bit, which determines whether 
the movement shall be clockwise or counter- 
clockwise. For the circuit implementation, the 
integrated circuits L291 (which includes a D/A 
converter and two operational amplifiers) and 

L292 are used. , . . . . 

« simpiineo circuit diagram is shown in tig. b. 



103 



Fig. 6 - Simplified circuit diagram (digital control) dition (no current drained by the motor), it must 

be: 




b s o- 



The current value \ 1 depends on the value of l ref 
and on the value of inputs bj through b 5 , where its 
sign depends on the b s input. 

The maximum value for l 1; which is obtained 
whenever inputs b 1 through b5 are low, is: 

, 31 V ref 31 

~ 'ref 



1 max 



16 



R1 



16 



In order to have the system in a steady state con- 



ll= -'2 

By imposing the balance condition at the maxi- 
mum speed, one obtains: l^ max = - lj max 



V re 



R1 



31 
16 



R2 



where 



K„ = dynamo's voltage constant 

n M = maximum speed preset for the motor. 

The current l re f, and consequently the ratio V re f/ 
R1, must lie within a certain range imposed by 
the D/A converter actually used. 
In our case, this range is 0.3 to 1 mA. The values of 
R1 and R2 can be determined from the previous 
relationship. The same considerations made in the 
description of the DC control system apply for the 
selection of R3. 

A complete diagram of the circuit implemented is 
indicated in fig. 7, while the input versus output 
characteristics is shown in fig. 8. 



Fig. 7 - Complete circuit diagram 




D1 + D4 



In the graph of fig. 8 the rotation speed of the 
motor is represented on ordinates, while the 
decimal speed code, corresponding to the binary 
code applied to inputs b 1 through b 5 , is rep- 
resented on abscissae. 

The abscissa 1 corresponds to the minimum speed 
code, i.e. input bj low and remaining inputs high, 
since the least significant input is b^ and the 
active status of inputs is low. The abscissa 31 corre- 



bj through b 5 low. The negative abscissae have 
been obtained by changing the status of the b s 
input. The graph in fig. 8 should have been made 
up of a number of dots; these dots have been 
joined together with an ininterrupted line for 
convenience. This graph has the same features as 
the graph in fig. 3, i.e. the curve features a discon- 
tinuity around the origin, and it lowers as long as 
the motor current drain increases. In this case 
f "n the circuit in fig. 7 can be modified in order to 



104 



Fig. 8 - Output characteristic of the circuit in Fig. 9 - Translator circuit 
fig. 7 

(rpm)| 









1200 


/ 










800 


/ 










400 


/ 


Speed code 


-32 


- lu 


-16 


-8 / 


8 16 


iu n 



prevent that the speed vary in function of the 
motor load, by adding a current loop in the control 
circuit, by using the remaining operational ampli- 
fier available in the integrated circuit L291 . 
Since this amplifier has only the inverting input 
available, while the non-inverting input is ground- 
ed, a circuit arrangement as schematically shown in 
fig. 9 has been adopted in order to have an output 
signal referred to ground, given an input signal re- 
ferred to a reference voltage (in L292) of approxi- 
mately 8V. 




Resistors R A and R B must be high-precision 
resistors in order to have output with no l m 
current present. In the practical implementation, 
resistors with an accuracy of 5% are used and the 
ends of a potentiometer are interposed between 
resistors R B and the output to the sum point of 
the error amplifier is made through the cursor. The 
gain of this current loop is proportional to the 
ratio R3/R B . A complete circuit diagram is shown 
in fig. 10. 

Since, for reasons of gain, resistor R B must be 
27 kn and, if connected to pin 7 of L292, should 
have subtracted too much current by thus affecting 
the correct operation of L292, it has been connec- 
ted to pin 11, having the same potential as pin 7. 
Consequently, the resistance value between pin 11 
and ground has been modified, in order to main- 
tain the switching frequency of L292 unchanged. 
In order to have a correct adjustment of potentio- 
meter P1, it is enough to set the O speed code {b 1 
through b 5 high) and turn the cursor until the 
motor stops. 

The input versus output characteristic obtained 
with the circuit of fig. 10 is indicated in fig. 11. 



Fig. 10 - Complete circuit with current feedback 




>^±>^t4 I— 1 22 i n ,, 
mil 2-mnX fJU-||J 7nF 



D2 : D<. 



D1 4- D4 



V F < 1,2V @ I = 2A 
trr < 200 ns 



105 



Fig. 11 



Output 

fig- 10 



characteristic of the circuit in 



(rprrw 
2000 : 




The no-load characteristics, relevant to the motor 
used for the previous tests, are shown in fig. 1 2. The 
times t a and t f are not equal to each other, which 
circumstance is basically due to the frictions 
which, during the acceleration phase, oppose in- 
crease of speed, while during the deceleration 
phase they contribute to make the speed decrease. 
As a matter of fact, from the movement equation: 



J + D + T f = K-, 



where: 

J = 
D = 
Tf = 
K t = 

= 
- 



System moment of inertia 
Coefficient of viscous friction 
Braking couple 
Motor constant 
Angular speed 
Angular acceleration 



and by disregarding the term D0, one obtains: 



where from it can be seen that | I is greater if l^, 
is negative. 



Fig. 12 - Pulse response 



RESPONSE TO INPUT STEP 

Measurements have been taken on the circuits 
described in the previous paragraphs, in order to 
analyze how the motor speed varies when a step 
variation is imposed to the input. 

For the system DC control, the control voltage has 
been changed from to the maximum value V iM 
and down to again. For the digital system the 
speed code has been changed from (bl through 
bs high) to the maximum value (b t through b 5 
low) and down to again. When the control quan- 
tity changes from to the maximum value, the 
output voltage of the error amplifier (Vp, fig. 1 
and fig. 6) assumes its maximum value, since the 
feed-back signal coming from the tachometer 
dynamo initially 0. In these conditions, L292 
supplies the motor with the maximum current 
(2A) and maintains it until the motor speed is 
sufficiently close to the maximum value. 

Since the motor is powered from a constant cur- 
rent, it moves with a constant acceleration and 
consequently its speed grows linearly from up 
to the maximum value over the time interval tg. 
The time needed for the motor to reach the maxi- 
mum speed also depends, besides the current, on 
the electrical and mechanical characteristics of the 
motor and on the moment of inertia of the load 
applied to the motor. When the control quantity 
changes from the maximum value to 0, the out- 
put of the error amplifier V assumes the maxi- 
mum value, but with an opposite sign with respect 
to the previous case, and the current flowing in 
the motor is also reversed and tends to brake it, 
by making the speed linearly decrease from the 
maximum value down to over the time period t f . 



v i • 
































D 20 


AO 


60 


80 


t(m 



n + 




lm * 






















1 



Error 
Amp. 



106 



A DESIGNER'S GUIDE TO THE 

L290/L291/L292 DC MOTOR SPEED/POSITION 

CONTROL SYSTEM 

The L290, L291 and L292 together form a complete microprocessor-controlled DC motor 
servopositioning system that is both fast and accurate. This design guide presents a descrip- 
tion of the system, detailed function descriptions of each device and application information. 



The L290, L291 and L292 are primarily intended 
for use with a DC motor and optical encoder in the 
configuration shown schematically in figure 1. This 
system is controlled by a microprocessor, or micro- 
computer, which determines the optimum speed 
profile for each movement and passes appropriate 
commands to the L291, which contains the sys- 
tem's D/A converter and error amplifiers. The 



L291 generates a voltage control signal to drive the 
L292 switchmode driver which powers the motor. 
An optical encoder on the motor shaft provides 
signals which are processed by the L290 tacho- 
meter converter to produce tacho voltage feedback 
and position feedback signals for the L291 plus 
distance/direction feedback signals for the control 
micro. 



Fig. 1 - The L290, L291 and L292 form a complete DC motor servopositioning system that cc 
directly to microcomputer chips. 



DIRECTION 



SPEED DEMAND 
WORO (5 BITS) ""- 




VELOCITY/ POSITION 
MODE SELECT 



MOTOR CURRENT 
'CONTROL VOLTAGE 



L291 

DIGITAL-ANALOG 

CONVERTER PLUS 

ERROR AND 

POSITION 

AMPLIFIER 



ABSOLUTE 
POSITION 
SIGNAL FOR 
INITIALIZATION 



\ 



L292 

SWITCHMODE 

MOTOR 

DRIVER 



-POSITION FEEDBACK 
-TACHO VELOCITY FEEDBACK 
-DAC REFERENCE VOLTAGE 



L290 

TACHOMETER 

CONVERTER 

8. REFERENCE 

GENERATOR 



DISTANCE/DIRECTION 
FEEDBACK TO 
MICROPROCESSOR 




107 



The system operates in two modes to achieve high 
speed and accuracy: closed loop speed control and 
closed loop position control. The combination of 
these two modes allows the system to travel 
rapidly towards the target position then stop pre- 
cisely without ringing. 

Initially the system operates in speed control mode. 
A movement begins when the microcomputer 
applies a speed demand word to the L291, typi- 
cally calling for maximum speed. At this instant 
the motor speed is zero so there is no tacho feed- 
back and the system operates effectively in open 
loop mode (see figure 2). In this condition a high 
current peak — up to 2A — accelerates the motor 
rapidly to ensure a fast start. 



As the motor accelerates the tacho voltage rises 
and the system operates in closed loop speed mode, 
moving rapidly forwards the target position. The 
microcomputer, which is monitoring the optical 
encoder signals (squared by the L290), reduces the 
speed demand word gradually when the target 
position is close. Each time the speed demand 
word is reduced the motor is braked by the speed 
control loop. 

Finally, when the speed code is zero and the target 
position extremely close, the micro commands the 
system to switch to position mode. The motor 
then stops rapidly at the desired position and is 
held in an electronic detent. 



Fig. 2 - The system operates in two modes to achieve high speed and accurary. Tachometer feedback 
regulates the speed during a run and brakes the motor towards the end. Position feedback allows 
a precise final positioning. 



MOTOR ACCELERATES 
RAPIDLY IN INITIAL 
OPEN LOOP CONDITIONS 



VELOCITY FEEDBACK 
REGULATES SPEED 
DURING RUN 



MOTOR 
SPEED 



/ 



MOTOR BRAKED 
PROGRESSIVELY BY 
REDUCING SPEED 
MAND WORD 




FINAL , PRECISE 
POSITIONING 
PERFORMEO IN 
POSITION MOOE 



<t> 



CURRENT PEAK 
ENSURES FAST 
STARTUP 



<v 



MOTOR BRAKED AS 
LOOP RESPONDS TO 
REDUCTIONS IN SPEED 
DEMAND WORD 



OPTICAL ENCODER 

The optical encoder used in this system is shown 
schematically in figure 3. It consists of a rotating 
slotted disk and a fixed partial disk, also slotted. 

Light sources and sensors are mounted so that the 
encoder generates two quasi-sinusoidal signals with 
a phase difference of + 90°. These signals are refer- 
red to as FTA and FTB. The frequency of these 
signals indicates the speed of rotation and the 
relative phase difference indicates the direction of 
rotation. An example of this type is the Sensor 
Technology STRE 1601, which has 200 tracks. 
Similar types are available from a number of manu- 
factures including Sharp and Eleprint. 

This encoder generates a third signal, FTF, which 
consists of one pulse per rotation. FTF is used to 
find the absolute position at initialization. 



Fig. 3 - The system operates with an optical 
encoder of the type shown schematically 
here. It generates two signals 90° out of 
phase plus a one pulse-per-rotation signal. 



ONE PULSE 
PER ROTATION 
OUTPUT 



PHOTOTRANSISTORS 



HOLE TO GENERATE 
ONE PULSE PER 
ROTATION SIGNAL 




OUTPUTS WITH 
±90' PHASE 
DIFFERENCE 



OVERLAPPING 

SLOTS 

GENERATE 

QUASI - SINEWAVE 

SIGNALS 



108 



THE L290 TACHOMETER CONVERTER 

The L290 tachometer converter processes the three 
optical encoder signals FTA, FTB, FTF to generate 
a tachometer voltage, a position signal and feed- 
back signals for the microprocessor. It also gene- 
rates a reference voltage for the system's D/A 
converter. 

Analytically, the tacho generation function can be 
expressed as: 



TACHO = 
dV AB 



dt 



FTA 

IFTAi 



dV 



AA 



dt 



FTB 
IFTBI 



In the L290 (block diagram, figure 4) this function 
is implemented by amplifying FTA and FTB in A1 
and A2 to produce V AA and V AB . V AA and 
V AB are differentiated by external RC networks to 
give the signals V MA and V MB which are phase 



Fig. 4 - The L290 processes the encoder signals, generating a tacho voltage and position signal for the 
L291 plus feedback signals for the microprocessor. Additionally, it generates a refence voltage 
for the L291's D/A converter. 




RC NETWORKS 
DIFFERENTIATE 
ENCODER 
SIGNALS 



shifted and proportional in amplitude to the speed 
of rotation. V MA and V MB are passed to multi- 
pliers, the second inputs of which are the sign of 
the other signal before differentiation. 

The sign (- or -) is provided by the 

comparators CS1 and CS2. Finally, the multiplier 
outputs are summed by A3 to give the tacho signal. 
Figure 5 shows the waveforms for this process. 

This seemingly complex approach has three im- 
portant advantages. First, since the peaks and nulls 
of CSA and CSB tend to cancel out, the ripple is 
very small. Secondly, the ripple frequency is the 
fourth harmonic of the fundamental so it can be 
filtered easily without limiting the bandwidth of 
the speed loop. Finally, it is possible to acquire 
tacho information much more rapidly, giving a 
good response time and transient response. 

Feedback signals for the microprocessor, STA, STB 
and STF, are generated by squaring FTA, FTB and 
FTF. STA and STB are used by the micro to keep 
track of position and STF is used at initialization 
to find the absolute position. 

Position feedback for the L291 is obtained simply 
from the output of A1 . 



Fig. 5 ■ 



These waveforms illustrate the generation 
of the tacho voltage in the L290. Note 
that the ripple is fourth harmonic. The 
amplitude of TACHO is proportional to 
the speed of rotation. 



ANTICLOCKWISE 
DIRECTION 




109 



The L290 also generates a reference voltage for the 
L291's D/A converter. This reference is derived 
from V AA and V AB with the function: 



V 



ref : 



I V 



AA 



I + I V 



AB 



Since the tacho voltage is also derived from V AA 
and V AB it follows that the system is self compen- 
sating and can tolerate variations in input levels, 
temperature changes and component ageing with 
no deterioration of performance. 



THE L291 D/A CONVERTER AND 
AMPLIFIERS 

The L291 , shown in figure 6, links the system to 



the micro and contains the system's main error 
amplifier plus a position amplifier which allows in- 
dependent adjustment of the characteristics of the 
position loop. 

It contains a five bit D/A converter with switchable 
polarity that takes its reference from the L290. 
The polarity, which controls the motor direction, 
is controlled by the micro using the SIGN input. 

The main error amplifier sums the D/A converter 
output and the tacho signal to produce the motor 
drive signal ERRV. The position amplifier is pro- 
vided to allow independent adjustment of the posi- 
tion loop gain characteristics and is switched in/out 
of circuit to select the mode. The final position 
mode is actually 'speed plus position' but since the 
tacho voltage is almost zero when position mode is 
selected the effect of the speed loop is negligible. 



Fig. 6- The L291 links the system to the microprocessor. It contains the system DA converter, main 
error amplifier and position amplifier. 



D/AREFERENCE TACHO VOLTAGE 
FROM L290 FROM L290 



POSITION FEEOBACH 
FROM L290 



FILTERS 
REFERENCE 



REMOVES 

FOURTH HARMONIC 

RIPPLE 




VELOC 


TY 


LOOP 




GAIN 

J 




cor 


TROL 


( - VOL 


T AGF. 


" TO 


L292 



POSITION 
MODE SELECT 
( STROBE ) 



THE L292 SWITCHMODE MOTOR 
DRIVER 

The L292 can be considered as a power transcon- 
ductance amplifier — it delivers a motor current 
proportional to the control voltage (ERRV) from 
the L291 . It drives the motor efficiently in switch- 
mode and incorporates an internal current feed- 
back loop to ensure that the motor current is 
always proportional to the input control signal. 



The input control signal (see block diagram, figure 
7) is first shifted to produce a unipolar signal (the 
L292 has a single supply) and passed to the error 
amplifier where it is summed with the current feed- 
back signal. The resulting error signal is used to 
modulate the switching pulses that drive the out- 
put stage. 

External sense resistors monitor the load current, 
feeding back motor current information to the 
error amplifier via the current sensing amplifier. 



110 



Fig. 7 - The L292 switchmode driver receives a control voltage from the L291 and delivers a switchmode 
regulated current to the motor. 



CURRENT FEEDBACK * * s c c cr 

FROM MOTOR Q StNSE 

v 510Q 510 Q 470uF RESISTORS 

--CZ>--! ♦ * \ *— , 



CURRENT 

CONTROL , 6 

VOLTAGE ^*- v l9^- 

FROM L 29 1 ! ,:K a 




The L292 incorporates its own voltage reference 
and all the functions required for closed loop cur- 
rent control of the motor. Further, it features two 
enable inputs, one of which is useful to implement 
a power on inhibit function. 

The L292's output stage is a bridge configuration 
capable of handling up to 2A at 36V. A full bridge 
stage was chosen because it allows a supply voltage 
to the motor effectively twice the voltage allowed 
if a half bridge is used. A single supply was chosen 
to avoid problems associated with pump-back 
energy. 



In a double supply configuration, such as the 
example in figure 8a, current flows for most of the 
time through D1 and Ql . A certain amount of 
power is thus taken from one supply and pumped 
back into the other. Capacitor C1 is charged and 
its voltage can rise excessively, risking damage to 
the associated electronics. 

By contrast, in a single supply configuration like 
figure 8b the single supply capacitor participates in 
both the conduction and recirculation phases. The 
average current is such that power is always taken 
from the supply and the problem of an uncontrol- 
led increase in capacitor voltage does not arise. 



Fig. 8 - A simple push pull output (a) needs a split supply and the device can be damaged by the voltage 
built up on CI. The L292 has a bridge output to avoid these problems. Only one supply is needed 
and the voltage across the single capacitor never rises excessively. Moreover, the motor can be 
supplied with a voltage up to twice the voltage allowed with a half bridge. 





^— 0* v ' 



111 



A problem associated with the system used in the 
L292 is the danger of simultaneous conduction in 
both legs of the output bridge which could destroy 
the device. To overcome this problem the com- 
parator which drives the final stage consists of two 
separate comparators (figure 9). Both receive the 
same V t , the triangular wave from the oscillator, 
signal but on opposite inputs. 

The other two inputs are driven by V T |_|, the error 
amplifier output, shifted by plus or minus R T I'. 
This voltage shift, when compared with V t , results 
in a delay in switching from one comparator to the 
other. 

Fig. 9 - The L292's final comparator actually 
consists of two comparators. This confi- 
guration introduces a delay to prevent 
simultaneous conduction of two legs. 




SOFTWARE AND INTERFACING TO THE 
MICRO 

In a typical system the L290/1/2 system is con- 
nected to the control microcomputer through ten 
I/O lines: seven outputs and three inputs. 

The outputs are all connected to the L291 D/A 
converter and consist of the five bit speed demand 
word, SIGN (which sets the direction) and the 
speed/position mode select line. Position feedback 
for the micro comes from the L290 tacho con- 
verter and consists of the signals STA, STB (the 
squared encoder outputs) plus the one-pulse-per 
rotation signal, STF (figure 11). 



Fig. 11 - In a typical system the L290/L291 /L292 
combination is linked to the micro 
through seven output lines, two inputs 
and an interrupt input. 



NTERRUPT 

NPUT 



TWO 
INPUTS 



SEVEN 
OUTPUT 
LINES 




FROM 
L290 



SCI SC5 
■--*-; SPEED DEMAND 
' WORD 



--»- SIGN 

-^ POSITION MODE 



TO 
L291 



Consequently there will always be a delay between 
switching off one leg of the bridge and switching 
on the other. The delay t is a function of the in- 
tegrated resistor R t (1 .5 kli) and an external capa- 
citor C17 connected to pin 10 which also fixes the 
oscillator frequency. The delay is given by: 

t = Rt C17 

In multiple L292 configurations (in a typewriter, 
for example, there may be two systems) it is de- 
sirable to synchronise the switching frequencies to 
avoid intermodulation. This can be done using the 
configuration shown in figure 10. 

Fig. 10 - Ground plane switching noise and mo- 
dulation phenomena are avoided in multi 
- L292 systems by syncronizing the 
chopper rate with this RC network. 




To follow the motor position the micro counts the 
STA pulses to measure the distance travelled and 
compares the phase of STA and STB to sense the 
direction. The most convenient way to do this is to 
connect the STA line to an interrupt input. An in- 
terrupt service routine will then sample STB and 
increment or decrement the position count de- 
pending on the relative phase difference: +90° if 
STB is high: -90° if STB is low. 

It could be argued that the micro doesn't need to 
sense the direction of the rotation because it con- 
trols the direction. In practice, however, it is better 
to sense the direction to allow for the possibility 
that the motor may be moved by externally 
applied forces. 

For each movement the micro calculates the dis- 
tance to be travelled and determines the correct 
direction. It then sets the L291 to velocity feed- 
back mode, sets the director appropriately and sets 
the speed demand word for maximum speed (pos- 
sibly less if the move is very short) . 

By means of the STA interrupt service routine it 
follows the changing position, reducing the speed 
demand word to brake the motor when the target 
position is very close. Finally, the micro orders the 
L291 to switch to position loop control for the 
final precise positioning. 



1 12 



Fig. 12 - Complete application circuit of the system. 







C.1 U F 0.1. u f 



+ :> 




41"'" 




. . c 


1S;-|/.70*JF 


• 4k ,„ f 


R is ^ p 


9 


510 n r jio n 


r- 




■is-Hi-;;„ F 







IN oj- OU' 



<1 - - 



<&:■- 



<* > - 



r^p 



COMP.'IN CE2 CE' 



V lb 



D1 -f D4 1A Fast Diodes 



V F < 1.2V @ I = 2A 
trr < 200 ns 



Fig. 13 - P.C. board and component layout 11 : 1 scale) 



SCI 

5C2 

SC3 

SO, 

SC5 

SIGN 

STROBE 

STF 

STB 

STA 



■© 
o 

•6 

■e 



GND 

FTF 
FTA 

FTB 

-12 V 
GND 

+12 V 





R9 

p m n 




i 




^j- 1 


c_ 


C 8 J 




( : ? ) 










1- 







_R_ 1 3 ]ri R18 

01 



r;> 







W -C 



D 5 ' 

3 C2 



CT3C.1 c_ 



R3r 



■ 
• 

o 

i fN, 

■ 

^ 1 




! C6 

Ri o 

Ri _j _j_ 


-Pi 

:s 




C4 




C cr ^ 


1 








( c-o ' 



'J J 





L29; 



mm 



s o: 

C16 



o: ci2 

00 



R15R17 
l l 



ft 



-I 



0- 
©- 



GND 
+ 1 2 V 



113 



Fig. 14 



Component 


Recommended 
value 


Purpose 


Larger than 
recommended value 


Smaller than 
recommended value 


R1, R2, R3 


1 kJ2 


To filter the noise on the 
encoder signals 


Offset voltacje increase 
(Vaa. v ab! 




R4, R5 


820 n 


Differentiator network 


Tacho offset and tacho 
signal increase 


Tacho offset increase 
Tacho signal decrease 


R6, R7 


4,7kS2 


To set the D/A input current 


D/A input current decrease 


D/A input current increase 


R8 


4.7kO 


To set the motor speed 


Motor speed increase 


Motor speed decrease 


R9 


5kn 


To adjust the motor speed 


Danger of oscillation 
R9 < Ft 13/ 10 




R11 


22kn 


To set the position loop 
gain 


— Position loop gain decrease 


— Position loop gain increase 

— Danger of oscillation of the 
motor shaft 


R12 


lookn 


To set the position loop 
gain 


— Position loop gain decrease 


- Position loop gain increase 

— Danger of oscillation of the 
motor shaft 


R13 


120kfi 


To set the speed loop gain 


— Speed loop gain increase 


— Speed loop gain decrease 


R14 


i5kn 


To set the position loop 
gain 


— Position loop gain increase 

— Danger of oscillation of the 
motor 


■■- Position loop gain decrease 


R15, R16 


510S7 


To filter the feedback current 


Danger of output saturation 
of the current sensing aplifier 
R15 + R16 < 3.3kii 




R17 


22kn 


To set the gain of the err. 
amplifier 


Increase of the gain at high 
frequencies 


Danger of oscillations 
R17 > 5.6ka 


R18, R19 


0,2 il 


To set the transconducTance 
value of the L292 


Transconductance decrease 
(R18, R15). I m < 0.44V 


Transconductance increase 


R20 


15kfJ 


To set the oscillator 
frequency 


Oscillator frequency 
decrease 


Oscillator frequency 
increase. R20 > 8.2kft 


R21 


33 a 


Compensation network 




Increase of the peak current 
in the output transistors 
during the commutations 


CI, C2, C3 


100 pF 


To filter the noise on the 
encoder signals 


Bandwidth reduction of the 
iow pass f ilter 


Bandwidth increment of the 
low pass filter 


C4, C6 


15 nF 


Differentiator network 


Tacho signal increase 


Tacho signal decrease 


C5 


2.2mF 


By-pass capacitor 


Larger set-up time after 
power on 


Reduced by-pass effect at 
low frequencies 


C7 


0.1 n F 


Low-pass filter for the D/A 
input current 




Increase of the current ripple 
at low speed 


C8 


0.22 ii 


— Low pass filter for the 
tacho signal 

— To determine the dominant 
pole of the speed loop 


Bandwidth reduction of the 
speed loop 


Low filtering at low speed, 
causing noise on the motor 


C10, C11 


0.1 »iF 


Supply by-pass capacitor 




Danger of oscillations 


C12 


47 nF 


To filter the feedback 
current 


— Lower value of the 
damping factor 

— Danger of oscillations 


— Higher value of dumping 
factor 


C13 


47 nF 


To set the gain of the error 
amplifier C13 - R17 - 
L M /R M 






C15 


0.1 ixf 


Supply by-pass capacitor 




Danger of oscillations j 


C16 


470uF 


Supply by-pass capacitor 




Ripple increment on the I 
supply voltage 


C17 


15 nF 


To set the oscillator frequency 
and the dead time of the 
output transistors 


~ Oscillation frequency 

reduction 
— Dead time increment 


— Oscillation frequency 
incremen. 

- Dead time reduction 


C18 


1 nF 


Compensation network 




Danger of oscillations 


01, D2, 
D3, D4 


1A 
Fast diodes 


Recirculation diodes 


._. 


. 



114 



When the system is powered up the mechanical 
subsystem may be in any position so the first step 
is to initialize it. In applications where the optical 
encoder never rotates more than one revolution — 
the daisy wheel of a typewriter, for example — 
this is simply done by rotating the motor slowly 
until the STF signal (one-pulse-per-rotation) is 
detected. 

Where the optical encoder rotates more than once 
the 'one-pulse-per-rotation' signal is not sufficient. 
An example of this is the carriage positioning servo 
of a computer printer. In this case the simplest 
solution is to fit a microswitch on one of the 
endstops. First the motor is run backwards slowly 
until the carriage hits the endstop.Then it moves 
forward until the STF signal is detected. The 
beauty of this solution is that the endstop micro- 
switch does not need to be positioned accurately. 



ADDING DISCRETE TRANSISTORS FOR 
HIGHER POWER 

In the basic application, the L292 driver delivers 
2A to the motor at 36V. This is fairly impressive for 
an integrated circuit but not enough for some ap- 
plications — robots, machine tools etc. The basic 
system can be expanded to accomodate these 
applications by adding external power transistors 
to the L292. This is preferable to simply adding a 
discrete driver stage in place of the L292 because 
the L292's current control loop is very useful. 

Figure 15 shows how four transistors are added to 
increase the current to 4, 6 or 8A, depending on 
the choice of transistor. When coupled to the L290 
and L291 this configuration appears to the system 
as an L292. 



The average motor current, l m , 
Vi 0.044 



is found from: 



APPLICATION CIRCUITS 

The complete circuit is shown in figure 12; a suit- 
able layout for evaluation is given in figure 13. 
Component values indicated are for a typical 
system using a Sensoi Technology STRE1601 
encoder and a motor with a winding resistance of 
5H and an inductance of 5 mH (this motor is 
described fully in figure 17). How to calculate 
values for other motors is explained further on. 

Figure14 explains what each component does and 
what happens if it is varied. Maximum and mini- 
mum values are also indicated where appropriate. 



where V : is the input voltage and R x is the value 
of the sense resistors R7 and R8. 

Suitable transistors for this configuration are in- 
dicated below: 



1 (A) 


V,IV] 


R x (mS2) 


Q1, Q2 


03, 04 


D1 - D4 


4 


9.1 


100 


BD708 


BD707 


2A Fast diodes 


6 


9.1 


65 


BD908 


BD907 


3A Fast diodes 


8 


9 1 


50 


BDW52A 


BDW51 A 


4A Fast diodes 



Fig. 15 - For higher power external transistors are added to the L292. This circuit delivers up to 4A, if 
2 BDW51A and 2 BDW52A are used it can deliver 8 A. 




~~[e 12 



? 



OON >3.2 V 
OFF < 2 V 



115 



The circuit shown in figure 16 is suitable for motor 
currents up to 50A at voltages to 150V. Two 
supplies are used; 24V for the L292 and LS141 
and 150V for the external transistors and motor. 
This circuit too behaves just like an L292, except 
for the higher power, and connects to the L290 
and L291 as usual. 

The motor current is given by: 

V in x 120x 10'* R 

' m — 



and 



FU 



390 n < R < 860 n 



where 



R q = R, 



12 x 10~ 3 f2 



This gives a range of transconductance values 
(l m /V in ) from 3.0 A/V (R = 390n) to 8.6 A/V 
(R = 860n). 

In this circuit the L292 drives two transformers 
whose secondaries drive the power transistors. The 
coil ratio of the transformers is 1 :20. To limit the 
duty cycle at which the transformers operate from 
15% to 85%, two zener diodes are inserted be- 
tween pin 7 and pin 9 of the L292. The LS141 op 
amp supplies current feedback from the transistor 
bridge to the L292. 



Fig. 16 - For higher voltages and currents-up to 150V at 50A - this circuit can be used. It connects to 
the L290 and L291, behaving just like and L292. 







-a^q"^ T 

U 2 . 





f^ r^ 



< >i 



| 162 Jl I |39_,1 39n! 82 iT I 



«Hg)2,3SW67 i^ty 



116 



DESIGN CONSIDERATIONS 

The application circuit of figure 12 will have to be 
adapted in most cases to suit the desired perform- 
ance, motor characteristics, mechanical system 
characteristics and encoder characteristics. Essen- 
tially this adaptation consists of choosing appro- 
priate values for the ten or so components that 
determine the characteristics of the L290 L291 
and L292. 

The calculations include: 

Calculation of maximum speed and acceleration; 
useful both for defining the control algorithm 
and setting the maximum speed. 

Calculation of R8 and R9 to set maximum 
speed. 

Laplace analysis of system to set C8 R11 R12 
R13andR14. 

Laplace analysis of L292 loop to set the sensing 
resistors and C12, C13, R15, R16, R17. 

Calculation of values for C4 and C6 to set max 
level of tacho signal. 

Calculation of values for R6 and R7 to set D/A 
reference current. 

Calculation of R20 to set desired switching 
frequency. 



MAXIMUM ACCELERATION 

For a permanent magnet DC motor the acceler- 
ation torque is related to the motor current by the 
expression: 



where: 



lm 
K T 
T a 
Tf 



is the motor current 

is the motor torque constant 

is the acceleration torque 

is the total system friction torque 



The acceleration torque is related to angular ac- 
celeration and system inertia by: 



T a - (J + J + J.) a 



where: 
J r 

Jr 



is the moment of inertia of the motor 
is the moment of inertia of the encoder 
is the moment of inertia of the load 
is the angular acceleration. 



In a system of this type the friction torque T f is 
normally very small and can be neglected. There- 
fore, combing these two expressions we can find 
the angular acceleration from: 



+ Jop + Ji 



lr 



It follows that for a given motor type and control 
loop the acceleration can only be increased by in- 
creasing the motor current, l m . 

The characteristics of a typical motor are given in 
figure 1 7. From this table we can see that: 

K T = 4.3 N cm/A (6.07 oz. in/A) 
J m =65g-cm 2 (0.92 x 1 CT 3 oz.in.s 2 ) 

We also know that the maximum current supplied 
by the L292 is 2A and that the moment of inertia 
of the STRE1601 optical encoder, J oe , is 0.3x10"" 
oz.in.s 3 . 

The moment of inertia of the load J L , is unknown 
but assume, for example, that J oe + J L s 2 J m . 
Therefore the maximum angular acceleration is: 



6.07 x 2 



2x0.92x1 0" 3 



6597.8 rad/s 



Fig. 17 - The characteristics of a typical DC 
motor. 



Motor - Parameter 


Value 


U BB (V S ) 


18V 


C. emf. K E 


4.5 mV/min -1 


N (without load) 


3800 rpm 


l om (without load) 


190 mA 


Tf (friction torque) 


0.7 N cm 


K T (motor constant) 


4.3 N cm/A 


Amature moment of inertia 


65 g. cm. 2 


R|yi of the motor 


5.4 n 


L M of the motor 


5.5 mH 



MAXIMUM SPEED 

The maximum speed can be found from: 



+ Kp fl + R r 



V S min= 2 V CEsat + Re 
where: 

E = K e fl is the internally generated voltage 
(EMF) 

K e is the motor voltage constant 

fl is the rotation speed of the motor. 

For example, if v s min = 20V 

2 v CEsat + R s l m = 5V (from L292 datasheet) 

R m l m = 10.8V (R m = 5.4a) 



we obtain: 

K eS2 (E)= 4.2V 



117 



and 



n = 



4.2V 



4.5 mV/min ' 

= 97.74 rad/s 



933.3 rpm 



The STRE1601 encoder has 200 tracks so this 
speed corresponds to: 

200 



V = n 



60 



3111.1 tracks/s. 



The time taken to reach maximum speed from a 
standing start can be found from 



97.74 rad/s 
6597.8 rad/s 2 



14.8 ms 



We can also express the acceleration in terms of 
tracks/s 2 : 

V = 3111.1 tracks/s 2 _ 

At 14.8 ms 

= 21 0209.5 tracks/s 2 

Therefore the number of tracks necessary to reach 
the maximum system speed for our example is: 

V 2 

P = = 23 tracks 

2 K 

This information is particularly useful for the 
programmer who writes the control software. 



SETTING THE MAXIMUM SPEED 

The chosen maximum speed is obtained by setting 
the values of R6, R7, R8, R9, C4 and C6 (all 
shown on the application circuit, figure 12). This is 
how it's done: 

The first step is to calculate R6 and R7, which 
define the DAC current reference. From the L291 
datasheet we know that l ref , the DA converter 
current reference, must be in the range 0.3 mA to 
1.2 mA. 

Choosing an l ref of roughly 0.5 mA, and knowing 
that V ref (the L290s reference output) is typically 
5V, it follows that: 

R6 + R7 = '-^— = 10 kn 



ref 



Therefore we can choose R6 = R7 = 4.7 kn (5% 
tolerance). 

Substituting the minimum and maximum values of 
V ref (from the L290 datasheet) and the resistance 
variations we can now check that the variation of 
l ref in the worst cases is acceptable. 



'ref i 



V. 



ref min 



(R6 + R7) max 



= 0.46 mA 



'ref typ ' 



'ref max 



V ref (typ) 
4.7 k + 4.7 k 



V 



ref i 



(R6 + R7) min 



0.53 mA 



= 0.62 mA 



These values are within the 0.3 mA to 1.2 mA 
limits. 

Now that the reference current is defined we can 
calculate values for R8 and R9 which define the 
tacho current at the summing point. 

The full scale output current of pin 12 of the L291 
(the D/A converter output) is: 

l = 1.937 l ref 

which is typically 1 .02 mA. 

The worst case output current is when l ref is at 
a maximum (0.62 mA) and the l out error is maxi- 
mum (+ 2%): 



\r 



0.62 x 1.937 x 1.02 = 1.22 mA 



This less than the 1 .4 mA maximum value for l out 
specified in the L291 datasheet. 

Assuming that the maximum DC voltage at the 
TACHO output of the L290 (pin 4) is 7V (this is 
the tacho voltage generated at the maximum sys- 
tem speed), we can find the sum of R8 and R9; 

R8 + R9 = J^Hi£l_ = _J_ = 6 . 85 kn 



o typ 



1.02 



Therefore we choose R8 = 4.7 kn and a 5 kn 
trimmer for R9. R9 is used to adjust the maximum 
speed. 

We can now calculate the ripple voltage and maxi- 
mum tacho voltage: 

V ripple pp = —~ (\/ 2-1) V tacho Dc = 2.3 V pp 



'tacho max 



2 V t 



7.8 V r 



This value is within the voltage swing of the tacho 
amplifier (± 9V); that means the choice of 
v tacho DC= 7V is correct. 

At this point we know the values of R6, R7, R8 
and R9. The maximum speed can now be set by 
choosing values for C4 and C6 which form the dif- 
ferentiation networks on the L290. These values 
depend on the number of tracks of the optical 
encoder. For the STRE1601 encoder the capacitor 
values can be found from figure 18. These curves 
show how the capacitor values is related to fre- 
quency (encoder rotation speed) for different 
tacho voltages and maximum speed. The example 
values are V tacno Dc = 7V and maximum speed = 
31 1 1 tracks/ sec therefore the value for C4 and C6 
is 15 nF. 

The values of R4 and R5 must be 820n to mini- 
mize the offsets. 



11E 



Fig. 18 - C4 and C6 value versus rotation speed 
for various maximum tacho voltage 
values. 



' 








| 
















- 


















\ \\\ 






































^S- 
















n^ 


5V 6V 


? V BV - 



















1 ? 3 ^56 1(KHz)-FTA 

3CD 600 900 1200 1500 1800 rpm 



LAPLACE ANALYSIS OF THE SYSTEM 

Suitable values for the components R11,R12,R13, 
R1 4 and C8 can be found from a Laplace analysis 
of the system. Figure 19 shows a simplified block 
diagram of the system which will be useful for the 
analysis. 



The analysis is based on the angular speed n and 
on the motor position 0. The motor is represented, 
to a first approximation, by the current l m and by 
the acceleration torque, T a , which drives an inertial 
load J. 

There are two conversion factors, K sp and Kfl. 
They link the mechanical parameters (position and 
speed) with the equivalent feedback signals for the 
two loops. The values of K sp and Kd are deter- 
mined by the encoder characteristics and the gain 
parameters of the integrated circuits. The open- 
loop and closed-loop gains are fixed by four ex- 
ternal resistors: 

" ^ref — fixes the reference current (R6 + R7) 

■ R speed — f ixes tne speed loop gain (R8 + R9) 

■ Rpos ~~ controls the position loop gain) R12) 

■ R err — controls the system loop gain (R13). 

The stability both of the speed loop and of the 
speed-position loop are defined by external com- 
ponents. 

The fundamental characteristics of the speed con- 
trol system can thus be determined by the designer. 

r sp is the time constant that determines the domi- 
nant pole of the speed loop and is determined by 
C8, R8 and R9 

R8 R9 
, = C8 



'sp 



R8+ R9 



Fig. 19 



Vpos 


' 


B re1 


K» 




& 








I - 


I ' 




(*) See L292 datasheet for an accurate analysis of this block. 



List of terms 



T a 
Tf 
J 

n 



Laplace variable 

Motor torque constant 

Acceleration torque 

Total system friction torque 

Total moment of inertia (J : 

Speed 



> + J m +J L ). 



119 



: Angular position 

: Conversion factor that links the 

motor rotation speed and the TACHO 

signal. 
: Conversion factor that links the 

motor position and the V pos signal. 



SETTING THE L292 COMPONENTS 

The sensing resistor and feedback loop component 
values for the L292 can be calculated easily using 
the following formulae. A detailed Laplace analysis 
of this block is given on the L292 datasheet. 

a) Sense resistors. R s = R18 = R19 

l m _ R2 R4 I 

V; R1 R3 R s 

R2 R4 Vj 

R s = L_ 

l m R1 R3 

(These resistors are all inside the L292). 

where: 

l m Is the motor current 

Vj is the input voltage corresponding to l m . 

For example, l m = 2A, V, = 9.1V, resistor values 
as in figure 7 (L292 internal block diagram) 

0.044 



FU 



I 



v, = 0.2 n 



b) R17, R15, R16.C12, C13 

G - 2Vs - 
m °" Rm V R 

V s = L292 supply voltage 
R m = motor resistance 
V R = L292 reference voltage 

and 



R4 C13 



4R15 C12 G mo R c 



J mo ' 's 

R4 = L292 internal resistor (400S7) 

R s = R18 = R19 

A good choice for £ is 1 A/ 2. Substituting this 
value, G mo and the values of R4 and R s : 

■ 2 = J_ = 400 CI 3 

2 4R15C12x0.2 

_ 1000 C13 



Therefore we can find C13 : 

1000 C13 = 47 x 10"' 
=> C13 = 47 nF 



Since 



Rn 



R17 ■■ 



= R17 C13 



C13 R r 



For the example motor L m = 5 mH, R m = 5.4J2 
therefore: 



R17 = 



C13 R n 



= 22 kf2 



From R15 C12 = 47x10"' s, choosing a value of 
R15;510 12, we have: 

C12 = 82 nF 

Also, R16= R15 = 510 12. 



DEAD TIME 

C17 sets the switching delay of the L292 which 
protects against simultaneous conduction. The 
delay is: 

t= R-C17 

and R r is an internal 1.5k resistor. The suggested 
1.5 nF value gives a switching delay of about 
2.25 ,us. This is more than adequate because the 
transistors have a switch off delay of only 0.5 /is. 



SWITCHING FREQUENCY 

The switching frequency is set by C17 and R20: 

f = L 



R15 C12 



= 1 



Also 



0.9 

2rr R15 C12 



Assuming that f T is 3 kHz, another recommended 
value: 

R15 C12 = 47 x 10~ 6 s 



2 R20 C17 

R20 must be at least 8.2 kn and is varied to set the 
frequency: the value of C17 is imposed by dead 
time requirements. Typically the frequency will be 
15-20 kHz. 

It shoud be outside the audio band to reduce noise 
but not to high or efficiency will be impaired. The 
maximum recommended value is 30 kHz. 



CURRENT RIPPLE 

To reduce dissipation in the motor and the peak 
output current the ripple, A l m , should be less than 
1 0% of the maximum current. 

Since A l m = • 



half period of oscillator) 



120 



and 



l m =0.1 I 



0.1 



m max 
V 5 



2f L M min 
5 V s 

' 'm max 



Therefore there is a minimum inductance for the 
motor which may not always be satisfied, if this is 
the case, a series inductor should be added and the 
value is found from: 

- 5V s _, 

L series L M 



If A t1 > A t2 and V s = 20V we obtain: 

n = I — = 80% 

20 

In practice the efficiency will be slightly lower as a 
results of dissipation in the signal processing circuit 
(about 1W at 20V) and the finite switching times 
(about 1W). 

If the power transferred to the motor is 40W, the 
80% efficiency implies 1 0W dissipated in the 
bridge and a total dissipation of 1 2W. This gives an 
actual efficiency of 77%. Since the L292'sMultiwatt 
package can dissipate up to 20W it is possible to 
handle continuous powers in excess of 60W. 



EFFICIENCY AND POWER DISSIPATION 

Neglecting the losses due to switching times and 
the dissipation due to the motor current, the effi- 
ciency of the L292's bridge can be found from: 



A t1 



v c 



t1 



n - 



t1 - A t2 



A t1 



A t2 



V s 
where: 

V ver- 2V(2V BE + R S l m ) 
V 5at s 4V(2V CEsat + 3V BE ) 
A t1 = transistor conduction period 
A t2 = diode conduction period. 



POSITION ACCURACY 

The main feature of the system L290, L291, L292 
is the accurate positioning of the motor. In this 
section we will analyse the influence of the offsets 
of the three ICs on the positioning precision. 

When the system is working in position mode, the 
signal FTA coming from the optical encoder, 
after suitable amplification, is sent to the summing 
point of the error amplifier (L291). If there were 
no offset and no friction, the motor would stop in 
a position corresponding to the zero crossing of the 
signal FTA, and then at the exact position required. 
With a real system the motor stops in a position 
where FTA has such a value to compensate the 
offsets and the friction; as a consequence there is a 
certain imprecision in the positioning, The block 
diagram, fig. 20, shows the parts of the 3 ICs 
involved in the offsets. First we will calculate the 
amount of the offsets at the input of the IC L292 
(point A of fig. 20). 



Fig. 20 



FTA 








L290 


pv 










\ V AA 


v l 


TACHC 




yS 






121 



L290 

The offset of the TACHO signal, V2, is the main 
cause of the imprecision of the positioning. Another 
offset in L290 is V1, the output offset voltage of 
A1 . The contribution at point A is: 



V 



1A 



V1 



R14 
R11 



V2 



R13 
R12 



R13 
R89 



Calling Vm the maximum value of the signal FTA, 
the phase error of the system is: 



If a c is the phase between two consecutive charac- 
ters, (it may be equal 360° or multiple of it) the 
percentage error in the character positioning is: 



e = 



100 



L291 

In this IC there are the following offsets: 

V3 = input offset voltage of the position amplifier 

lj = input bias current of the position amplifier 

l 2 = output offset current of the D/A converter 
plus ER.AMP bias current 

V4 = input offset voltage of the error amplifier. 

Their contribution at point A is: 

R14 . R13 



V 



3A 



= V3 



(1 + 



Vh 



VI 



2A" 



R11 
R14 • 

I; 



) 



R12 



R13 



= V4 (1 + 



R12 

• R13 

R13 
R12 // R89) 



-) 



L292 

Referring to this IC we must consider the input 
offset voltage V5. Moreover, we call V6 the input 
voltage that must be applied to the L292 to keep 
the motor in rotation, i.e. to compensate the 
dynamic friction. V6 is not an offset voltage, but 
has the same effects, and for this reason we have to 
put it together with the offsets. 



In these calculations we have not considered how 
the precision of the signal FTA, coming from the 
optical encoder, influences the positioning error. 
The percentage value of the pitch accuracy must be 
added to e to have the total percentage error in the 
character positioning. Any DC offset of the mean 
value of the signal FTA must be multiplied by Al 
and added to V1 to obtain its effect on the error. 



NUMERICAL EXAMPLE 

In this numerical example we will calculated the 
precision of the positioning in the worst case, i.e. 
with all the offsets at the max value. The values of 
the externa! components are taken from the ap- 
plication circuit, (fig. 12). 

R11=22K R12=100K R13=120K R14=15K 
R89 = R8 + R9= 6K 

From the data sheets of the three ICs we can find: 

V1=55mV V2 = 80 mV V3 = 4.5 mV 

V4= 2mV V5 = 350mV 

lj =0.3mA l 2 = 0.4 M A 

A1 min = 22dB = 12.6 



V; 



Transconductance 
of L292 



V 6A = V6 = 



lg = Motor current necessary 
to compensate the 
dynamic friction 



lr 



Vi 



min = 205 



mA 
V 



V* 



0.4V 



' Mmin 

For l 6 we will consider the value l<, = 50 mA 
15 120 



V 



1A 



55.10" 



22 



V 2A = 80 



10" 



100 
120 



= 45 mV 



= 1.6V 



The total offset voltage referred to point A is given 
by the sum of all the precedent terms: 

V A = V 1A + V 2A + V 3A + VI 1A + VI 2A + V 4A + 

+ v 5A + v 6A . 

The amplitude of the signal FTA necessary to com- 
pensate the offset V A is: 

R12 _ R11 . 1 
R13 ' R14 A1 



V 



FTA 



V, 



122 



4.5 • 10~ 3 (1 + 



,= 0.3- 10 



120 




100 



= 9.1 mV 



= 5.4 mV 



V | 2A =0.4 • 10~ 6 • 120 • 10' =48 mV 
120 



V/LA =2-10" 



(1 + -^^) = 44.9 mV 
5.6 



/ 5 A = 350 mV 



'6A ■ 



V FTA = 2.329 



ft = sirT 



_50_ 
205 



244 mV 




12.6 



= 0.228V 



0.226 
0.4 



s 35 



If we consider an optical encoder with 200 tracks/ 
turn and a daisy wheel with 100 characters, the 
phase between two consecutive characters is 
Ct c = 120", and then the maximum percentage 
error we can have is. 



35 
720 



100 = 4.8% 



From this numerical example we can see that the 
main contribution to the positioning error is given 
by the offset of the TACHO signal (V 2A ), other 
big contributions are given by the input offset 
voltage of L292 (V 5A ) and by the voltage neces- 
sary to compensate the dynamic friction of the 
motor (V 6A ). This last term is only determined by 
the motor and can also have greater values. 

The error we have calculated is the maximum pos- 
sible and it happens when all the offsets have the 
max value with the same sign, i.e. with a prob- 
ability given by the product of the single prob- 
abilities. Considering as an example every offset 
has a probability of 1% to assume the max value, 
the probability the error assumes the max value is: 



P= (10~ 2 ) 7 = 10~ 14 



Fig. 21 



speed 

(rpmi 




I I | : ' | i 


800 


















600 
















Y 


] 














~/y~ 






400 








: 
























' 


200 
































\ 





















FTA 

:khz) 



encoder, we can note the speed of the motor is 
not a linear function of the speed digital code 
applied to L291 . The diagram of fig. 21 shows 
this function and it is evident that the speed in- 
creases more than a linear function, i.e. if the 
speed code doubles, the speed of the motor be- 
comes more than the double. The cause of this non 
linearity is the differentiator network R4 C4 and 
R5 C6 (see fig. 22) that has not an ideal behaviour 
at every frequency. 



Fig. 22 




"MA '"5 1 



1 > V MA = V AA sin f 

<p = tg' 1 oj R5 C6 cj = 2 n f 

2) v ma = V AA sintg~' lo R5 C6 
f = frequency of the signal FTA 

This last relation gives the amplitude of the signal 
V MA ; it is evident there is not a linear function 
between V MA and oj, like V MA = Kcj and the dif- 
ference is greater if the product oj R5 C6 doesn't 
respect the disequation oj R5 C6 <1 . , i.e. at high 
frequencies. 

The phase angle between V MA and V AA should 
be 90° and then <p = 0, in our case \p increases 
with the frequency according to the equation 
if = tg"' u> R5C6, and influences the amplitude of 
the output signal TACHO. In fig. 23 are shown the 
waveforms that contribute to generate the TACHO 
signal. A and B are the signals V AA and V AB in 
phase with the input signals FTA and FTB. C and 



Fig. 23 



12 16 2 4 speed code 




SPEED ACCURACY 

f we consider the complete system with L290- 
L291-L292 driving a DC MOTOR with optical 



- V MA sign V 4B 



5563665553556355^ 



^" --" -« S5t5t5t5tSt5t5t5Cst5t5tSt5CsCS° 



123 



D are the signals V MA and V MB : the continue line 



indicate the ideal case, in fact the phase between 
V MA and V AA is 90°; the dotted line is referred to 
the real case in which the phase is lower than 90". 
By adding the two signals shown in E we obtain 
the TACHO signal, whose expression is: 



Fig. 24 




V TACHO~ V l\ 



sign V,c 



V 



MA 



iign V AB . 



The signals in E are referred to the ideal case, the 
ones in F to the real case. It is possible to demon- 
strate the mean value of the TACHO signal in the 
real case is lower than the one we could have with 
an ideal differentiator network and this explains 
why in fig. 21 the speed of the motor increases 
more than a linear function. The mean value of the 
waveforms F is (fig. 24). 

,. it - ip 2 K1 

3) V m = K1 sin a d a= cos $ 

-v *■ 

Since the waveforms E are half sinewaves, the 
mean value is 

4) V m = 

■n 
We can conclude that two causes contribute to 
give a TACHO signal lower than the theoretical 
one, both due to the differentiator network: 

a) the amplitude of the signal V MA is lower than 
V MA = Koj and we can call 61 the relative per- 
centage error. 

sin tcf ' cj R5 C6 - oj R5 C6 



£1 



co R5 C6 



100 



b) 



62 = (cos^- 1) • 100 



tg" 



oj R5 C6 



The total percentage decrease of the TACHO 
signal is given with a good approximation by 
the sum of 6 1 and 62. 

Example: 



Consider: 

f = 3000 Hz 

3000 , 
200 



n = - 



corresponding to 
60 



ei 



-2.6% with R5 : 
C6 = 



820 12 

15 nF 



62 
63 



-2.6% 

61 + 62 = -5.2% 



From the diagram of fig, 21 we note that at a 
speed of 900 rpm corresponds a theoretical speed 
of 855 rpm with a percentage difference of about 
5.2%. 



SPEED ACCURACY DUE TO THE D/A 
CONVERTER 

To analyse the influence of the DAC precision on 
the speed accuracy we will refer to the following 
(fig. 25). 



the mean value of the signals V MA • sign V AB 
and V MB • sign V AA is lower than the the 
theoretical one because there is a shift in the 
phase of the signals V MA and V MB .The relative 
percentage error only due to the shift of the 
phase is 



900 rpm of the motor if 200 
are the tracks/turn of the 
encoder 



Fig. 25 





■ret , 
t 


"'TACHO 
Q 


SCI — 




Re9 ^TACH0_ 


SC2 — 




5 C 3 - ■ • 
SC4 — 


DAC 




SC5 






SIGN 




—L 




The value of the output current of the DAC l 
depends on l ref and on the digital code defined by 
the inputs SC1 -SC5, while its direction depends on 
the value of the SIGN input, the max theoretical 
value of l , obtained with SC1 -SC5 low, is: 

, _ + 31 , 

'OM "" - ~ j^ — 'ref 

The motor will run at a speed corresponding to the 
following value of the TACHO signal: 

y _ , n„„_ 31 

v TACHO" " 'OM 



R89= ± 



16 



ref 



R89 



This last relation is true if we don't consider the 
motor friction and the offsets. Consider now the 
possible spreads we can have in the motor speec 
due to the DAC. If we call Iomi tne value of the 
max output current l corresponding to the SIGN 
LOW and loM2 tne one corresponding to the 
SIGN HIGH, the percentage error we have in the 
max speed from the positive to the negative 
value is: 



64 



'OM2 



100 



OM 



Note that we have consider the sum of Iomi anc 
Iqm2 because they have opposite signs. This kinc 
of error is principally due to a different gain o 
the DAC between the two conditions of the SIGf\ 
LOW and HIGH. An equal difference of ! OM1 anc 

l OM2' from 'OM (HoMll ~ I'omI = HOM2I ~ I'omI 
doesn't constitute a speed error because this shif 
from the theoretical value can be compensated b\ 
adjusting the resistor R89 that is formed by a fixec 
resistor in series with a potentiometer. 



124 



Vith the guaranteed values on the L291 data sheet 
ve can calculate for e4 the max value: 

21 mA 



€4 = 



1,4 mA 



100=1 .5% 



\nother characteristic of a D/AC is the linearity, 
hat in our case is better than ± 1/2 LSB. This 
'alue is sufficient to guarantee the monotonicity of 
, and then of the speed of the motor, as a func- 
ion of the input digital code. The precision of 
: 1/2 LSB implies a spread of the speed at every 
onfiguration of the input code of ± 1,61% re- 
erred to the maximum speed. The max percentage 
rror we can have is then greater at low level speed 
± 50% at min speed) and has its minimum value at 
he maximum speed (1.61%). 



ACCURACY DUE TO THE ENCODER 

The amplitude of the signals FTA and FTB deter- 
mines the value of the TACHO signal. This ampli- 
tude must be constant on the whole range of the 
frequency, otherwise it is not possible to have a 
linear function between the TACHO signal and the 
frequency. The spread of the amplitudes of the 
two signals FTA and FTB between several encoder 
can be compensated by adjusting the potentio- 
meter R9 (see fig. 12). The phase between the two 
signals should be 90°. If there is a constant dif- 
ference from this value, a constant factor reduc- 
tion of the TACHO signal results that can be com- 
pensated with the potentiometer R9. If the dif- 
ference from 90° is random, also the reduction of 
the TACHO signal is random in the same way, 
and by means of R9 it is possible to compensate 
only the mean value of that reduction. 



125 



DESIGNING WITH THE L296 

MONOLITHIC POWER 

SWITCHING REGULATOR 

A cost-effective replacement for costly hybrids, the SGS L296 Power Switching Regulator 
delivers 4A at an output voltage of 5.1V to 40V and includes many popular supply features. 
This comprehensive application guide explains how the device operates and how it is used. 
Typical application circuits are also presented. 




127 



The SGS L296 is the first monoiithic switching re- 
gulator in plastic package which includes the power 
section. Moreover, the circuit includes all the func- 
tions which make it specially suited for micropro- 
cessor supply. 

Before the introduction of L296, which realizes 
the step down configuration, this function was im- 
plemented with discrete power components driven 
by integrated PWM regulator circuits (giving a max- 
imum output current of 300 to 400 mA) or with 
hybrid circuits. Both of these solutions are charac- 
terized by a low efficiency of the power transistor. 
For this reason it is generally necessary to operate 
at frequencies in the 20kHz to 40 kHz range. Of 
the two alternatives discrete solutions are usually 
less expensive because they do not include as many 
functions as the L296. 

With the new L296 regulator the driving problem 
of the power control stage has been eliminated. Be- 
sides a higher overall efficiency, it is therefore also 
possible to operate directly at frequencies as high 
as 100 kHz. At 200 kHzthe device still operates (fur- 
ther reducing the cost of the L and C external com- 
ponents) when a reduction of a few percent in effi- 
ciency is acceptable. 

The device delivers a maximum current of 4A to 
the load, at an output voltage adjustable from 5.1 
to 40V; the maximum operating input voltage is 
46V. The high voltage and the high current capa- 
bilities of the device aje a result of the special tech- 
nology used and the special care taken in designing 
the power transistor. Essential requirements for a 
good power transistor are high gain and high cur- 
rent levels, low saturation voltage and good second 
breakdown robustness. To achieve high gain at high 
current levels, the power transistor has to be desi- 
gned to maximize the emitter's perimeter/area ratio. 



In the L296 power transistor, realized with a high 
voltage (50V) process, current densities in the ma- 
gnitude order of 10 m A/Mil 2 are achieved. 

In its most complete configuration, in which all the 
available functions are being used, a significant re- 
duction of the external component count is achiev- 
ed compared with discrete componentsolution. 

The L296 is mounted in a MULTIWATT® plastic 
package with 1 5 pins, minimizing the cost per watt 
and allowing a low thermal resistance of 3°C/W be- 
tween junction and package and of 35°C/W between 
junction and ambient. This thermal resistance (in- 
cluding the contact resistance) is comparable to 
that of the more costly metal TO-3 packages. 



THE STEP-DOWN CONFIGURATION 

Fig. 1 shows the simplified block diagram of the 
circuit realizing the step-down configuration. This 
circuit operates as follows: Q1 acts as a switch at 
the frequency f and the ON and OFF times are suit- 
ably controlled by the pulse width modulator cir- 
cuit. When Q1 is saturated, energy is absorbed from 
the input which is transferred to the output through 
L. The emitter voltage of Q1 , Vg, is Vi-Vsat when 
Q is ON and -Vp (with V F the forward voltage 
across the D diode as indicated) when Q1 is OFF. 
During this second phase the current circulates 
again through Land D. Consequently a rectangular- 
shaped voltage appears on the emitter of Q1 and 
this is then filtered by the L-C-D network and con- 
verted into a continuous mean value across the 
capacitor C and therefore across the load. The cur- 
rent through L consists of a continuous component, 
'LOAD* ar, d a triangular-shaped component super- 
imposed on it, Al|_, due to the voltage across L. 



Fig. 1 — The basic step-down switching regulator configuration. 




7 'load 



128 



Fig. 2 — Principal circuit waveforms of the fig. 1 circuit. 



OF! 7 ON OFF ON OFF 
Q-l h-rz 1 : > *- 



•on 'off 



H h 



V CE, 



'a 



X 



M L 



1 '' 

' pea k 



l peak 



1ai l 

1-1- 



-V|-(V sa tFV ) 



■-<VV ) 




a) 



b) 



c) 



d) 



■load e ) 



AQF c 








., 






"'c 


~\ /a 


B V 


**s^^^ 


■^ 


t 



£ A1 C =A1l 



~AQ- f 




C " Bf.C 




h) 
AV ESFf A': E SR 




»o V = V r +v 



o = 'C^ E5R 



129 



Fig. 2 shows the behaviour of the most significant 
waveforms, in different points of the circuit, which 
help to understand better the operation of the 
power section of the switching regulator. For the 
sake of simplicity, the series resistance of the coil 
has been neglected. Fig. 2a shows the behaviour of 
the emitter voltage (which is practically the voltage 
across the recirculation diode), where the power 
saturation and the forward V F drop across the 
diode era taken into account. 

The ON and OFF times are established by the fol- 
lowing expression: 

T ON 
V n = (V, - V s; ' 



which therefore gives: 

A^ 
8fc 



Q 



T, 



ON 



+ T, 



OFF 



Fig. 2b shows the current across the switching tran- 
sistor. The current shape is trapezoidal and the 
operation is in continuous mode. At this stage, the 
phenomena due to the catch diode, that we consider 
as dynamically ideal, are neglected. Fig. 2c shows 
the current circulating in the recirculation diode. 
The sum of the currents circulating in the power 
and in the diode is the current circulating in the 
coil as shown in fig. 2e. In balanced conditions the 
AIl 1 ' current increase occuring during Ton has t0 di L 

be equal to the Al|_ decrease occurring during Tqff- v i = L — — 
The mean value of li_ corresponds to the charge dt 

current. 
The current ripple is given by the following formula: wmch 9' ve s- 



Fig. 2h shows the voltage ripple V ESR due to the 
resistive component of the capacitor. This com- 
ponent is v ESR (t) = i c (t) • ESR. Fig. 2i shows 
the overall ripple V , which is the sum of the two 
previous components. As the frequency increases 
(>20kHz), which is required to reduce both the 
cost and the sizes of L and C, the V ESR component 
becomes dominant. Often it is necessary to use 
capacitors with greater capacitance (or more capa- 
citors connected in parallel to limit the value of 
ESR within the required level. 

We will now examine the stepdown configuration 
in more detail, referring to fig. 1 and taking the be- 
haviour shown in fig. 2 into account. 

Starting from the initial conditions, where Q = ON, 
V C = v o and 'L = 'D = 0. using Kirckoff second 
principle we may write the following expression: 

V, = v L + v c (Vsat is neglected against Vj). 



dt. 



dt 



Al, + = Ai,~ = 



( V; - V s: 



T ON ~ 



d|L_ 
dt 



(v,-v J 



(1) 



(2) 



V n + V F 



Tqff 



The current through the inductance is given by: 



It is a good rule to respect to lo^ifg ~^\\_I2 relation- 
ship, that implies good operation in continuous 
mode. When this is not done, the regulator starts 
operating in discontinuous mode. This operation is 
still safe but variations of the switching frequency 
may occur and the output regulation decreases. 

Fig. 2d shows the behaviour of the voltage across 
coil L. In balanced conditions, the mean value of 
the voltage across the coil is zero. Fig. 2f shows the 
current flowing through the capacitor, which is the 
difference between II and l|_OAD. 

In balanced conditions, the mean current is equal 
to zero, and Al c = Al L . The current l c through the 
capacitor gives rise to the voltage ripple. 
This ripple consists of two components: acapacitive 
component, AV C , and a resistive component,AV ESR , 
due to the ESR equivalent series resistance of the 
capacitor. Fig. 2g shows the capacitive component 
AVc of the voltage ripple, which is the integral of a 
triangular-shaped current as a function of time. 
Moreover, it should be observed that vq (t) is in 
quadrature with \qM and therefore with the voltage 
V ESR . The quantity of charge AQ + supplied to the 
capacitor is given by the area enclosed by the ABC 
triangle in fig. 2f : 



h = 



(Vj-Vq) t 



(3) 



When V|, V , and L are constant, l L varies linearly 
with t. Therefore, it follows that: 



Ai L + = 



(Vi-V )T C 



(4] 



When Q is OFF the current through the coil has 
reached its maximum value, l pea k and because it 
cannot vary instantaneously, the voltage across the 
coil is inverted and the diode D becomes forward 
biased to allow the recirculation of the current 
through the load. 

When Q switches OFF, the following situation is 
present: 



v C (t) = V., i L (t) ■■ 



(t)= I 



peak 



And the equation associated to the following loof 
may be written: 



AQ =■ 



Ai L 



di L 

L — + v c 



(5 



130 



where: 



power absorbed by the system. P, is given by P , 
plus all the other system losses. The expression of 
the efficiency becomes therefore the following : 



dt 



(V F + VJ/L 



(6) V 



It follows therefore that 
V F + V, 



ii (t) 



°_ t 



(7) 



The negative sign may be interpretated with the 
fact that the current is now decreasing. Assuming 
that Vp may be neglected against V , during the 
OFF time the following behaviour occurs: 



Ii 



V„ 



therefore: 




Al L - = -^_T OFF 

L L 




But, because 




Al L + = Ai L - 


if follows that : 


(V, - V ) T ON 


Vo T OFF 



which allows us to calculate V n 



T Or> 



t on + Tqff 



= v ; 



'ON 



(8) 



(9) 



10) 



P o + Psat + P D + P L + Pq + Psw 



(12) 



DC LOSSES 

P sa t : saturation losses of the power transistor Q. 
These losses increase as V: decreases. 



= V, 

T, 



T Oh 



where 



ON 

T 



T 



= V„ t L — 



(13) 



and V sat is the power 



transistor saturation at current l . 

Pq: losses due to the recirculation diode. These 
losses increase as Vj increases, as in this case 
the ON time of the diode is greater. 

p D = V F l Q '" P =V F 'o '1 ~ -) <14) 



V: 



Vi 



where Vp is the forward voltage of the recir- 
culation diode at current l . 

P|_: losses due to the series resistance F>s of the 
coil 



(15) 



P q : losses due to the stand-by current and to the 
power driving current: 



where T is the switching period. 

Expression (10) links the output voltage V to the 
input voltage V, and to the duty cycle. The relation- 
ship between the currents is the following: 



Tr- 



lir 



EFFICIENCY 

The system efficiency is expressed by the following 
formula: 



./„=_2_100 



77% 



where P =V I (with l = l LOAD ) 



Pa = V,- I 



3q 



■ v, r 



3q 



where being: 

Ton Vq 

T Vi 



it follows that : 



Pq - Vi r 3q + v Q i" 3q 



n which : 
!'3q = '3q at 0% duty cycle 



I" 



3q '3q(i00%d.c.) - hq (0%d.i 



SWITCHING LOSSES 

P sw : switching losses of the power transistor: 



Psw = V, l 



tr + t f 
2T 



(16) 



is the output power to the load and P, is the input The switching losses of the recirculation diode are 



131 



neglected (which are anyway negligible) as it is as- 
sumed that diode is used with recovery time much 
smailer than the rise time of the power transistor. 

We can neglect losses in the coil (it is assumed that 
A! \_ is very small compared to l ) and in the out- 
put capacitor, which is assumed to show a low ESR. 



From the behaviour shown in fig. 2 it may be cal- 
culated that the charge current of the output ca- 
pacitor, within a period, is Al L /4, which is supplied 
for a time T/2. It follows therefore that: 



Av r 



Al L T 
4C 2 



All T Ai L 



8C 



8fC 



(19) 



Calculation of the inductance value, L 

Calculating T D n and T OF p through (4) and (9) 
respectively it follows that: 



Tqn = 



Al|_ • L 



Vi-V 

But because: 

Ton + Tqff = T 

it follows that: 

Al L - L Al L - L 



Tqff - 



Al L • L 



and Al^ = Al L : = Al L , 



V ; - V„ 



V„ 



= T 



Calculating L, the previous relation becomes: 



L = (V ' - V o' V o T 



v, Ai L 



(18) 



Fixing the current ripple in the coil required by the 
design (for instance 30%of l Q ), and introducing the 
frequency instead of the period, it follows that: 

_(V| - V qIVq where Lis in Henry and f in Hz 
Vi-0.3-l o -f 



but, remembering expression (4) 
(V| - V, 



Ai, + = • 



T ON . -r Y° T 
and T 0N - — 



therefore equation (19) becomes: 
(V-, - V ) V 



Av, 



IVi f 2 LC 



Finally, calculating C it follows that: 

c <Vi - Vq) Vq 

8 Vj AV C f 2 L 



where: 



L is in Henrys 
C is in Farads 
f is in Hz 



(20) 



Finally, the following expression should be true: 
_ A v Cmax 



ESR n 



Ah 



21) 



It may happen that to satisfy relation (21) a ca- 
pacitance value much greater than the value calcu- 
lated through (20) must be used. 



Calculation of the output capacitor C 

From the output node in fig. 3 it may be seen that 
the current through the output capacitor is given by : 



L (t) 



- U 



Fig. 3 — Equivalent circuit showing recirculation 



when Q, is turned off. 



LOAD 




TRANSIENT RESPONSE 

Sudden variations of the load current give rise to 
overvoltages and undervoltages on the output vol- 
tage. Since i c = C (dv c /dt) (22), where dv c = AV , 
the instantaneous variation of the load current Al 
is supplied during the transient by the output ca- 
pacitor. During the transient, also current through 
the coil tends to change its value. 
Moreover, the following is true: 

= L — (23) where di L = Al . 



dt 



v L = V; 



= V 



Vo 



for a load increase 



for a load decrease 



Calculating dt from (22) and (23) and equalizing, it 
follows that: 



U 'L 

V L 



= C 



dv.. 



132 



Calculating dv c and equalizing it to AV , it follows 
that: ... 2 



Av„ 



LAL 



C(V, -V n ) 



AV„ = 



lAi ' 



(24) for + AI 



(25) for -Al r 



From these two expressions the dependence of over- 
shoots and undershoots on the Land C values may 
be observed. To minimize AV it is therefore neces- 
sary to reduce the inductance value L and to in- 
crease the capacitance value C. Should other auxili- 
ary functions be required in the circuit like reset or 
crowbar protections and very variable loads may be 
present, it is worthwhile to take special care for mi- 
nimizing these overshoots, which could cause 
spurious operation of the crowbar, and the under- 
shoot, which could trigger the reset function. 



DEVICE DESCRIPTION 

Fig. 4 shows the package in which the device is 
mounted and the pin function assignments. 
The internal structure of the device is shown in 
fig. 5. Each block will now be examined. 



Power supply 

The device is provided with an internal stabilized 
power supply that, besides supplying the reference 
voltage of 5.1V for the whole system, also supplied 
the internal analog blocks. 

Special features of the voltage reference are its ac- 
curacy, temperature stability and high line rejection. 
Through zener-zap trimming, the voltage is within 
±2%limits. 



Fig. 4 — Pin assignments of the L296. 



<!>-« 



£ 





CROWBAR DRIVE 

RESET OUTPUT 

RESET DELAY 

RESET INPUT 

OSCILLATOR 

FEEDBACK INPUT 

FREQUENCV COMPENSATION 

GROUND 

SYNC INPUT 

INHIBIT INPUT 

SOFT-START 

CURRENT LIMIT 

SUPPLY VOLTAGE 

OUTPUT 

CROWBAR INPUT 



Tab < 



Fig. 5 — Block diagram of the L296. In addition to the basic regulation loop the device includes functions 
such as reset, crowbar and current limiting. 






- 1 - P 

II 



_^HH' L_l UM,T 



CROWBAR CROWBAR 
INPUT DRIVE 

9 9 



SAWTOOTH 
OSCILLATOR 









S Q 

INHIBIT 

FLIP 

FLOP 

R Q 


1 





THERMAL 
SHUTDOWN 



T 



io ? 




± 



6 

INHIBIT 
INPUT 



5.1V 
REFERENCE 



-ORESET INPUT 
-ORESET OUTPUT 



; RESET DELAY 



133 



OSCILLATOR 

The oscillator block generates the saw-tooth wave- 
form that sets the switching frequency of the 
system. This signal, compared with the output 
voltage of the error amplifier, generates the PWM 
signal to be sent to the power output stage. The 
saw-tooth, whose amplitude is between 1.2V and 
3.2V, is generated by charging rapidly the C osc 
capacitor which then discharges across the R sc 
resistance. As shown in fig. 6, the oscillator is rea- 
lized by a comparator (with grounded compatible 
input) with hysteresis whose thresholds are 1.2V 
and 3.2V respectively. The C osc capacitor and the 
Rose resistance are connected to the non-inverting 
input of the comparator which set the oscillating 
frequency is fixed. When the voltage on pin 11 is 
less than 3.2V, the switch S-\ is closed and the cur- 
rent generator charges the C osc capacitor rapidly; 
in this phase S2 is also closed. As soon as 3.2V is 
reached the comparator output drives S2 open 
(therefore opening S-| , too); the inverting input 
voltage is reduced to about 1.2V and the capacitor 
starts to discharge itself across the R osc resistor 
(the l bias effect is neglected). When the voltage 
reaches 1.2V, S2 and S-| close again and a new cycle 
starts. The generated waveform is shown in fig. 7. 

To achieve a good accuracy of the switching fre- 
quency it is essential to have a charging time of the 
capacitor which is much smaller than the discharg- 
ing time. In this way, the oscillation frequency 
only depends on the external components Cp S c 
and R sc- ^ or thls reason tne capacitor charging 
current (when Si is ON) is typically around 10mA. 
For example, with a 2.2 nF capacitor to switch 
from 1 .2V to 3.2V about 400 ns is required, which 
is negligible compared to the 1 jUs period that oc- 
curs when the operation is performed at 100 kHz. 
The diagrams shown in fig. 8 allow the calculation 
of the R osc value (R1 in fig. 8) with C osc as a par- 
ameter (C3 in fig. 8) when the oscillation frequency 
required for operation has been previously fixed. 



Fig. 6 - Internal schematic of the oscillator 



Fig. 
f = 



7a- 
100 



Oscillator waveform at pin 



KHz <R C 



4.3 KSl, C 



1 1 with 
2.2 nF) 




Fig. 7b - Oscillator 
f = 50 KHz (R osc 



waveform 
= 9. 1 KSl, 



t : 5jus/div 



at pin 11 with 
C osc = 2.2 nF) 




Fig. 8 



5/is/div 



Nomogram for the choice of oscillator 
components. 


































































































































































































si 


J. 


1,5 nF 


















































































































I 
























I II NX 






















C3.2.2nlN^ 






















i 1 








i 












L 




I ; , iS 





Fig. 8 shows two suggested values for the C osc 
capacitance. Excessively low capacitance value may 
give rise to an inaccuracy of the upper threshold 



134 



due to the switching delays of the comparator. This 
inaccuracy in caused by an excessively short rise 
time of the voltage. A capacitance value too high 
gives rise to a charging time which is too long com- 
pared to the discharging time. An additional inac- 
curacy cause would be therefore present for the 
switching frequency, now due to spread of the 
charge current. 

Th? oscillation frequency is given by the following 
formula: 



l osc ^osc 



(26) 



PWM (see fig. 9) 

The PWM signal is generated on the comparator 
output; the triangular-shaped waveform and the 
continuous signal coming from the output of the 
transconductance error amplifier are sent to its 
inputs. The PWM signal is then transferred to the 
driving stage of the output power transistor. 



SOFT START (see fig. 9) 

Soft start is an essential function for correct start- 
up, to prevent stresses and possible breakdown 
from occurring in the power transistor and to ob- 
tain a monotonically increasing output voltage. 
In particular, the L296, as itdoes not have any duty 
cycle limitation and due to the type of current limi- 
tation does not allow the output to be forced to a 



steady state without the aid of the soft-start facility. 
Soft-start operates at the start-up of the system, 
after the inhibit has been activated, after an inter- 
vention of the current limitation and after the inter- 
vention of the thermal protection. 

The soft-start function is realized through a capaci- 
tor connected to pin 5 which is charged at constant 
current (= 100/UA) up to a value of about V R gF- 
During the charging time, through PNP transistor 
Q58, the voltage on pin 9 is forced to increase with 
the same rising speed as on pin 5. Starting from the 
discharged capacitor condition (pin 5 voltage = OV) 
the power transistor is in the OFF condition, as the 
voltage on pin 9 is smaller than the minimum level 
of the ramp voltage. As the capacitor is charged, 
the PWM signal begins to be generated as soon as 
the error amplifier output voltage crosses the ramp; 
the power stage starts to switch with steadily in- 
creasing duty cycle. This behaviour is shown in 
fig. 10. As soon as the steady condition is reached 
the duty cycle sets itself to the right value due to 
the effect of the feedback network while the soft- 
start capacitor completes its charging to a value very- 
close to V REf =. 

The soft-start effect is determined, apart from the 
switch-on time, when the current limitation oper- 
ates, due to either an overload or a short circuit, to 
keep the mean value of the current absorbed by the 
power supply low. 

Moreover from fig. 1 1 it may be observed that 
since the voltage on pin 9 can decrease under the 
minimum ramp level and increase over the maxi- 
mum level no limitations have been provided on 
the duty cycle, which therefore may vary between 
and 100%. 



Fig. 9 — Partial internal schematic showing PWM and soft start blocks. 



\\:\i 




135 



Fig. 10 — Soft start waveforms. When power is applied, or after an inhibit, the L296's output current 
rises slowly under control of the soft start circuit. 



OSCILLATOR 
OUTPUT 



CLAMPED- LRROP. 
AMP OUTPUT 



NOMINAL 
ERROR AMP 

OUTPUT 



OUTPUT 
CURRENT 




S -5835 



Fig. 1 1 — Waveform for calculation of duty cycle and soft start time. 




1 start -up 



CALCULATING THE DUTY CYCLE AND 
SOFT-START TIME 

Assume, for simplicity, that the rising edge of the 
ramp is instantaneous; V r is the output voltage of 
the error amplifier and V c the ramp voltage (see 
fig. 11). The PWM comparator block switches 
when V r = V c ; therefore: 



E e 



Consequently: 



x ~ R osc Cose ln — 



The time obtained from this expression is the Tqff 
time of the power transistor. The duty cycle d is 
given by: 



= 1 



V r 



R, 



V; 



'OSC Cqsc ' n T7~ 



(27) 



Consequently, starting with the capacitor discharg- 
ed, the output of the regulator will be at the nom- 
inal level when the voltage at the terminal of the 
capacitor (which is charged by a constant current) 
has reached V r — 0.5V. 



136 



t start-up 



_ C S5 (V r -0.5V) 



'5so 



where C ss is the soft-start capacitor and l 5s0 is the 
charging current. 

Considering as the soft-start time the time required 
for the soft-start capacitor to charge from (1 2V- 
0.5V) to V r - 0.5V, gives: 



tss = 



Css (Vr- 1.2) 
Isso 



(28) 



substituting V r from (27) gives: 

V r = E e V v i / 

substituting into (28) gives: 

Css 



tss = 



Isso 



E e 



tfH, 



,2) 



SYNCHRONIZATION 

The synchronization function is available on pin 7, 
this function allows the device to be switched at an 
externally generated frequency (leaving pin 11 
open), or to mutually synchronize several devices, 
using one of them as master and the others as 
slave (Fig. 12). 

This allows several devices to be operated at the same 
frequency, avoiding undesirable intermodulation 
phenomena. The number of mutually synchron- 
izable devices is obviously much greater than the 



three devices shown in the figure. It is anyway dif- 
ficult to establish an exact maximum number of 
devices, as it depends on different conditions. 

The first consideration concerns the accuracy which 
must be achieved and maintained on the oscillation 
frequency. Since the bias current on pin 7 is an out- 
put current, the sum of all the bias currents must 
be much smaller than the capacitor discharge cur- 
rent in close proximity to the lower discharge thre- 
shold. Therefore, assuming C osc = 2.2 nF and 
R osc = 4.3 Kn, it follows that: 



= 280mA 



1.2V 
4.3 Kn 

Assuming that a 10% variation may be accepted, 
it follows therefore that the number of synchron- 
izable devices is given by: 



N = 



28 /UA 



This means that if the overall l bias is too high it 
may modify the discharging time of the capacitor. 

The second consideration concerns the layout 
design. 

In the presence of a great number of devices to be 
synchronized, the lenght of the paths may become 
significant and therefore the distributed inductance 
introduced along the paths may begin to modify 
the triangular shaped waveform, particularly the 
rising edge which is very steep. This effect would af- 
fect the devices that are physically located more 
distant from the master device. 

The amplitude of the saw-tooth to be externally 
connected must be within 0.5V and 3.5V, values 
also representing the maximum swing of the error 
amplifier output. 



Fig. 12 - In multiple supplies several L296's can be synchronized as shown here. 




137 



CURRENT LIMITATION 

The current limitation function has been realized 
in a rather innovative way to avoid overload con- 
dition during the short circuit operation. In fact, 
while for all the other devices a constant current 
limitation is implemented by acting on the duty 
cycle (therefore, in short circuit conditions an 
output current is equal to the maximum limitation 
current), the new control approach allows operation 
in short circuit conditions with a mean current 
much smaller than the allowed 4A value. Operation 
of the current limiter will now be described. 
Refer to the block diagram, fig. 13. 

The current which is delivered from the output 
transistor to the load flows through the current sens- 
ing resistor R s . When the voltage drop on R s is 
equal to the offset voltage of the current compara- 
tor, the comparator generates a set pulse for the 
flip-flop, with a delay of about 1 fJsec. The purpose 
of this delay is to avoid triggering of the protection 
circuit on the current peak that occurs dunng the 
recirculation phase. Therefore, the output Q goes 



low and the power stage is immediately switched 
off, while the output Q goes high and acts directly 
on the soft-start capacitor discharging the soft-start 
capacitor at a costant current (about 50 /J.A). 
When the voltage on pin 5 reaches 0.4V the com- 
parator triggers, supplying a reset pulse to the flip- 
flop; from now on, the power stage is enable and 
the soft-start phase starts again. When the limitation 
cause, either overload or short circuit, is still present 
the cycle repeats again. The waveform of the out- 
put current on pin 2 is shown in fig. 14. 

From fig. 14 it may be observed how this current 
limitation technique allows the short circuit oper- 
ation with a very low output current value. 

It is possible to reduce the maximum current value 
by acting on pin 4. On this pin a voltage of about 
3.3V is present; by connecting a resistance a con- 
stant current, given by 3.3/R, is sent to- ground. 
This current reduces the offset voltage of the cur- 
rent comparator, therefore anticipating its triggering 
threshold. 



Fig. 13 - Partial schematic showing the current limiter circuit. 




CURRENT 
LIMITER 



^SS 



138 



Fig. 14a — Current limiter waveforms. 



CURRENT 

LIMITER 

TRIGGERS 



AVERAGE 
SHORT CIRCU 
CURRENT 



-nn nfllli 


^-^iUteffl::: 


*- 



Fig. 14b — Load current in short circuit condit- 
ions (Vj = 40v, L = 300 iiH, f^ 100 KHz) 





■■■in iii 

■■■(■■a 



t : 5ms/div 

Fig. 14c — Current at pin 2 when the output is 
short circuited. 




t: 5ms/div 



RESET 

The reset function is of great importance when the 
device is used to supply microprocessors, logic de- 
vices, and so on. This function differentiates the 
SGS L296 device from all previous devices. The 
block diagram of the function is shown in fig. 15. 
A reset signal is generated when the output voltage 



is within the limits required to supply the micro- 
processor correctly. 

The reset function is realized through the use of 3 
pins: the reset input pin 1 2, the reset delay pin 13 
and the reset output pin 14. When the voltage on 
pin 1 2 is smaller than 5V the comparator output is 
high and the reset capacitor is not charged because 
the transistor Q is satured and the voltage on pin 
14 is at low level, since Q2 is saturated, too. When 
the voltage on pin 12 goes above 5V, the transistor 
Q switches OFF and the capacitor can start to 
charge through a current generator of about 100JUA. 
When the voltage on pin 13 goes above 4,5V the 
output of the related comparator switches low and 
the pin 14 goes high. As the output consists of an 
open collector transistor, a pull-up external resist- 
ance is required. In contrast, when the reset input 
voltage goes below 5V, less a hysteresis voltage of 
about 100 mV, the comparator triggers again and 
instantaneously sets the voltage on pin 14 low, 
therefore forcing to saturation the Q1 transistor, 
that starts the rapid discharge of the capacitor. 
Obviously, the reset delay is again present when 
the voltage on pin 13 is allowed to go under 4.5V. 

To achieve switching operations without uncer- 
tainties the two comparators have been provided 
with an hysteresis of about 100 mV. In every oper- 
ating condition the reset switching is guaranteed 
with a minimum reset input of 4.75V, the value 
required for correct operation of the microproces- 
sor even in the presence of the minimum Vrj=f 
value. 

Normally pin 12 is used connected to pin 10. When 
it is connected to the output, the function may be 
more properly called "reset"; on the other hand, 
when it is connected through resistive divider, to 
the input voltage, the function is called "power 
fail". Fig. 16 and fig. 17 show the two possible 
usages. 

The "power-fail" function is used to predict, with 
a given advance, the drop of the regulator output 
voltage, due to main failures, which is enough to 
save the data being processed into protected mem- 
ory areas. Fig. 18 summarises the reset function 
operation. 



139 



Fig. 15 - Partial schematic showing reset circuit. 



RESET 

INPUT 



,N£ 



L296 



toon I ! 4 5v 



?>^<°' 



C RESET 




Fig. 16 - For power - on reset the reset block is Fig. 17 - To obtain a power fail signal, the reset 
connected as shown here. block is connected like this. 



RESET 
OUT 

9 



RESET 
OUT 













14 






L296 


2 


13 


12 1 






CZJ 



eT 






K 




12 


L296 


2 


13 




10 



i i 



Fig. 18 — Waveform of the reset circuit. 



RESET 
THRESHOLD 



MONITORED 
VOLTAGE 



OUTPUT NOW AN INTERRUPTION 

STABLE, RESET OF SUPPLY CAUSES 

3 GOES HIGH RESET OF MICRO 

lOOmV OF ] I fl T POWER DOWN 

HYSTERESIS j | MICRO IS INHIBITED 

J Irf. Uf- I /IMMEDIATELY 



RESET 
OUTPUT 



J I 



DELAY DELAY 



140 



CROWBAR 

This protection function is realized by a completely 
independent block, using pin 1 as input and pin 1 5 
as output. It is used to prevent dangerous overvolt- 
ages from occurring when the output exceeds 20% of 
rated value. Pin 1 5 is able to output a 1 00 mA cur- 
rent to be sent to the gate of a SCR which, trig- 
gering, short circuits either output or the input. 
When connected to the input, as the SCR is trig- 
gered a fuse in series connected to power supply 
is blown and to bring the system back to operation 
manual intervention is requested. Figs. 19, 20 and 



21 show the different configurations. 

When the voltage on pin 1 exceeds by about 20% 
the Vref value the output stage is activated, which 
sends a current to the SCR gate, after a delay of 
about 5 JUsec to make the system insensitive to low- 
duration spikes. When activated, the output stage 
delivers about 100mA; when not activated.it drains 
about 5 mA and shows a low impedance to the SCR 
gate to avoid uncorrect triggering due to random 
noise. If the crowbar function is not used connect 
pin 1 to ground. 



Fig. 19 — Connection of crowbar circuit at output for 5.1V output applications. 




O v o 



Fig. 20 — Connection of crowbar circuit at output for output voltages above 5. 1 V. 




Fig. 21 — Connection of crowbar circuit to protect input. When triggered, the SCR blows the fuse. 




CROWBAR 



INHIBIT 

The inhibit input (pin 6) is TTL compatible and is 
activated when the voltage exceeds 2V and deacti- 
vated when the voltage goes under 0.8V. As may 
be seen in the block diagram, the inhibit acts on 
the power transistor, instantaneously switching it 
off and also acts on the soft-start, discharging its 
capacitor. When the function is unused, pin 6 must 
be grounded. 



THERMAL PROTECTION 

The thermal protection function operates when the 
junction temperature reaches 150°C; it acts directly 
on the power stage, immediately switching it off, 
and on the soft-start capacitor, discharging it. The 
thermal protection is provided with hysteresis and, 
therefore, after an intervention has occurred, it is 
necessary to wait for the junction temperature to 
decrease of about 30°C below the intervention 
threshold. 



141 



APPLICATIONS 

Though the L296 is designed for step-down regu- 
lator configurations it may be used in a variety of 
other applications. We will now examine these pos- 
sibilities and show how the capabilities of the device 
may be extended. 

In fig. 22 the complete typical application is shown, 
where all the functions available on the device are 
being used. This circuit delivers to the load a maxi- 
mum current of 4A and a voltage which is estab- 
lished by the voltage divider constituted by R7 and 
R 8 resistances. The following table is helpful for a 
quick calculation of some standard outputvoltages: 



Resistor value for 
standard output voltages 


Vo 


R 8 


R 7 


12V 
15V 
18V 
24V 


4.7 k£2 
4.7 kfi 
4.7 kSl 
4.7 k£2 


6.2 kSl 
9.1 kfi 
12 k£2 
18 kfl 



To obtain V = V RE p the pin 10 is directly con- 
nected to the output, therefore eliminating both 
R7 and Rg. The switching frequency is 1 00 kHz. 



Fig. 22 — Schematic, PCB layout and suggested component values for the evaluation circuit used to 
characterize the L296. This is a typical stepdown application which exercises all the device's 
functions. reset 



"i o 



C7,C8 : EKR (ROE) 




RESETO O INHBiT 



CS-0192/2 



v o O- 

gndO 



? 



-© 



-© 



f C8 )■ C? 



Q 1 ^ ' 





<£> 



mm 



Suggested Inductor (L1) 



OV; 



Core Type 


No 
Turns 


Wire 
Gauge 


Air 
Gap 


Magnetics 58930 -A2MPP 


43 


1.0 mm. 


- 


Thomson GUP 20x16x7 


65 


0.8 mm. 


1 mm. 


Siemens EC 35/17/10 
(B6633& -G0500-X127I 


40 


2x0.8 mm. 


- 


VOGT 250 /jH Toroidal coil, p 


art numbe 


5730501 BOO 





142 



Fig. 23 — Oscilloscope photographs showing main 
waveforms of the figure 22 circuit. 




t: 2;us/div 



The oscilloscope photographs of the main wave- 
forms are shown in fig. 23. The output voltage rip- 
ple AV depends on the current ripple in the coil 
and on the performance of the output capacitor at 
the switching frequency (100 kHz). A capacitor 
suitable for this kind of application must have a 
low ESR and be able to accept a high current ripple, 
at the working frequency. For this application the 
Roederstein EKR series capacitors have been selec- 
ted, designed for high frequency applications 
(>200 kHz) and manufactured to show low ESR 
value and to accept high current ripples. To mini- 
mize the effects of ESR, two 100 mF/40V capaci- 
tors have been connected in parallel. The behaviour 
of the impedance as a function of frequency is 
shown in fig. 24. 

Also the selection of the catch diode requires 
special care. The best choice is a Schottky diode 
which minimizes the losses because of its smal- 
ler forward voltage drop and greater switching fre- 
quency rate. A possible limitation comes from 
the backward voltage, that generally reaches 40V 
max. 

When the full input voltage range of the device is 
required in this application it is possible to use 
super fast diodes with 35 to 50 ns rated recovery 
time, where no more problems on the backward 
voltage occur (on the other hand, they show a 
greater forward voltage). The use of slower diodes, 



with trr = 100 ns or more is not recommended; 
The photographs in fig. 25 show the effects on the 
power current and on the voltage on pin 2, due to 
the diodes showingdifferentspeeds. Diodes showing 
trr greater than 35-50 ns will reduce the overall ef- 
ficiency of the system, increasing the power dis- 
sipated by the device. 

The third componentrequiring care is the inductor. 
Fig. 22a shows the part numbers of some types used 
for testing. Besides having the required inductance 
value, the coil has to show a very high saturation 
current. 

Therefore, a correct dimensioning requires a satu- 
ration current above the maximum value of I2 l- 
the current limit threshold. 

To achieve high saturation with ferrite cores an air 
gap between the two core halves must be provided; 
the air gap causes a leakage flux which is radiated in 
the surrounding space. To better limit this pheno- 
menon "pot cores" may be used, whose geometry 
is such to better limit the flux radiated to the out- 
side. 

Using toroidal cores, for instance of Magnetic 
58930-A2 moly-permalloy kind, both the require- 
ments of high saturation and low leakage flux are 
satisfied. The saturation is softer that the saturation 
shown by the ferrite materials. The air gap is not 
concentrated in one area, but is finely distributed 
along the whole core; this gives the low leakage 
flux value. 

Careful selection of the external components there- 
fore allows the realization of a power supply system 
whose benefits are significant when compared to a 
system with the same performance but realized with 
the linear technique. 

Fig. 24 — Typical impedance/frequency curves for 
EKR capacitors. 

G- 5476 













































































[ 






























_. 


















^ 




















. 












4- - 




1 — 1— ' 












L, t 


--t-4— 








1 ^ 


-><&£j-1 




















if^— — Wi 


" 






,_-biJ- 


s4 T^ 




V >. ^v^ 


■*Oc 


J i 




_£2o 


'2$\ ~t 


^^^ 


j^y,; 






— 


'"^f^sbt - 




■rf^Si 


■ r^ 








" - "~f ^ 










h_ TTi 


t+ ^*H 








! i 


T ^ n\ 

11 .1 1 1 . 



143 



Fig. 25 - Oscilloscope photographs showing the will be a least 5V at 4A. The minimum input volt- 
waveforms obtained with diodes having age is given by: 
different t rr values. 

_K ■■II V ' mm = V ° + V drop + y V ripple 

!HHP" Si iHHl where: 

!■«■«■■■■ ! v ripple ^ io_n _ tnu^l _ 3 2V 
rsSMBW«P« 

I diodeJLMtf|||£M|MI|IM||H||IUHMV| 

laHHSssir; r 

(a good approximation is 8 ms for t^ at mains fre- 
quency of 50Hz and 10.000 mF for C.the filter ca- 
pacitor after the bridge). Therefore V; min s 10.6V. 
Since operation must be guaranteed even when the 
mains voltage falls 20% , the nominal voltage on 
load at the terminals of the regulator must be: 

w V imin 10.6 

To allow even a small margin we have to choose: 

Vnom = 14V 

The power that the series element must dissipate is 
therefore: 

p d = (V nom - V Q > l = 36 W 

and a heatsink will be necessary with a thermal 
resistance of: 

Rth heats. = 0.8 °C/W 

and the transformer must supply a power of: 

p diss = 14x4 = 56W 

It must therefore be dimensioned for: 
t: 2jas/div 50 

Pd = = 62VA 

SWITCHING vs LINEAR ° 9 

Switching regulators are more efficient than linear 
types so the transformer and heatsink can be smal- 
ler anc cheaper. But how much can you gain ? Switching (L296) 

We can estimate the savings by comparing equiv- Assuming the same nominal voltage 114V), the L296 
alent linear and switching regulators. For example, data sheet indicates that the power dissipated in this 
suppose that we want a 4A/5V supply. case is only 7W. And this power is dissipated in two 

elements; the L296 itself and the recirculation diode. 

Linear '* follows that the trasnformer must be roughly 

30VA and the heatsink thermal resistance about 
For a good linear regulator the minimum dropout 11 °C/W. 

144 




■KnnI 


r- 


r - 


y. 




I I i I I 






- — 


— 


' — 


■|t rr < lUOnsH 






f<*f w 




: 


rf 




~>*1P 


Ut, 


.- -J 


l 


= L_J 




r 




■■■ 




:: 1 








•" 




IHlM 


1 




'ml 


t 


■■*]■■ 


p 


^^ 


1 





Linear 


Switching 


Transformer 
Heatsink 


62 VA 

0.8 °C/W 


30 VA 

11 °c/w 



This comparison shows that the L296 switching 
regulator allows a saving of roughly 50% on the 
cost of the transformer and an impressive 80-90% 
on the cost of the heatsink. Considering also 
the extra functions integrated by the L296 the 
total cost of active and passive components is 
roughly the same for both types. 

Finally, it is important to note that a lower power 
dissipation means that the ambient temperature in 
the regulator enclosure can be lower -particularly 
when the circuit is enclosed in a box - with all the 



advantages cooler operation brings. 

If for some reason it is necessary to use higher sup- 
ply voltages the switching technique, and hence the 
L296, becomes even more advantageous. 

LOW COST APPLICATION AND 
PREREGULATOR 

Fig. 26 shows the low cost application of a 4A and 
V = 5.1 V power supply. A minimum amount of 
essential external components is required, which 
are necessary for correct operation. It is impossible 
to save other components, specially the soft-start 
capacitor. Without soft-start, the system cannot 
reach the steady state and there is also a serious risk 
of damaging the device. 



Fig. 26 — A minimal component count 5, 1 V/4A supply, 

Q*I0V to.46V 



IOOOjUF/SOV 

_rHH 




INPUt 




300^H 



-LSGS8R20 
▲ OR 

I Bvwao 



~1 ' 



■ 2 2/"F 



This application is very well suited not only as a 
low-cost power supply, but also as pre-regulator for 
post-regulators distributed in differentcircuitpoints, 
or even on different boards (Fig. 27). The post-regu- 
lators may be selected among the low-drop types, 
like L4805 and L387 for example, still obtaining 
a high efficiency, combined with an excellent regu- 
lation. The use of L387 device allows us to use also 
the reset function, useful to power a micropocessor. 



POWER SUPPLY COMPLETE WITH 
TRANSFORMER 

Fig. 28 shows a power supply complete of trans- 
former, bridge and filter, with regulation on the 
output voltage from 5.1V to 15V. 

As already stated above, the output capacitors have 
to show some speciale features, like low ESR and 
high current ripple, to obtain low voltage ripple 



values and high reliability. The input filter capaci- 
tors must not be neglected because they have to 
show excellent features, too, having to supply a 
pulsed current, required by the device at the 
switching frequency. The current ripple is rather 
high, greater than the load current. For this appli- 
cation, two parallel connected 3300 jdF /50V EYF 
(ROE) capacitors have been used. 

POWER SUPPLY WITH MAINS 
SWITCHING PREREGULATOR 

When it is desirable to eliminate the 50/60 Hz 
transformer — in portable or volume-limited equip- 
ment—a mains preregulator can be added to reduce 
the input voltage to a level acceptable for the L296. 
In this case the pre-regulator circuit is connected to 
the primary of the transformer which now operates 
at the switching frequency and is therefore smaller 
and lighter. 



145 



Using a UC3840 which includes the feed-forward mary is no longer necessary, reduces the corn- 
function it is possible to compensate mains variation plexity and cost of the transformer which needs 
within wide limits. The secondary voltage is there- only a single secondary winding, 
fore only affected by load variations. Using one or Fig. 28 A shows a mu I ti -output supply with a mains 
more L296s as postregulators, feedback to the pri- preregulator. 



Fig. 27 — The L296 may also be used as a preregulator in distributed supply systems. 




6V L2*. 



4F? 



"X" 



X" 



X" 



7j — £ 



-0 5V 



RESET 
OUTPUT 



(*} L2 and C2 are necessary to reduce Ttle switching frequency spikes. 



Fig. 28 — A typical variable supply showing the mains transformer. 




*SG53ft20 OR BVW80 



V = 5.1 to 15V 

l Q = 4A max. (mm. load current - 100 mA) 

ripple < 20 mV 

load regulation (1A to 4A) - 10mV|V„= 5 IV) 

line regulation (220V ± 15% and to l = 3A) -= 15 mV (V - 5.1V) 



146 



Fig. 28A - A multiple output supply using a switching preregulator rather than a mains transformer. 




12V(200mA> 
-O 



POWER SUPPLY WITH - 30V ADJUST- 
ABLE VOLTAGE 

When output voltages lower than 5V are required, 
the circuit shown in fig. 29 may be used. 

Calibration is performed by grounding the P1 sli- 
der. Acting on P2, the current which flows through 
the 10 kfl resistor is fixed at approximately 2.5mA 
to obtain an output voltage of 30V. The equivalent 
circuit is shown in fig. 30. 

Acting now on the slider of P1, the current flow- 



ing through the divider may be varied. The new 
equivalent circuit is shown in fig. 31. 

Reducing the current flowing, also the voltage drop 
across the 10kfi resistance is reduced, together 
with V . When the current reaches zero, it follows 
that V = V REF . When the voltage on the slider 
of P1 exceeds Vref, the current start to flow in 
opposite direction and V begins to decrease below 
5V. 

When l x x 10Kn = V REF it follows that V = 0. 



Fig. 29 - Variable 0-30 V supply illustrating how output voltages below 5. 1 V are obtained. 




147 



Fig. 30 - When setting up the figure 29 circuit the 
slider of PI is grounded, giving the 
equivalent circuit shown here, and P2 
adjusted to give an output voltage of 
30 V. 

— ♦ O v o 



L296 io 



^"ref 



2.5 

m A 



Fig. 31 - Partial schematic showing output voltage 
adjustment of figure 29. 




DUAL OUTPUT REGULATOR 

The application shown in fig. 32 is specially inter- 
esting because it provides two output voltages. The 
first voltage, the main one, is directly controlled 
by the feedback circuit. The second voltage is ob- 
tained through an auxiliary winding. 

It often happens, when microprocessors, logic de- 
vices etc., have to be power supplied, that a main 
5V output and an auxiliary + 12V or — 12V out- 
put are required, the latter with lower current re- 
quirements (100 4- 200 mAl and a stabilization 
level not excessively high. As the auxiliary power 
supply is obtained through a completely separated 
winding, it is possible to obtain either a positive or 
negative voltage (compared to the main voltage or 
also a completely isolated voltage. With Vj variable 
between 20V and 40V, V Q = 5.1Vandl = 2.5A, 
the auxiliary -12V/0.2A voltage is within a ± 2%tol- 
erance. 



Fig. 32 - Dual output regulator showing how an additional winding can be added to the inductor to gene- 
rate a secondary output. 

4700JJF 



I 1 
3 

I mF ne.eKci 

I I" 




3 



:fc> f r 



WHIBIT 
INPUT 




zr 



2.2/uF 



;2.2/jF 



PERSONAL COMPUTER POWER SUPPLY 

Using two mutually synchronized devices it is pos- 
sible to obtain a four output power supply suitable 
for power a microprocessor system. 



V, 



01 
y 02 



"03 



5.1V/4A 

12V/2.5A (up to4A) 

-5V/0.2A 

-12V/0.2A 



The schematic diagram is shown in fig. 33. The 5V 
output is also provided with the reset function, that 
is available also for the 12V output. 

The feedback is direct, no other external com- 
ponent is used and no calibration is therefore requir- 
ed. An output is obtained with the accuracy of 
the reference voltage (± 2%). For the 12V output, 
by using a resistive divider with 1% resistance an 
output is obtained whose spread is within ±4% . 



148 



Fig. 33- Microcomputer supply with 5V, -5V, 12V and -12V outputs. 




moouF 

25V 
EKR 



The two devices are mutually synchronized not to 
give rise to intermodulation which could generate 
unpleasant noise and, at the same time, a further 
component saving is achieved. 

The crowbar function is implemented on both 5V 
and 12V outputs, using a single SCR connected to 
the input. The latter, by discharging to ground the 
electrolytic filter capacitors, blows the fuse con- 
nected in series with the devices power supply. In 
this way, should a faulty be present on either of 
the main outputs, the supply is switched off for 
whole system. 



To inhibit both the devices with a single input sig- 
nal, it is possible to connect the two inhibit inputs 
(pin 6) together; the 5KJ7 resistance is used when 
the inhibit input is left open. If this input is not 
used it must be grounded. 

As may be noted in the diagram, to obtain the two 
auxiliary voltages is very simple and cost-effective. 

It is suggested that the diodes are fast types (trr< 
50 nsec); should slower diodes be required some 
more turns have to be added to the auxiliary win- 
ding. 



149 



BATTERY CHARGER 

When the device has to be used as current generator 
it is necessary to avoid the internal current limiter 
is operated Fig, 34 shows the circuit realizing con- 
stant current limitation. In this way it is possible 
to obtain a 6V, 12V and 24V battery charger. For 
each of these voltages a max. current of 4A is avail- 



able, which is large enough for batteries up to 40- 
45 Ah (for 12V type). With reference to the electric 
diagram through the 2KfJ potentiometer the max 
output current is set, while through the H 1 — R2 
output divider the voltage is set. (Ri may be re- 
placed by either a potentiometer or a 3 position 
switch, to directly obtain the three 6V, 12V and 
24V voltages). 



Fig. 34 — Battery charger circuit illustrating how the device is used to regulate the output current. 

"T 




-* r - 



n Ji x,0 ° ^\ 

<n| ^« r I m 



1MJ1 470p^ T^OpF 



HIGHER INPUT VOLTAGE 



Since a maximum input voltage of 46V (operating 
value) may be applied to the device the diagram 
shown in fig. 35 may be used when it is necessary 
to exceed this limit. 

This system is particularly useful when operating at 
low output voltages. In this case a mean current 
'iDC which has a low value when compared to l is 
obtained. In fact, since V = V, (T n/T) and 
^o to = Vj 'iDC (assuming the device has an ideal 
efficiency), it follows that I|dc = 'o (Tqn/T). 
Assuming to be: 

v o = 5V l =4A and V 3 ~ 37V, 



it follows that: 

Ton/T = V /Vi = — = 0.135 

|, DC = 4x 0.135 = 0.54A. 

With input voltage 50V and l Q = 4A, the external 
transistor dissipates about 7W. High good efficiency 
is still achieved, around 74% ; in the real case, con- 
sidering also the device losses, an afficiency around 
62%is achieved. 

During output short circuits the external transistor 
is not overloaded because in this condition Ijdc 
reduces to values lower than 1 00mA. It is not pos- 
sible to realize this application with series post- 
regulator because the efficiency would be unac- 
ceptably low. 



Fig. 35 — The maximum input voltage can be raised above 46V by adding a transistor as shown here. 



V = + 4i 10 60V 

O 1— 



Ji 1 



"" T I 1 JC3 

1^ T S3300uF 

^ iZ1 T 5ov 
TV J39* 



3 L296 2 



"X - 



i 



150 



MOTOR CONTROL 

The L296 is also suitable for use in motor controls 
applications. Fig. 36 shows how to use the device 
to drive a motor with a maximum power of about 
100W and provided with a tachometer generator 
for a good speed control. 



HIGHER CURRENT REGULATORS 

It is possible to increase the output current to the 
load above 4A through the use of an external power 
transistor. Fig. 37 shows a suitable circuit. The fre- 
quency is around 40 kHz to prevent the device from 
loosing excessive power due to switching on the 
external power. 



The circuits shown in fig. 38 and fig. 39 show how 
current limitation may be realized in two different 
ways: through a sensing resistor connected in series 
with the collector of the external power transistor 
or through a current transformer. 

In the first case, the sensing resistor is a low value 
resistor able to withstand the maximum load cur- 
rent required. The V C £ of the power transistor is 
higher than its V CEsat ; when the resistor is connec- 
ted in series to the collector Vqe is reduced; conse- 
quently since the overall dissipated power is cons- 
tant, the power dissipated by the sensing resistor is 
subtracted from that dissipated by the power tran- 
sistor. The values indicated in figs. 38 and 39 reali- 
ze adjustable current limitation for load currents 
around 10A. 



Fig. 36 - With a tacho dynamo supplying feedback the L296 can be used as a motor speed controller. 




Fig. 37 — The output current may be increased by adding a power transistor as shown in this circuit. 



^V,.20¥tot6V 



10.000 AiF 50V 




VHE2401 l 

2.200|iiF M 



151 



Fig. 38 — This circuit shows how current limiting for the external transistor is obtained with a sensing 
resistor. 




2N2906A 



O"o 



Fig. 39 — A small transformer is used in this example for current limiting. 



j, !50nF 1N4001 

" -II I »' 



AD1 S 



1N4001 




T 



7nF n 220/1 



*T! ^MAGNETICS TOROID 
TYPE 55121 - A2 



STEP-UP CONVERTER 

With the L296 it is also easy to realize a step-up 
converter, by using a MOS power transistor. Fig. 40 
shows the electric diagram of the step-up converter. 
The frequency is 100 kHz, operation is in discon- 
tinuous mode and the device internal current lim- 
iter is used. Therefore no other external protection 
is required. 

The input voltage could be a 12V car battery, from 
which an output voltage of 35V may be obtained. 
Lower output voltage values may be obtained by 
reducing the value of R7. 



DESCRIPTION OF OPERATION 

Fig. 41 shows the diagram of the circuit realizing 
the step-up configuration. 

When the transistor Q1 is ON, the inductance L 
charges itself with a current given by: 

The peak current in the coil is: 

V, 
'peak ~ "j Tqn 



152 



Fig. 40 — A step-up converter using a power MOS transistor. 



J^ferT—°* 




Fig. 41 — Basic schematic for step-up configurat- 
ions. 




In this configuration, unlike the step-down con- 
figuration, the peak current is not strictly related 
to the load current. The energy stored in the coil is 
successively discharged across the load when the 
transistor switches OFF. To calculate the l load 
current, the following procedure may be used: 



1 I I 2 
— L 'peak 

2 
lo = 



V„ L 



L I 



peak 



V; 2 T ON 2 



2 V T 2 L V T 



LAYOUT CONSIDERATIONS 

Both for linear and switching power supplies when 
the current exceeds 1A a careful layout becomes 
important to achieve a good regulation. The prob- 
lem becomes more evident when designing switch- 
ing regulators in which pulsed currents are over im- 
posed on dc currents. In drawing the layout, there- 
fore, special care has to be taken to separate ground 
paths for signal currents and ground paths for load 
currents, which generally showa much higher value. 

When operating at high frequencies the path length 
becomes extremely important. The paths introduce 
distributed inductances, producing ringing phenom- 
ena and radiating noise into the surrounding space. 

The recirculation diode must be connected close to 
pin 2, to avoid giving rise to dangerous extra nega- 
tive voltages, due to the distributed inductance. 

Fig. 43 and fig. 44 respectively show the electric 
diagram and the associated layout which has been 
realized taking these problems into account. Greater 
care must be taken to follow these rules when two 
or more mutually synchronized devices are used. 



For a greater output power to be available, the 
internal limitation must be replaced by an external 
circuit to protect the external power devices and to 
limit the current peak to a convenient value. A dual 
comparator (LM393) with hysteresis is used to 
avoid uncertainties when the current limitation 
operates. The electric diagram is shown in fig. 42. 



153 



Fig. 42 - High power step-up converter showing how the current limiting function is realized externally. 




154 



Fig. 43 - Typical application circuit showing how the signal and power grounds are connected. 

RESET 



o- 



C1 
lOpFS 
63V 



R6 



,R2 

100 

C2 
2.2~F 



1296 



*Vl CA 



± L 3 n| ?oVi ^ u- 



L_^a 



GNDO ± 



C7.C8 : EKR (ROE) 



6 

INHIBIT 




o v ° 



OSND 



Suggested Inductor (L1) 



Cora Typa 


No 
Turns 


Wire 
Gauge 


Air 
Gap 


Magnetics 58930 - A2MPP 


43 


1.0 mm. 




Thomson GUP 20x16x7 


65 


0.8 mm. 


1 mm. 


Siemens EC 35/17/10 
(B6633&-G0500-X127) 


40 


2 x 0.8 mm. 


- 


VOGT 250 mH Toroidal coil, p 


art number 5" 


30501800 





Resistor values for 
standard output voltages 



12V 
15V 
18V 
24V 



R8 



4.7 k<2 
4.7 kS> 
4.7 k<2 
4.7 k<2 



6.2 kS2 
9.1 k!2 
12 kfi 
18 kS2 



Fig. 44 - A suitable PCB layout for the figure 43 circuit realized in accordance with the suggestions in 
the text (1 : 1 scale). 



RESetQ Oinhibit 




155 



HEATSIIMK DIMENSIONING 

The heatsink dissipates the heat produced by the 
device to prevent the internal temperature from 
reaching values which could be dangerous for device 
operation and reliability. 

Integrated circuits in plastic package must never 
exceed 150 °C even in the worst conditions. This 
limit has been set because the encapsulating resin 
has problems of vitrification if subjected to tempera- 
tures of more than 150 °C for long periods or of 
more than 170°C for short periods. In any case the 
temperature accelerates the ageing process and 
therefore influences the device life; an increase of 
10°C can halve the device life. A well designed 
heatsink should keep the junction temperature 
between 90°C and 1 10°C. Fig. 45 shows the struc- 
ture of a power device. As demonstrated in thermo- 
dynamics, a thermal circuit can be considered to be 
an electrical circuit where Ri, R2 represent the 
thermal resistance of the elements (expressed in 
°C/W) (see fig. 46). 



But since the aim of this section is not that of stud- 
ing the transistors, the circuit can be further redu- 
ced as shown in figure 48. 

Fig. 48 



Fig. 45 



PLASTIC PACKAGE 




Fig. 46 



, (T\ ' C1 i I C2 ! j C3 V C C4 f i 

2 HH HI— HH ■ — II — " _L 

DIE DIE ATTACH T AB HEAT5INK 



C1,C2 are the thermal capacitance (expressed in 

°C/W) 
I is the dissipated power 

V is the temperature difference with respect 

to the reference (ground) 

This circuit can be simplified as shown in fig. 47, 
where: 

C c is the thermal capacitance of the die plus 
that of the tab. 

is the thermal capacitance of the heatsink 
is the junction case thermal resistance 
is the heatsink thermal resistance 



C h 
Rjc 
Rh 



Fig. 47 





If we now consider the ground potential as ambient 
temperature, we have: 

T = T a + (R|„ + R h ) P d a) 



Rh Pd 

T c = T a + R h Pd 



b) 
c) 



Thermal contact resistance depends on various fac- 
tors such as the mounting, contact area and plan- 
arity of the heatsink. With no material between the 
device and heatsink the thermal resistance is around 
0.5 °C/W; with silicone grease roughly 0.3 °C/W 
and with silicone grease plus a mica insulator about 
0.4 °C/W. See fig. 49. In application where one ex- 
ternal transistor is used together, the dissipated 
power must be calculated for each component. The 
various junction temperatures can be calculated by 
solving the circuit shown in fig, 50. This applies if 
the dissipating elements are fairly close with 
respect to the dissipator dimensions, otherwise the 
dissipator can no longer be considered as a concen- 
trated constant and the calculation becomes 
difficult. This concept is better explained by 
the graph in fig. 51 which shows the case (and there- 
fore junction) temperature variation as a function 
of the distance between two dissipating elements 
with the same type of heatsink and the same dis- 
sipated power. The graph in fig. 51 refers to the 
specific case of two elements dissipating the same 
power, fixed on a rectangular aluminium plate with 
a ratio of 3 between the two sides. The temperature 
jump will depend on the total dissipated power and 
on the devices geometrical positions. We want to 
show that there exists an optimal position between 
the two devices: 



1 



Fig. 49 



side of the plate 



156 



Fig. 50 



h R /' H Rc 




Fig. 52 shows the trend of the temperature as a 
function of the distance between two dissipating 
elements whose dissipated power is fairly different 
(ratio 1 to 4). This graph may be useful in appli- 
cation with two L296 synchronized. 



Fig. 51 




d (cm) 



Fig. 52 



'• T ,-T CC) 



"H t— — r- 



150 
HO 
130 
120 
110 

100 
90 

3°-f" 
70 
60 



d (cm ) 



~~T 1 1— 



157 



APPENDIX A: 

CALCULATING SYSTEM STABILITY 

This section is intended to help the designer in the 
calculation of the stability of the whole system. 

Figure A1 shows the entire control system of the 
switching regulator. 

The problem which arises immediately is the trans- 
fer function of the PWM block and output stage, 
which is non-linear. If this function can be con- 
sidered linear the analysis is greatly simplified. 

Since the circuit operates at a constant frequency 
and the internal logic is fairly fast, the error intro- 
duced by assuming that this function is linear is 
minimized. Factors which could contribute to the 
non-linearity are an excessive delay in the output 
power transistor, ringing and parasitic oscillations 



generated in the power stage and non-linearity in- 
troduced by magnetic part. 

In the case of the L296, in which the power transis- 
tor is internal and driven by well-controlled and ef- 
ficient logic, the contribution to non-linearity is 
further reduced. 

For the assumption of linearity to be valid the cut- 
off frequency of the LC filter must be much lower 
than the switching frequency. In fact, switching 
operation introduces singularities (poles) at roughly 
half the switching frequency. Consequently, as long 
as the LC filter is still dominant, its cut-off fre- 
quency must be at least an order of magnitude 
lower than the switching frequency. This condition 
is not, however, difficult to respect. The charac- 
teristics of LC filter affect the output voltage wa- 
veforms; is generally much less than an order of 
magnitude below the switching frequency. 



Fig. A1 — The control loop of the switching regulator. 




GAIN OF THE PWM BLOCK AND OUT- 
PUT STAGE 

The equation which links V to V, is: 

V = V, T ° N 

T 

A variation ATqn in the conduction time of the 
switching transistor causes a corresponding varia- 
tion in the output voltage, AV , giving : 

AV _Vj 

At on t 

Indicating with V r the output voltage of the error 
amplifier, and with V ct the amplitude of the ramp 
(the difference between the maximum and mini- 
mum values), T ON is zero when V r is at the mini- 
mum value and equal to T when V r is at a maxi- 
mum. Consequently: 

ATon T 



AV r v ct 

The gain is given by: 

AV ^ Vj 

Av r V ct 

Since V ct is absolutely constant the gain of the 
PWM block is directly proportional to the supply 
voltage Vj. 



ERROR AMPLIFIER 

The error amplifier is a transconductance amplifier 
(it transforms a voltage variation at the input into 
a current variation at the output). It is used in open 
loop configuration inside the main control loop 
and its gain and frequency response are determined 
by a compensation network connected between its 
output and ground. 



Fig. A2 — Open loop frequency and phase response 
of error amplifier. 

























X 


Gy 




















s 
















r \ 











































































158 



In the application a series RC network is recommend- 
ed which gives high system gain at low frequency — 
to ensure good precision and mains ripple rejection 
and a lower gain at high frequencies to ensure stab- 
ility of the system. Figure A2 shows the gain and 
phase curves of the uncompensated error amplifier. 

The amplifier has one pole at about 7 kHz and a 
phase shift which reaches about — 90° at frequen- 
cies around 1 MHz. 

The introduction of a series network R c Cc be- 
tween the output and ground modifies the circuit 
as shown in figure A3. 

Figure A4 shows the gain and phase curves of the 
compensated error amplifier. 



Fig. A3 - 



Compensation network of the error 
amplifier. 




The DC gain must be considered equal to 

A o = 9m R o 

PWM block and output stage: 

V; 



3 PWM =- 



Vet 



LC FILTER: 



3 LC 



1 +s C • ESR 
s 2 LC + s C ESR + 1 



where ESR is the equivalent series resistance of the 
output capacitor which introduces a zero at high 
frequencies, indispensable for system stability. Such 
a filter introduces two poles at the angular fre- 
quency. 

1 



S-6858 



Refer to the literature for a more detailed ana- 
lysis. 

Feedback: consists of the block labelled a 

a= 1 when V = V REF (and therefore V = 5.1V) 

and 

R 2 
a= _- /■ when V >V REF 
1 2 



Fig. A4 — Bode plot showing gain and phase of 
compensated error amplifier. 



Fig. AS — Block diagram used in stability calculat- 
ion 



UNCOMPENSATED 
COMPENSATED 




2TTR C C 2Tm c C c 2TT R C 2TTR C C 



CALCULATING THE STABILITY 

For the stability calculation refer to the block dia- 
gram shown in figure A5. 

The transfer functions of the various blocks are re- 
written as follows. 



9m*c 



Vet 




L 






















X 















To analyse the stability we will use a Bode diagram. 
The values of L and C necessary to obtain the re- 
quired regulator output performance, once the fre- 
quency is fixed, are calculated with the following 
formulae: 

= (Vj-Vp) Vq 

V; f Al L 

= (Vi-Vo)Vo 
8 L f 2 AV 

Since this filter introduces two poles at the angular 
frequency 
1 



Vlc 



The simplified transfer function of the compensated we place the zero of the R c Q network in the same 
error amplifier is: place: 

1 + s R r C c ,.. 1 1 



J EA 



9m" 



s C r 



<9m = 



2500 



Rr- C r _ 



159 



Taking into account also the gain of the PWM block, 
the Bode plot of figure A6 is obtained. 

The slope where the curve crosses the axis at dB 
is about 40dB/decacie therefore the circuit is un- 
stable. 

Taking into account now the zero introduced by the 
equivalent series resistance (ESR) of the output ca- 
pacitor, we have further condition for dimensioning 
the R c C c network. Knowing the ESR (which is 
supplied by the manufacturer for the quality com- 
ponents) we can determine the value of R c so that 
the axis is crossed at OdB with a single slope. The 
zero introduced by the ESR is at the angular fre 
quency: 



1 



"zESR 



ESR • C 



The overall Bode diagramm is therefore as shown 
in figure A7. 



Fig. A6 — Bode plot of system taking filter and 
compensation network into account 



DC GAIN AND LINE REGULATION 

Indicating the open-loop gain of the error amplifier 
with A„, the overall open-loop gain of the system is". 



A t 



A r 



M 



R-: 



When V = V R f£F, the gain becomes: 

Vi 
At = A oV - 
v ct 

Considering the block diagram of figure A8 and 
calculating the output variation AV caused by a 
variation of \A, from the literature we obtain: 



Av„ 



Ag Vi 

v, t 



Ri + R- 



This espression is of genera! validity, in our case 
the percentage variation of the reference must be 
added by vector addition. 



Fig. A8 - Block diagram for calculation of line 
regulation. 





+ 












V, 


+ 

! 


REF 




A o 


Vet 






















R2 














R1+R2 







-*. V o 



Fig. A7 — Bode plot of complete system taking 
into consideration the equivalent series 
resistance of the output capacitor. 

dB | 




Vet 



APPENDIX B: 

REDUCING INTERFERENCE 

The main disadvantage of the switching technique 
is the generation of interference which can reach 
levels which cause malfunctions and interfere with 
other equipment. 

For each application it is therefore necessary to 
study specific means to reduce this interference 
within the limits allowed by the appropriate stan- 
dards. 

Among the main sources of noise are the parasitic 
inductances and capacitances within the system 
which are charged and discharged fastly. Parasitic 
capacitances originate mainly between the device 
case and the heatsink, the windings of the inductor 
and the connection wires. Parasitic inductances are 



160 



generally found distributed along the strips of the 
printed circuit board. 

Fast switching of the power transistors tends to 
cause ringing and oscillations as a result of the 
parasitic elements. The use of a diode with a fast 
reverse recovery time (trr) contributes to a re- 
duction in the noise flowing by the current peak 
generated when the diode is reverse biased. 

Radiated interference is usually reduced by enclos- 
ing the regulator in a metal box. 

To reduce conducted electromagnetic interference 
lor radio frequency interferences - RFI) to the 
levels permitted a suitably dimensioned filter is ad- 
ded on the supply line. The best method, generally, 
to reduce conducted noise is to filter each output 
terminal of the regulator. The use of a fixed switch- 
ing frequency allows the use of a filter with a rela- 
tively narrow bandwidth. For off-line switching re- 
gulators this filter is usually costly and bulky. In 
contrast, if the device is supplied from a 50/60 Hz 
transformer the RFI filter problem is greatly re- 
duced. 

Tests have been carried out at the laboratories of 
Roederstein to determine the dimensions of a mains 
supply filter which satisfies the VDE 0871/6.78, 
class B standard. The measurements (see figs. B1 
and B2) refer to the application with the L296 sup- 
plied with a filtered secondary voltage of about 30V, 
with V = 5.1V and l = 4A. The switching fre- 
quency is 100 kHz. 

Figure B1 shows the results obtained by introduc- 
ing on the transformer primary a 0.01 mF/250V~ 
class X capacitor (type ERO F1 772-31 0-2030). To 
reduce interference further below the limit set by 
the standards an additional inductive filter must be 
added on the primary of the transformer. 

Figure B2 shows the curves obtained by introducing 
this inductive filter (type ERO F1 753-210-124). 

Measurements have also been performed beyond 
30 MHz; the maximum value measured is still well 
below the I imit curve. 



Fig. B1 — EMI measurements with a capacitor con- 
nected across the primary transformer 
with screen grounded (A) and floating (B) 




lOKHz 3C 100 300 IMHi 



Fig. B2 - EMI results with the addition of an 
due five filter on the mains input. 




100 300 



1MH7 3 



161 



DESIGNING MULTIPLE-OUTPUT 
POWER SUPPLIES WITH THE L296 AND L4960 

Multiple output supplies can be realized simply and economically using the SGS L296 and L4960 high 
power switching regulators. This note describes several practical circuits of this type. 




Most of the switching regulators produced today 
have multiple outputs. The output voltages most 
frequently used - at least for powers up to 50W - 
are +5V -5V, + 12V and -12V. In these supplies the 
5V output is normally the output which delivers 
the highest current and requires the highest pre- 
cision. For the other voltages - particularly the 
negative outputs - less precision (±5% +7% ) is 
usually sufficient. Often, however, for high current 
12V outputs better stabilization and greater 
precision (typically ±4% - the output tolerance of 
an L7800 series linear regulator) are required. 

Multiple output supplies which satisfy these re- 
quirements can be realized using the SGS L296 and 
L4960 high power switching regulator ICs, Several 
practical supply designs are described below to 
illustrate how these components are used to build 
compact and inexpensive multi-output supplies. 



DUAL OUTPUT 15W SUPPLY 

Vol = 5V/3A, V 2 = 12V/150mA 
A single L296 is used in this application to produce 
two outputs. The application circuit, Figure 1, il- 
lustrates how the second output (12V) is obtained 
by adding a second winding to the output in- 
ductor. Energy is transferred to the secondary 
during the recirculation period when the internal 
power device of the L296 is OFF. 
Since the 12V output is not separated from the 5V 
output fewer turns are necessary for the second 
winding, therefore less copper is needed and load 
regulation is improved. 

In applications of this type it is a good rule to 
ensure that the power drain on the auxiliary out- 
put is no more than 20-25% of the power delivered 
by the main output. 



163 



Fig. 1- Dual output DC-DC converter (5V/3A, 12V/150mA) 



iuuu ajt 




if 



BYV 26-50 : +12V 

X f -o 

02 A0V=t= ? , n . lF 
. N2 EKRJ 220 ^ 

~ '"" + 5.1V 




Transformer: magnetics 58930, N1 = 30 turns, N2 = 40 turns 



Table 1 shows the performance obtained with this dual output supply. This circuit operates at a switch- 
ing frequency of 50KHz. 

TABLE 1 



Parameter 



Output voltage 
lol = 3A 



Output ripple 



Line regulation 
lol = 3A 



Line regulation 
lol = 700mA 



Load regulation 
lol = 700mA -+3A 



Load regulation 
lol = 700mA 



Load regulation 
lol = 3A 



Efficiency 



V| = 30V 
l o2 = 150mA 



20V < Vi < 40V 
lo2= 150mA 



20V < Vi < 40V 

lo2 = 100mA 



V| = 30V 
lo2 = 150mA 



Vi = 30V 

lo2 = 1 00 -* 150mA 



Vi = 30V 

lo2 = 100^ 150mA 



Vi = 30V 

V 1 = 5.120V lol=3A 

V 2= 12.089V lo2 = 150mA 



Vol 



5.120 



70 



15 



15 



10 



V02 



12.089 



40 



30 



10 



130 



40 



40 



75 



Unit 



[mV] 



[mVl 



[mV] 



[mV! 



[mV! 



[mV: 



simple dual output supply with the L4960, a 
device containing the same control loop blocks 
as the L296 and a 2A output stage. (Fig. 2). Though 

» UJ . „., ,, . „^ ._...--. this circuit costs very little the performance 

The same technique -adding a secondary winding - obtained (see Table 2) is more than satisfactory, 
can also be used to produce an economical and The switching frequency is 50kHz. 

164 



DUAL OUTPUT 7.5W SUPPLY 

Vol = 5V/1.5A, Vo2= 12V/100mA 



Fig. 2- Dual output DC-DC converter (5V/1.5A, 12V/W0mA) 



-15V to 35 V 




220^uF 
iOV 



Transformer: magnetics 58206, N1 = 30 turns, N2 = 40 turns 



TABLE 2 



Output voltage 
lol = 1.5A 



Output ripple 



Line regulation 
lol = 1.5A 



Line regulation 
lol = 500mA 



Load regulation 
lol = 0.5A-M.5A 



Parameter 



Load regulation 
lol = 500mA 



Load regulation 
lol = 1.5A 



Efficiency 



Vi = 25V 
lo2 = 100mA 



15V < Vi < 35V 
lo2 = 100mA 



15V < Vi «35V 
lo2 = 50mA 



Vj = 25V 
lo2 = 100mA 



Vi = 25V 

l 2 = 50mA-* 100mA 



Vi = 25V 

lo2 = 50mA -*■ 100mA 



Vi = 25V 

101 = 1.5A 

102 = 100mA 



Vol 



5.050 



50 



Vo2 



12.010 



30 



75 



60 



78 



100 



55 



50 



Unit 



[mV] 



[mV] 



[mV] 



[mV] 



TRIPLE OUTPUT 15W SUPPLY used - 

To ensure good tracking of the 12V and -12V 
vol - 5V/3A, Vo2- 12V/100mA, Vo3= -12V/100mA outputs the secondary outputs in this application 
Figure 3 shows how to obtain two auxiliary out- snould be bifilar wound. 

Juts (± 12V) which are isolated from the 5V This circuit operates at 50KHz and gives the per- 
sutput. For this output power range an L296 is formance indicated in Table 3 

165 



Fig. 3- Triple output DC-DC converter (5V/3A, 12V/100mA, -l2V/100mAI 



20V to 40V ( 




L296 




i 6 



_. --SGS8R20 
nl 41 OR 



UT~± !& 



— 0-12V 
BYV28-50 
-t — 05.1V 

S220>jF 

"™ EKR 



TABLE 3 



Parameter 


Vol 


Vo2 


Vo3 


Unit 


Output Voltage 
lol =3A 


V| = 30V 

lo2 = lo3 = 100mA 


5.057 


12.300 


-12.300 


[V] 


Output ripple 


80 


30 


30 


[mV] 


Line regulation 
lol = 700mA 


20 < V| < 40V 

lo2 = lo3 = 100mA 


15 


60 


60 


[mV] 


Line regulation 
lol = 3A 


20 < Vj < 40V 

lo2 = lo3 = 100mA 


18 


100 


100 


tmV] 


Load regulation 
lol = 0.7^3A 


Vj = 30V 

lo2 = lo3 = 100mA 


4 


150 


150 


[mV] 


Load regulation 
lol = 3A 


Vi = 30V 

102 = 100mA 

103 = 50 -> 100mA 





125 


52 


[mV] 


Load regulation 

101 =3A 

102 = 50-* 100mA 


Vj = 30V 
lo3 = 100mA 





50 


120 


L mV] 
% 


Efficiency 


76 



TRIPLE OUTPUT 7.5W SUPPLY 



For lower output powers, the L296 in the previous 
application may be replaced by an L4960 as shown 
in Figure 4. The performance of this circuit is 
V ol = 5V/1.5A, Vo2= 12V/50mA, Vo3= -12/50mA indicated in Table 4. 

166 



Fig. 4 - Triple output DC-DC converter (5V/1.5A, 12V/50mA, - 12V/50mA) 



1000 uF 



>• 15V to 35V 



3+1 ZV 



1Ka M EKRj 220 ^ 

\\ lnF= wvhi 
I EKRi=220>jF 




+ 5V 



TABLE 4 



S-6059,'2 



Parameter 


Vol 


Vo2 


Vo3 


Unit 


Output Voltage 
iol = 1.5A 


Vi = 25V 

'o2 = lo3 = 50mA 


5.040 


12.020 


-12.020 


[V] 


Output ripple 


60 


30 


30 


[mV] 


Line regulation 
lol = 500mA 


15 « V| < 35V 
lo2 = lo3 = 50mA 


5 


80 


80 


[mV] 


Line regulation 
lol = 1.5A 


15 < V(<35V 
lo2 = lo3 = 50mA 


4 


60 


60 


[mVl 


Load regulation 
lol = 0.5^1.5A 


V, = 25V 

lo2 = lo3 = 50mA 


5 


120 


120 


[mV] 


Load regulation 

lo = 1.5A 

lo3 = 20-* 50mA 


V| = 25V 
lo2 = 50mA 





15 


50 


[mV] 


Load regulation 

101 = 1.5A 

102 = 20 -► 50mA 


V| = 25V 
lo3 = 100mA 





50 


15 


[mV] 


Efficiency 


70 




% 



THE L296 AND L4960 HIGH POWER 
SWITCHING REGULATORS 



The SGS L296 is a monolithic stepdown switching 
regulator assembled in the 15-pin Multiwatt 
package. Operating with supply input voltages up 
to 46V it provides a regulated 4A output variable 
from 5.1V to 40V. 

Internally the device is equipped with current 
limiter, soft start and reset (or power fail) func- 
tions, making it particularly suitable for supplying 
microprocessors and logic. 



The precision of the L296's internal reference 
(±2% ) eliminates the need for external dividers or 
trinning to obtain a 5V output. 

The synchronization pin allows synchronous ope- 
ration of several devices at the same frequency to 
avoid generating undesirable beat frequencies. 

The L4960 is a similar device assembled in the 
7-lead Heptawatt package. Like the L296 it has 
a maximum input voltage of 46V and it provides a 
regulated output voltage variable from 5V to 40V 
with a maximum load current of 2.5A. Current 
limiting, soft start and thermal protection func- 
tions are included. 



167 



The thermal protection circuit in both the L296 
and L4960 has a hysteresis of 30°C to allow soft 
restarting after a fault condition. 



The absolute average current in the sypply is there- 
fore : 



THE STEP DOWN CONFIGURATION 

Figure 5 shows the basic structure of a step down 
switching regulator. The transistor Q is used as a 
switch and the ON and OFF times are determined 
by the control circuit. 

When Q is saturated current flows from the supply, 
Vi, to the load through the inductor L. Neglecting 
the saturation voltage of Q, Ve - Vi. 

When Q is OFF, current continues to flow in the 
inductor L, in the same direction, forcing the diode 
into conduction immediately therefore Ve is nega- 
tive. In these conditions the load current flows 
through L and D. 

The average value of the current in the inductor is 
equal to the load current. In the inductor a triangu- 
lar current ripple equal to Ati_ is added to this 
average current. 

During the time when Q is ON this ripple is : 



AI L = 


(V, 


- V o> T ON 




L 


and wh 


en Q 


is off it is: 


AI L = 


V o- 


T OFF 







Equating these expression and assuming that the 
transistor and diode are ideal we obtain : 



Once the working frequency and desired ripple 
current have been fixed the value of the inductor 
L is given by : 

«v,-v ) v 



V f AI L 



and the value of the capacitor C required to give 
the desired output voltage ripple (AV) is : 



<V V o> V o 



8 Lf 2 Af r 



This capacitor must have a maximum ESR given 
by : 

ESR* 



WAX 



Al, 



And, finally, the minimum load current, loMIN, 
must be : 



lOMIN = 



AIl (Vi - Vo) Vo 



2Vj f L 



V =V, 



'ON 



Ton is the conduction time 
of the transistor 



T is the oscillator period 



Fig. 5- Basic STEP-DOWN configuration 




V REF 



168 



30W DC-DC CONVERTER 



Designing power supplies in the 30-40W range is 
becoming increasingly difficult because it is here 
that there is the greatest need to maintain per- 
formance levels and reduce costs. The application 
proposed here is very competitive because it 
exploits new ICs to reduce size, number of com- 
ponents and assembly costs. 

This solution, the DC-DC converter, compares very 
favourable with off-line switching supplies in terms 



of cost. DC-DC converters can, in fact, be realized 
even by designers with little e-xperience and allows 
the convenience of working with low voltages, 
Off-line switching supplies gre only preferable 
when the weight and size of tffe mains transformer 
in a DC-DC converter would be excessive. 

In this circuit, figure 6 two devices are used, an 
L296 and an L4960. The L296 is used, to supply a 
5V output with a current of 3A and the auxiliary 
-5V/100mA output and the L4960 is used to pro- 
vide the 12V/1 .5 A output and the auxiliary -12V/ 
100mA output. 



Fig. 6- Multioutput DC-DC converter with L296 and L4960 (5V/3A, 12V/1.5A,-12V/100mA,-5V/100mA! 

20V<=V|<40V 

O- 




ZlOOOjuF 
25V 
EKR 



169 



Table 5 shows the performance obtained 
TABLE 5 



with this power supply. 



Parameter 


Vol 


Vo2 


Vo3 


Vo4 


. 

Unit 


Output Voltage Vi = 30V 

101 = 3A lo3 = 1.5A 

102 = 100mA lo4 = 100mA 


5.080 


-5010 


11.96 


12.00 


[V] 


Output ripple 


50 


30 


50 


40 


[mV] 


Line regulation 20 « Vi « 40V 
lol = 1A lo2 = 100mA 
lo3 = 0.5A lo4 = 100mA 


13 


15 


10 


20 


[mV] 


Load regulation Vi = 30V 
lol = 1Ato3A lo2 = 100mA 


8 


90 






[mV] 


lo3 = 0.5 to 1.5A l 4 = 100mA 






3 


80 


[mV] 


Load regulation Vi = 30V 

lol = 3A lo2 = 50-*100mA 





100 






[mV] 


lo3 = 1.5A lo4 = 50 ->• 100mA 









100 


[mV] 


Load regulation Vi = 30V 

lol = 1A lo2 = 50 -> 100mA 





35 






[mV] 


lo3 = 0.5A lo4= 50 -> 100mA 









90 


[mVl 


Line regulation 20 < Vi « 40V 
lol = 3A lo2 = 100mA 


15 


45 






[mV] 


lo3 = 1.5A lo4 = 100mA 






15 


40 


[mV] 



This application illustrates how two devices may If a power fail function is required in place of 

be synchronized. Note also that the reset circuit is the reset function the Figure 6 circuit should be 

used in this case to monitor the output voltage modified as shown in Figure 8. 
(see figure 7). 



Fig. 7- Reset output waveforms 



RESET 
THRESHOLD" 



MONITORED 
VOLTAGE 



OUTPUT NOW 
STABLE, RESET 
GOES HIGH 
lOOmV OF I 

HYSTERESIS J 



AN INTERRUPTION 
OF SUPPLY CAUSES 
RESET OF MICRO 



RESET 

OUTPUT 



¥ 



DELAY DELAY 

170 



AT P0WIR DOWN 
MICRO IS INHIBITED 
/ IMMEDIATELY 



Fig. 8 




-RESET 



CALCULATING THE POWER FAIL TIME the time when the input voltage falls to the mini- 
mum level required to maintain the regulated 
The 'power fail time' is defined as the time from output (see Figure 9), From this definition we can 
when the power fail output (pin 14) goes low to evaluate the energy balance. 



Fig. 9 



Vj 




V| 


«r V l 


\ V. 












V I2 






-LV 












I 




, 'PF 




t 


PF WAVE FORM , 
(PIN 16) 












































\ 


i 












* 



The energy which the filter capacitor C supplies 
to the operating device while it discharges is: 



E = 1/2C (Vi J 



V 2 2 



(1) 



1/2C (Vi 2 



V 2 'l 



Equating the expressions (1 ) and (2) gives: 
Po 

• tPF 

I? 

where Vj | s the input voltage at which the voltage 
on pin 12 reaches 5V (through the divider R1/R2); 
V2 is the maximum input voltage below which 



The load drains a power of P = Vo lo. Taking into 

consideration the average efficiency n (derived the device" no longer regulates. 

with the input between Vi and V2), the power to 

be supplied at the input of the device is: Rearranging this expression to obtain C: 



P02 



Po 

V 



(2) 



2PptPF 
V (Vi 2 -V 2 2 



171 



EXAMPLE - Suppose that V = 5V, 
T pf = 10ms and V, = 35V. Fixing Vi = 
V2 = 10V we obtain: 



2 Po tPF 
T) (V1 2 -V 2 2 



2x15x 10 • 1Q- ! 
0.75 (25 2 -10 2 



lo = 3A, 
25V and 



= 760/mF 



Figs 10 - Load current in short circuit conditions 
(Vi = 40V, L = 300iiH, f = WOKHzj 



We therefore choose a capacitor of 1000/iF. 



CROWBAR 

The L296 includes an internal crowbar function; 
the only external component needed is an SCR. 
The intervention threshold of this block is fixed 
internally at ± 20% of the nominal value of the 
internal reference. 

In the Figure 6 circuit the SCR is triggered by an 
overvoltage on the 5V output (usually the most 
important output to monitor) and shortcircuits 
to ground the 5V output and, through the diode 
which connects the two outputs, the 12V output. 

Since the internal current limiter in the device is 
designed to function as shown in Figure 10 (that 
is, with pulsed output current) the SCR turns 
off in the gap between pulses and is re-activated 
gain if, when the device restarts softly, the fault 
condition has not been eliminated. But if the fault 
no longer exists the SCR remains OFF and the 
output voltage returns to the normal value. 

If the designer prefers the supply to remain off 
after the SCR has been activated the circuit can be 
modified as shown in Figure 11. In this modifica- 
tion, when the SCR is triggered a very high current 
flows in the fuse, blowing it. 

Since the filter capacitor can have a high value 
and be charged to high voltages the choice of SCR 
is important. The type used in this circuit - the 
TYP512 - is a plastic packaged SCR able to handle 
12Arms and 300A for 10ms. The maximum forward 
and reverse voltages are about 50V. 

If the crowbar circuit is not used it is advisable to 
connect pin 1 to ground or pin 10. 




t : 5ms/div 
Current at pin 2 when the output is short circuited. 




t : 5ms/div 



Fig. 11 



i it 




172 



DUAL REGULATORS SIMPLIFY 
MICRO SYSTEM SUPPLY DESIGN 

Combining two 5V regulators and a reset circuit on a single chip, special purpose regulator 
chips simplify the design of power supplies for microprocessor systems incorporating battery 
backup RAMs or shadow-type NV RAMs. 



Power supplies for microprocessor systems are 
often complicated by the need to take care of the 
special requirements of non-volatile read/write 
memory. Where battery backup CMOS RAMs are 
used, for example, it is important to ensure that 
the RAMs are disabled when the primary supply is 
removed. And when shadow-type NV memory is 
included the backup transfer must be initiated and 
completed when the supply is interrupted. Designed 
specifically for such applications, the SGS L4901, 
and L4902 dual voltage regulators combine two 5V 
regulators plus a reset circuit on a single chip, sim- 
plifying the designer's task. 

Assembled in the SGS Heptawatt [TM] 7-lead 
package, the L4901 and L4902 contain separate 
voltage regulators rated at 5V/300mA (the "V1" 
output) and 5V/400mA (the "V2" output). 

Both the V1 and V2 regulators have an output 
voltage precision of ± 2% and include protection 
against output short circuits and 60V input tran- 
sients. Also included on the chip is a reset circuit 



with externally programmable timing which de- 
pends on the input voltage and the output of the 
V1 regulator. 

Functionally, the two devices are identical except 
that the L4901 has separate inputs to the two 
regulators and the L4902 has a common input plus 
a disable input which controls the V2 output. (Fig. 1) 
Generally the V1 regulator is used to supply cir- 
cuits which must be powered continuously — 
volatile memory, a time-of-day clock and so on - 
while the V2 output supplies other 5V circuits 
which may be powered down when the equipment 
is inactive, 

The VI output features a very low leakage current 
at the output - less than 1mA - to allow the use 
a backup battery. The V1 regulator also features a 
low quiescent current at the input (0.6mA typical) 
to minimize battery drain in applications where the 
V1 regulator is permanently connected to a battery 
supply, 



Fig. 1a - TWO 5V OUTPUTS - The 14901 Dual Fig. 1b - DISABLE INPUT- The L4902 is similar 
Regulator provides 300mA and 400mA 5V outputs to the L4901 but also features a disable input for 
and includes a microprocessor reset function, the V2 regulator. 
This device is ideal for microprocessor systems 
with battery backup or shadow RAM. 



^r 



-i L_ 



THERMAL 
PROTECTION 



"X 



-L RESET 
T" DELAY 



JgSE, 



173 



Fig. 2 - WAVEFORMS — An important feature of the L4901 series regulators is that the reset circuit 
monitors the input voltage. 

+ V IN. V 01 




SWITCH 
ON 



SWITCH 
OFF 



VERSATILE DEVICES 

The L4901 and L4902 are versatile devices which 
simplify the supply circuitry of many systems and 
can be used in a number of different mays. 

One possibility, outlined in figure 3, is to connect 
the V1 regulator permanently to a battery to 
supply a CMOS time-of-day clock and a CMOS 
microcomputer chip with volatile memory. In this 
example the V2 output supplies non-essential 5V 
circuits. A typical use of this scheme is in trip com- 
puters or car radios with programmable tuning. 

An alternative, shown in figure 4, is to use the 
L4901 with a backup battery on the V1 output to 
maintain a CMOS clock and a standby-type NMOS 
microcomputer chip. In this case the main on/off 
switch disconnects both the V1 and V2 regulators 
from the battery. 

Figure 5 illustrates how the L4902's disable input 



may be used in a CMOS microcomputer applica- 
tion. In this example the V2 output, supplying 
non-essential circuits, is turned off under control 
of the microprocessor circuit. Configurations of 
this type are used in products where the "OFF" 
switch is part of a keypad scanned by a micro 
which operates continuously, even in the "OFF" 
state. 

The L4901 is also ideal for microcomputer systems 
using battery backup CMOS static RAMs. As shows 
in figure 6 the V1 output supplies the CMOS RAMs 
and the V2 output supplies the microprocessor 
plus other 5V circuits. The L4901's reset output is 
used both to reset the Z80 and, through the 
M74HC138 address decoder, to ensure that the 
RAMs are disabled as soon as the main supply 
voltage starts to fall. Note that the M74HC138 is 
supplied from the backup battery. 



Fig. 3 - LOW QUIESCENT CURRENT at the V1 input makes the L4901 useful in applications like this 
where the V1 regulator is always connected to the battery. 



0.22*jF 



7 OUT 1 

— | T 



5 RESET OUT i RESET 



CMOS 
CLOCK 



CMOS 

AJP WITH 

VOLATILE 

RAM 



OTHER 
LOGIC 

@5V 



174 



Fig. 4 - LOW LEAKAGE at the V1 output makes the L4901 ideal for battery backup operation. 

7 OUT 1 ' j-Dl <2< jA V„ D 



-GEO- 



C MOS 

CLOCK 



BACKUP 
BATTERY 



6 OUT 2 V, D 

— T ' " 

~^ i RESET ] 

5 RESET Out] RESET 



/jP(3875-2875) 

WITH BATTERY 

BACKUP 

RAM 



OTHER LOGIC 



Fig. 5 - STANDBY - The L4902 can be used in applications where the supply is connected permanently 
and the disable function used to turn off non-essential circuits in the standby state. 





, f 






7 OUT 1 


V DD 




INI 1 


REG.l 


1 


CMOS 
CLOCK 


PATTERY i — l— i 


1 1 


J 


^ 1/UF 
3 V 02 DIS 


V 0D„ 
OUT PORT 


I ^ F X 




CMOS 

JUP WITH 

VOLATILE 

RAM 




6 0UT2 


IN PORT 




H 


REG. 2 


1 




1 


t 

,-L, 1 tolO/Llf 

5 RESET OUT 


I J 

o 








OTHER 
LOGIC 

?5 5V 


2 

Ct 

10 nF 2^ 


1 

i RESET 
- - * » 













It is important to make sure that the RAMs are 
disabled because the lithium cells used as backup 
batteries have a high internal resistance. If the 
RAMs were not forced into the low consumption 
standby state the battery voltage could drop so low 
that memory contents are corrupted. Moreover, to 
prevent latch up, no input of a CMOS RAM should 
ever be higher than the supply voltage. 

IDEAL FOR SHADOW MEMORIES 

Another interesting application for the L4902 is 
supplying a shadow-ram microcomputer chip like 
the SGS M38SH72 where a fast non-volatile 
memory is backed up on-chip by a slow EEPROM 
{figure 7). For these chips it is important to ensure 
that the backup command is generated when the 



supply is removed, a function which the L4902's 
reset output can perform. Since the L4902's reset 
function depends on the INPUT voltage the power 
fail condition is sensed early enough to guarantee 
that the backup transfer will be successful. 

In figure 7 the reset output is forced low when the 
input voltage falls below 6.3V or when the V1 out- 
put goes below 4.8V. This allows 10ms for the 
backup transfer (with 10,uF capacitors) which is 
more than sufficient. 

Similarly, the L4902 can be used with shadow- 
type RAMs such as the Xicor X2201. In the figure 
8 circuit a capacitor on the V1 input ensures that 
the X2201 is powered during the transfer opera- 
tion. When the input voltage is removed or goes 
below 6.3V the L4902's reset output, connected to 



175 



the 8085's TRAP input, forces the execution fo a 
service routine which saves the state of the ma- 
chine in the RAM then issues a backup command. 
The V2 output drops immediately while the 680mF 
capacitor on the V1 input provides enough energy 
to keep the X2201 running for the 10ms needed to 
complete the backup transfer. The low consump- 
tion of the V1 regulator allows the use of a rela- 
tively small capacitor for this function. 

ADDING A WATCHDOG 

By adding a few components and two Schmitt 



trigger gates a watchdog function can be added to 
the L4902 (figure 9). Normally an output port of 
the micro will supply a software-generated pulse at 
least every 10ms. If something has gone wrong in 
the software or hardware and these pulses are 
missing the disable input will be activated after a 
period set by R1 .C1, disabling all the circuitry con- 
nected to the V2 output of the L4902. The disable 
period could be useful to prevent spurious opera- 
tion of motors and solenoids while the control 
processor is malfuntioning. 



Fig. 6 - CMOS RAMs - The L4901 is useful in systems with battery backup CMOS RAMs because the 
reset output can be used to ensure that the RAM chips are disabled to reduce battery drain when the main 
supply ia removed. 




Fig. 7 - NV MEMOR Y nCs - The L4902 is also useful for supplying chips like the SGS M38SH72 single- 
chip micro with NV memory. In this application the reset circuit initiates the RAM-to-shadow transfer. 



O- 



DISABLE 

O 



I 



14902 



X" 



~^ "5V C 



THER = 



V 2 TOOTHERS 

CHIPS |lO/jF 



100nF 1 



M385H72 



RESET 



GND 

"X" 



176 



D*«f ~r? HA P yiJi AM$ ~ The L490Vs res et function also serves in systems using shadow type NV 
HAMs like the X2201 to ensure that the backup transfer is executed correctly. 



ViO p-W . '. 

J=680 
~T" » F 



IN 1 



L«901 

IN2 OUT 2 



CT RESET 

GNO 



T 



"X 



lOyuF 



X2201 



Z> 



~X — " 



ADDRESS DATA 



8085 



Fig. 9 - With a CMOS Schmitt trigger and a few components a watchdog function can be added for 
critical applications. 



O- 



ITT 
I" 



IN 0UT1 



L4902 



RST 



DIS TIM. 

GND 



«Jl 10nF 



^ 



r 

4.7 uF _L 




'DD 



RST pP 



OUTPUT 
PORT 



47nF 

33 nF 



|2'3 A0106 






JUUL 



177 



UC3842 PROVIDES LOW-COST 
CURRENT-MODE CONTROL 



The fundamental challenge of power supply design 
is to simultaneously realize two conflicting objec- 
tives: good electrical performance and low cost. 
The UC3842 is an integrated pulse width modu- 
lator (PWM) designed with both these objectives 
in mind. This IC provides designers an inexpensive 
controller with which they can obtain all the per- 
formance advantages of current-mode operation. 
In addition, the UC3842 is optimized for efficient 
power sequencing of off-line converters and for 
driving increasingly popular POWERMOS. 

This application note gives a functional description 
of the UC3842 and suggests how to incorporate 
the IC into practical power supplies. A review of 
current-mode control and its benefits is included 
and methods of avoiding common pitfalls dis- 



cussed. The final section presents designs of two 
power supplies utilizing UC3842 control. 



CURRENT-MODE CONTROL 

Figure 1 shows the two-loop current-mode control 
system in a typical buck regulator application. A 
clock signal initiates power pulses at a fixed fre- 
quency. The termination of each pulse occurs 
when an analog of the inductor current reaches a 
threshold established by the error signal. In this 
way the error signal actually controls peak induc- 
tor current. This contrasts with conventional 
schemes in which the error signal directly controls 
pulse width without regard to inductor current. 



Fig. 1- Two-loop current-mode control system 




Several performance advantages result from the 
use of current-mode control. First, an input volt- 
age feed-forward characteristic is achieved; i.e., 
the control circuit instantaneously corrects for 
input voltage variations without using up any of 
the error amplifier's dynamic range. Therefore, 
line regulation is excellent and the error amplifier 
can be dedicated to correcting for load variations 
exclusively. 

For converters in which inductor current is con- 
tinuous, controlling peak current is nearly equiv- 
alent to controlling average current. Therefore, 
when such converters employ current-mode con- 
trol, the inductor can be treated as an error-volt- 
age-controlled-current-source for the purposes of 
small-signal analysis. This is illustrated by Figure 
2. The two-pole control-to-output frequency re- 
sponse of these converters is reduced to a single 
pole (filter capacitor in parallel with load) response. 



Fig. 2 



Inductor looks like a current source to 
small signals 



"SEfO- 




VOLTAGE 
CONTROLLED 
CURRENT 
SOURCE 



O«o 



One result is that the error amplifier compensation 
can be designed to yield a stable closed-loop con- 
verter response with greater gain-bandwidth than 
would be possible with pulse-width control, giving 
the supply improved small-signal dynamic response 
to changing loads. A second result is that the error 



amplifier compensation circuit becomes simpler 
and better behaved, as illustrated in Figure 3. Ca- 
pacitor Cj and resistor Rj Z in Figure 3a add a low 
frequency zero which cancels one of the two con- 
trol-to-output poles of non-current-mode con- 
verters. For large-signal load changes, in which 
converter response is limited by inductor slew 
rate, the error amplifier will saturate while the in- 
ductor is catching up with the load. During this 
time, Cj will charge to an abnormal level. When the 
inductor current reaches its required level, the volt- 
age on Cj causes a corresponding error in supply 
output voltage. The recovery time is Rj Z Ci, which 
may be milleseconds. However, the compensation 
network of Figure 3b can be used where current- 
mode control has eliminated the inductor pole. 
Large-signal dynamic response is then greatly im- 
proved due to the absence of Cj. 

Fig. 3 - Required error amplifier compensation for 
continuos inductor current designs using 
(a) Dyty-cycle control and (b) Current- 
mode control. 




Fig. 4 - UC3842 block diagram 




180 



Current limiting is simplified with current-mode 

control. Pulse-by-pulse limiting is, of course, 
inherent in the control scheme. Furthermore, an 
upper limit on the peak current can be established 
by simply clamping the error voltage. Accurate 
current limiting allows optimization of magnetic 
and power semiconductor elements while ensuring 
reliable supply operation. 

Finally, current-mode controlled power stages can 
be operated in parallel with equal current sharing. 
This opens the possibility of a modular approach 
to power supply design. 



FUNCTIONAL DESCRIPTION 

A block diagram of the UC3842 appears in Fig- 
ure 4. This IC will operate from a low impedance 
DC source of 10V to 30V. Operation between 10V 
and 16V requires a start-up bootstrap to a voltage 
greater than 16V in order to overcome the under- 
voltage lockout. V cc is internally clamped to 34V 
for operation from higher voltage current-limited 
sources (l cc < 30mA). 



Under-Voltage Lockout (UVLO) 

This circuit insures that V cc is adequate to make 
the UC3842 fully operational before enabling the 
output stage. Figure 5a shows that the UVLO turn- 
on and turn-off thresholds are fixed internally at 
16V and 10V respectively. The 6V hysteresis 
prevents V C c oscillations during power sequencing. 
Figure 5b shows supply current requirements. 
Start-up current is less than 1mA for efficient 
bootstrapping from the rectified input of an off- 
line converter, as illustrated by Figure 6. During 
normal circuit operation, V cc is developed from 
auxiliary winding Waux with Di and Cin. At 
start-up, however, Cin must be charged to 16V 
through Rin. With a start-up current of 1mA, Rin 
can be as large as 100kn and still charge Cin when 
Vac = 9° v Rlv1s ( |ow line). Power dissipation in 
R|N would then be less than 350mW even under 
high line (Vac = 130V RMS) conditions. 

During UVLO, the UC3842 output driver is biased 
to a high impedance state. However, leakage cur- 
rents (up to 10^A), if not shunted to ground, could 
pull highthegateof a POWERMOS. A 100kn shunt, 
as showing in Figure 6, will hold the gate voltage 
below 1 V. 



Fig. 5 (a) - Under-voltage lockout and (b) supply current requirements. 



ON/OFF COMMAND cc 

TO REST OF IC * 



V 0N = 16V 

V OF =10V 



>k 



(a) 



(b) 



Fig. 6 - Providing power to the UC3842 




UC3842 

OUT 




181 



Oscillator 

The UC3842 oscillator is programmed as shown in 
Figure 7a. Oscillator timing capacitor Cy is charged 
from Vref (5V) through Ry, and discharged by 
an internal current source. Charge and discharge 
times are given by: 

t c * 0.55 Ry Ct 



t □ r- I 0.0063 Ry - 2.7 

td « Ry Cy «n ! 

\ 0.0063 Ry-4.0 
1 



frequency, then, is: f = - 

tc + td 

For Ry > 5kf2, td is small compared to tc, and: 
1 1.8 



During the discharge time, the internal clock signal 
blanks the output to the low state. Therefore, td 
limits maximum duty cycle (DmaxI to: 



J MAX 



tc + td 



1 



td 

T 



0.55 Ry Cy Ry Cy 



where: t = 1/f = switching period. 

The timing capacitor discharge current is not 
tightly controlled, so td may vary somewhat over 
temperature and from unit to unit. Therefore, 
when very precise duty cycle limiting is required, 
the circuit of Figure 7b is recommended. 

One or more UC3842 oscillators can be synchron- 
ized to an external clock as shown in Figure 8. 
Noise immunity is enhanced if the free-running 
oscillator frequency (f = 1/(t c + td)) isprogrammed 
to be ~ 20% less than the clock frequency. 



Fig. 7 (a) - Oscillator timing connections and (b) circuit for limiting duty cycle. 



V REF W^ ~1 




T 



(a) 




CNTL THRESH 
GND 



Dmax 



ItH+tL.) 



tH =0.693 (Ra + RbIC 
t(_ = 0.693 RbC 



Fig. 8- Synchronization to an external clock 





0,0 I WF 

11 


! ■ 

u 

I)™ 


V REF 

UC3842 


EXTERNAL 
CLOCK 

JUU 


R T -C, 

GND 


II 













Error Amplifier 

The error amplifier (El A) configuration is shown in 
Figure 9. The non-inverting input is not brought 
out to a pin, but is internally biased to 2.5V ± 2%. 
The E/A output is available at pin 1 for external 
compensation, allowing the user to control the 
converter's closed-loop frequency response. 

Figure 10a shows an E/A compensation circuit 
suitable for stabilizing any current-mode con- 
trolled topology except for flyback and boost 
converters operating with continuous inductor 
current. The feedback components add a pole to 
the loop transfer function at f p = 1 /2rr Rf Cf. Rf 
and Cf are chosen so that this pole cancels the zero 
of the output filter capacitor ESR in the power 
circuit. Rj and Rf fix the low-frequency gain. They 
are chosen to provide as much gain as possible 
while still allowing the pole formed by the output 
filter capacitor and load to roll off the loop gain to 



182 



unity (OdB) at f « fswitching/4. This technique 
insures converter stability while providing good 
dynamic response. 

Continuous-inductor-current boost and flyback 
converters each have a right-half-plane zero in their 
transfer function. An additional compensation pole 
is needed to roll off loop gain at a frequency less 
than that of the RHP zero. Bp and C p in the cir- 
cuit of Figure 10b provide this pole. 

The E/A output will source 0.5mA and sink 2mA. 
A lower limit for Rf is given by: 

„ V E/A OUT(MAX)- 2.5V _ 6V - 2J5V _ -,._ 

H f(MIN) * =-= : — ~ : /Kli 



0.5mA 



0.5mA 



E/A input bias current (2/iA max) flows through 
Ri, resulting in a DC error in output voltage (V ) 
given by: 

AV (max) = (2/iA) Ri 

It is therefore desirable to keep the value of Rj as 
low as possible. 

Figure 11 shows the open-loop frequency response 
of the UC3842 E/A. The gain represent an upper 
limit on the gain of the compensated E/A. Phase 
lag increases rapidly as frequency exceeds 1MHz 
due to second-order poles at ~ 10MHz and above. 



Fig. 9 - UC3842 error amplifier 




Fig. 10 - la) Error amplifier compensation addi- Fig. 1 1 - Error amplifier open-loop frequency 



(a) 



lb) 



tion pole and lb) needed for continuous 
inductor-current boost ad flyback. 





I 1 



response 




Current Sensing and Limiting 

The UC3842 current sense input is configured as 
shown in Figure 12. Current-to-voltage conversion 
is done externally with ground-referenced resistor 
Rs. Under normal operation the peak voltage 
across Rs is controlled by the E/A according to 



183 



the following relation: 



'R s (Pk) 



V C - 1.4V 



where: Vq = controt voltage = E/A output voltage. 

Rs can be connected to the power circuit directly 
or through a current transformer, as Figure 13 il- 
lustrates. While a direct connection is simpler, a 
transformer can reduce power dissipation in Rs, 
reduce errors caused by the base current, and pro- 
vide level shifting to eliminate the restraint of 
ground-referenced sensing. The relation between 
Vc and peak current in the power stage is given by : 



/V Rs (pk)\ N / 

1(pk) = N (_!_)=( 



V r - 1.4V 



where: N ; 

For purposes of small-signal analysis, the control- 



current sense transformer turns ratio. 
1 when transformer not used. 



to-sensed-current gain is: 
i(pk) _ N 



V c 3R S 

When sensing current in series with the power 
transistor, as shown in Figure 13, current wave- 
form will often have a large spike at its leading 
edge. This is due to rectifier recovery and/or inter- 
winding capacitance in the power transformer. If 
unattenuated, this transient can prematurely 
terminate the output pulse. As shown, a simple 
RC filter is usually adequate to suppress this spike. 
The RC time constant should be approximately 
equal to the current spike duration (usually a few 
hundred nanoseconds). 

The inverting input to the UC3842 current-sense 
comparator is internally clamped to 1V (Figure 
12). Current limiting occurs if the voltage at pin 3 
reaches this threshold value, i.e. the current limit 
is defined by: 

N • 1V 



IMAX 



Fig. 12- Current sensing 




RRENT 
NSE 
COMPARATOR 



Fig. 13- Transformer-coupled current sensing 




uc 

3842 



Totem-Pole Output 

The UC3842 has a single totem-pole output. The 
output transistors can be operated to ± 1A peak 
current and ± 200mA average current. The peak 
current is self-limiting, so no series current-limiting 
resistor is needed when driving a power MOS gate. 



Cross-conduction between the output transistors 
is minimal, as Figure 14 shows. The average added 
power due to cross-conduction with V; = 30V is 
only 80mW at 200kHz. 

Fig. 14 - Output cross-conduction 



| 20V/div~B^B| 



200mA/div. 



200ns/div. 



184 



Figures 15-17 show suggested circuits for driving 
POWERMOS and bipolar transistors with the 
UC3842 output. The simple curcuit of Figure 15 
can be used when the control IC is not electrically 
isolated from the power MOS. Series resistor Rj 
provides damping for a parasitic tank circuit for- 
med by the power MOS input capacitance and any 
series wiring inductance. Resistor R2 shunts output 
leakage currents (10,uA maximum) to ground when 
the under-voltage lockout is active. Figure 16 
shows an isolated power MOS drive circuit which is 
appropriate when the drive signal must be level- 
shifted or transmitted acrossan isolation boundary. 
Bipolar transistors can be driven effectively with 
the circuit of Figure 17. Resistors Rj and R2 fix 
the on-state base current. Capacitor Ci provides a 
negative base current pulse to remove stored charge 
at turn-off. 

Fig. 15- Direct POWERMOS drive 




Fig. 16- Isolated POWERMOS drive 

18 to30V 

9 

|? FERROXCUBE 

1811 
100-3C8 




PWM Latch 

This flip-flop, shown in Figure 4, ensures that only 
a single pulse appears at the UC3842 output in any 
one oscillator period. Excessive power transistor 
dissipation and potential saturation of magnetic 
elements are thereby averted. 



Shutdown Techniques 

Shutdown of the UC3842 can be accomplished by 
two methods; either raise pin 3 above 1V or pull 
pin 1 below 1V. Either method causes the output 
of the PWM comparator to be high (refer to block 
diagram, Figure 4). The PWM latch is reset domi- 
nant so that the output will remain low until the 
first clock pulse following removal of the shut- 
down signal at pin 1 or pin 3. As shown in Figure 
18, an externally latched shutdown can be ac- 
complished by adding an SCR which will be reset 
by cycling Vcc below the lower under-voltage 
lockout threshold (10V). At this point all internal 
bias is removed, allowing the SCR to reset. 



Fig. 18- 



(a) 



Shutdown achieved by 
a) Pulling pin 3 high 
bl Pulling pin 1 Low 



8) V REF 



4.7Kn I 

SHUTDOWN (.5?) M 




UC38« 



3J 'SENSE 



TO CURRENT 
" SENSE RESISTOR 



(b) 



hutoownJ^) 



Fig. 17- Bipolar drive with negative turn-off bias 

12to30v 




AVOIDING COMMON PITFALLS 

Current-mode controlled converters can exhibit 
performance peculiarities under certain operating 
conditions. This section explains these situations 
and how to correct them when using the UC3842. 



Slope Compensation Prevents 
Instabilities 

It is well documented that current-mode controlled 
converters can exhibit subharmonic oscillations 



185 



when operated at duty cycles greater than 50% . Fig. 19 

Fortunately, a simple technique (usually requiring 
only a single resistor to implement) exists which 
corrects this problem and at the same time im- 
proves converter performance in other respects. 
This "slope compensation" technique is described 
in detail in Reference 6. It should be noted that 
"duty cycle" here refers to output pulse width 
divided by oscillator period, even in push-pull 
designs where the transformer period is twice that 
of the oscillator. Therefore, push-pull circuits will 
almost always require slope compensation to 
prevent subharmonic oscillation. 

Figure 19 illustrates the slope compensation 
technique. In Figure 19a the uncompensated con- 
trol voltage and current sense waveforms are shown 
as a reference. Current is often sensed in series with 
the switching transistor for buck-derived top- 
ologies. In this case, the current sense signal does 
not track the decaying inductor current when the 
transistor is off, so dashed lines indicate this in- 
ductor current. The negative inductor current 
slope is fixed by the values of output voltage (V ) 
and inductance (L): 



-Vf -Vq _ -IV F + V ) 



di L = . Vl 

dt L 



where: Vf = forward voltage drop across the free- 
wheeling diode. The actual slope (1T12I of the 
dashed lines in Figure 19a is given by: 



Slope compensation waveforms: 

a) No Comp. 

b) Comp. added to control voltage 

c) Comp. added to curren t sense 




CURRENT SENSE 
(TRAN5IST0R CURRENT) 



CURRENT SENSE 
(TRNSISTOR CURRENT) 



CURRENT 
SENSE 



TRANSISTOR 
CURRENT 



rri2 



Rs 



di|_ 
dt 



-R 5 (V F + Vq) 

NL 



where: Rs and N are defined as the "Current 
Sensing" section of this paper. 

In Figure 19b, a sawtooth voltage with slope m has 
been added to the control signal. The sawtooth is 
synchronized with the PWM clock, and practice is 
most easily derived from the control chip oscillator 
as shown in Figure 20a. The sawtooth slope in Fi- 
gure 19b is m = IT12/2 This particular slope value is 
significant in that it yields "perfect" current-mode 
control; i.e. with m2/2 the average inductor cur- 
rent follows the control signal so that, in the small- 
signal analysis, the inductor acts as a controlled cur- 
rent source. All current-mode controlled converters 
having continuous inductor current therefore 
benefit from this amount of slope compensation, 
whether or not they operate above 50% duty. 

More slope is needed to prevent subharmonic 
oscillations at high duty cycles. With slope m = rri2, 
such oscillations will not occur if the error ampli- 
fier gain (Av(e/A)) at half the switching fre- 
quency (fs/2) is kept below a threshold value 
(Reference 6): 



A v (E/A) 



where: Co 



m = nri2 
f = f s /2 



= sum of filter and load capacitance 
= 1/f s 



Slope compensation can also improve the noise 
immunity of a current-mode controlled supply. 
When the inductor ripple current is small com- 
pared to the average current (as in Figure 19a), 
a small amount of noise on the current sense or 
control signals can cause a large pulse-width jitter. 
The magnitude of this jitter varies inversely with 
the difference in slope of the two signals. By adding 
slope as in Figure 19b, the jitter is reduced. In 
noisy environments it is sometimes necessary to 
add slope m > 1112 in order to correct this problem. 
However, as m increases beyond m = m2/2, 
the circuit becomes less perfectly current con- 
trolled. A complex trade-off is then required; for 
very noisy circuits the optimum amount of slope 
compensation is best found empirically. 
Once the required slope is determined, the value 
of Rslope in Figure 20a can be calculated: 



^ Vramp 



A V (E/A) - - 



0.7V , 

/2 ( 



FISLOPE 



3m t 
1.4 



(ZFlfs 



Rslope \ 



2.1 ■ m 



ZfUs 



Z F |fs 



where: Zp| f 5 is the E/A feedback impedance at 
the switching frequency. 



For m 



Atramp 



□ . , / R s (Vf + Vn \ -, i , 

"SLOPE = 1.7t y Z F | f s 

NL / 



186 



Note that in order for the error amplifier to ac- 
curately replicate the ramp, Zp must be constant 
over the frequency range f s to at least 3f s . 

In order to eliminate this last constraint, an alterna- 
tive method of slope compensation is shown in 
Figures 19c and 20b. Here the artificial slope is 
added to the current sense waveform rather than 
subtracted from the control signal. The magnitude 
of the added slope still relates to the downslope of 
inductor current as described above. The require- 
ment for RsLOPE is now: 



Rf 



aVramp / 



At RAMP \ Rf + RSLOPE 



0.7 / Rf 

t/2 \ R, + RsLOPE 



"'SLOPE 



1.4Rf 



- -Rf 



Rf 



\ mi 



For m = 1H2: 

R □ / 1.4NL ,\ 

n<;i nop- = Rf ( 1 I 

\R S (V F + Voir / 



^SLOPE 



R SLOPE loads the UC3842 Rt/Ct terminal so as 
to cause a decrease in oscillator frequency. If 
R SLOPE >> Rt then the frequency can be cor- 
rected by decreasing Rt slightly. However, with 
R SLOPE < 5Rt the linearity of the ramp degrades 
noticeably, causing over-compensation of the 
supply at low duty cycles. This can be avoided by 
driving Rslope with an emitter-follower as shown 
in Figure 21. 



Fig. 20 - Slope compensation added (a) to control signal or lb) to current sense waveform 



sT^r^ 




(b) 









V REF 








R T 










r t' c t 

FROM E'A 




\ "SENSE. 


= c T 


■ 


~ 


? 




L/N , j R f 








C0MPj> 


u« s 


I' 




UC3 


8« 



187 



Fig. 21 ■ 



Emitter-follower minimizes load at 
RT/CT terminal. 




Noise 

As mentioned earlier, noise on the current sense or 
control signals can cause significant pulse-width 
jitter, particularly with continuous-inductor-current 
designs. While slope compensation helps alleviate 
this problem, a better solution is to minimize the 
amount of noise. In general, noise immunity im- 
proves as impedance decrease at critical points in 
a circuit. 

One such point for a switching supply is the 
ground line. Small wiring inductances between 
various ground points on a PC board can support 
common-mode noise with sufficient amplitude to 
interfere with correct operation of the modulating 
IC. A copper ground plane and separate return 
lines for high-current paths greatly reduce common- 
mode noise. Note that the UC3842 has a single 



ground pin. High sink currents in the output 
therefore cannot be returned separately. 

Ceramic bypass capacitors (0.1/liF) from V, and 
Vref to ground will provide low-impedance paths 
for high frequency transients at those points. The 
input to the error amplifier, however, is a high- 
impedance point which cannot be bypassed without 
affecting the dynamic response of the power 
supply. Therefore, care should be taken to lay out 
the board in such a way that the feedback path is 
far removed from noise generating components 
such as the power transistor(s). 

Figure 22a illustrates another common noise-in- 
duced problem. When the power transistor turns 
off, a noise spike is coupled to the oscillator Ry/ 
Ct terminal. At high duty cycles the voltage at 
Ry/Cy is approaching its threshold level (~2.7V, 
established by the internal oscillator circuit) when 
this spike occurs. A spike of sufficient amplitude 
will prematurely trip the oscillator as shown by 
the dashed lines. In order to minimize the noise 
spike, choose Cy as large as possible, remembering 
that deadtime increases with Cy. It is recommended 
that Cy never be less than ~1000pF. Often the 
noise which causes this problem is caused by the 
output (pin 6) being pulled below ground at turn- 
off by external parasitics. This is particularly true 
when driving POWERMOS. A diode clamp from 
ground to pin 6 will prevent such output noise 
from feeding to the oscillator. If these measures 
fail to correct the problem, the oscillator fre- 
quency can always be stabilized with an external 
clock. Using the circuit of Figure 8 results in an 
Rt/Ct waveform like that of Figure 22b. Here 
the oscillator is much more immune to noise 
because the ramp voltage never closely approaches 
the internal threshold. 



Fig. 22 - a) Noise on pin 4 can cause oscillator to pre-trigger 

b) With external sync, noise does not approach threshold level 



INTERNAL 
THRESHOLD 




(a) 



(b) 



Maximum Operating Frequency 

Since output deadtime varies directly with Cy, the 
restraint on minimum Cy (1000pF) mentioned 
above results in a minimum deadtime capability for 
the UC3842. This minimum deadtime varies with 
Ry and therefore with frequency, as shown in Fi- 
gure 23. Above 100kHz, the deadtime significantly 



reduces the maximum duty cycle obtainable at the 
UC3842 output (also show in Figure 23). Circuits 
not requiring large duty cycles, such as the forward 
converter and flyback topologies, could operate 
as high as 500kHz. Operation at higher frequencies 
is not recommended because the deadtime be- 
come less predictable. 



1? 



The speed of the UC3842 current sense section 
poses an additional constraint on maximum ope- 
rating frequency. A maximum current sense delay 
of 400ns represents 10% of the switching period at 
250kHz and 20% at 500kHz. Magnetic components 
must not saturate as the current continues to rise 
during this delay period, and power semiconduc- 
tors must be chosen to handle the resulting peak 
currents. In short, above ~ 250kHz, may of the 
advantages of higher-frequency operation are lost. 



CIRCUIT EXAMPLES 
1. Off-Line Flyback 

Figure 24 shows a 25W multiple-output off-line 
flyback regulator controlled with the UC3842. 
This regulator is low in cost because it uses only 
two magnetic elements, a primary-side voltage 
sensing technique, and an inexpensive control 
circuit. Specifications are listed below. 



SPECIFICATIONS: 

Fig. 23 - Deadtime and maximum obtainable 

duty-cycle vs. frequency with minimum Input Voltage 
recommended Ct. 



95 VAC to 130 VAC 
(50Hz/60Hz) 



Irs) 
700 
650 
600 
550 
500 
450 
£00 
350 
300 







b 




C T = 1000pF 




















max td ^-' v. * " "v^y ""N^. 




DUTY@MAX td / " S *S V ^Ns^ ^V 










| N^ 


70 


MIN td 





Output Voltage: 



Line Isolation: 
Switching Frequency: 
Efficiency (s> full load: 



A. +5V, 5%: 1A to 4A load 
Ripple voltage: 50m V 
P-P Max. 

B. + 12V, 3% : 0.1A to 
0.3A load 

Ripple voltage: 100mV 
P-P Max 

C. -12V, 3% 0.1 A to 0.3A 
load 

Ripple voltage: 100mV 
P-P Max 

3750V 

40kHz 

70% 



Fig. 24 - 25W off-line flyback regulator 

i.7AlW 




I 



L Hb 



1 



| I 56Kft 



J. 



IN 3613 



2CV 




2^fl SGSP3 6 9 



1 



T 



i?opf oas a 



DC OUT 5V 2to5A 



T!;COILCRAFT E-4140-B 
PRIMARY-97TURNS 

SINGLE AWG2A 
SEC0NDARY-4TURNS 

U PARALLEL AWG22 
CONTROL-9 TURNS 

3 PARALLEL AWG28 



ISOLATION 
BOUNDARY 



189 



A25W OFF-LINE 
FLYBACK SWITCHING REGULATOR 



INTRODUCTION 

This note describes a low cost switching power 
supply for applications requiring multiple output 
voltages, e.g. personal computers, instruments, 
etc. . . The discontinuous mode flyback regulator 
used in this application provides good voltage 
tracking between outputs, which allows the use of 
primary side voltage sensing. This sensing tech- 
nique reduces costs by eliminating the need for an 
isolated secondary feedback loop. 

The low cost, (8pin) UC1842 current mode control 
chip employed in this power supply provides per- 
formance advantages such as: 

1) Fast transient response 

2) Pulse by pulse current limiting 

3) Stable operation 

To simplify drive circuit requirements, a TO-220 
power MOS SGSP369 is utilized for the power 
switch. This switch is driven directly from the 
output of the control chip. 



Power Supply Specifications 

1. Input voltage: 95VAC to 130VAC (50Hz/ 
60Hz) 

2. Output voltage: 

A. +5V,± 5%: 1A to 4A load 
Ripple voltage: 50mV P-P Max 

B. +12V,+ 3%: 0.1A to 0.3A load 
Ripple voltage: 100mV P-P Max 

C. -12V, ± 3%: 0.1A to 0.3A load 
Ripple voltage: 100mV P-P Max. 

3. Line Isolation: 3750V 

4. Switching Frequency: 40KHz 

5. Efficiency <s) Full Load: 70% 



Basic Circuit Operation 

The 117VAC input line voltage is rectified and 



smoothed to provide DC operating voltage for the 
circuit. When power is initially applied to the cir- 
cuit, capacitor C2 charges through R2. When the 
voltage across C2 reaches a level of 16V the output 
of IC1 is enabled, turning on power MOS Q1. 

During the on time of Q1 , energy is stored in the 
air gap of transformer (inductor) T1. At this time 
the polarity of the output windings is such that all 
output rectifiers are reverse biased and no energy is 
transferred. Primary current is sensed by a resistor, 
R10, and compared to a fixed 1V reference inside 
IC1. When this level is reached, Q1 is turned off 
and the polarity of all transformer windings re- 
verses, forward biasing the output rectifiers. All 
the energy stored is now transferred to the output 
capacitors. Many cycles of this store/release action 
are needed to charge the outputs to their respective 
voltages. Note that C2 must have enough energy 
stored initially to keep the control circuitry ope- 
rating until C4 is charged to a level of approximately 
13V. The voltage across C4 is fed through a voltage 
divider to the error amplifier (pin 2) and compared 
to an internal 2.5V reference. 

Energy stored in the leakage inductance of T1 
causes a voltage spike which will be added to the 
normal reset voltage across T1 when Q1 turns off. 
The clamp consisting of D4, C9 and R12 limits 
this voltage excursion from exceeding the BVDSS 
rating of Q1. In addition, a turn-off snubber made 
up of D5, C8 and R11 keeps power dissipation in 
Q1 low by delaying the voltage rise until drain cur- 
rent has decreased from its peak value. This snubber 
also damps out any ringing which may occur due 
to parasitics. 

Less than 3.5% line and load regulation is achieved 
by loading the output of the control winding Nc, 
with R9. This resistor dissipates the leakage energy 
associated with this winding. Note that R9 must 
be isolated from R2 with diode D2, otherwise C2 
could not charge to the 16V necessary for initial 
start-up. 

A small filter inductor in the 5V secondary is added 
to reduce output ripple voltage to less than 50mV. 
This inductor also attenuates any high frequency 
noise. 



191 



Fig. 1 - 25W off-line flyback regulator 




Notes 1 - All resistors are 1/4W unless noted 

2 - See appendix for construction details 

3 - L1 = Ferroxcube 204T50-3C8 (Toroid), N° turns: 4, Wire Gauge: 1mm. (18AWG) 



Fig. 2 - Block diagram: UC1842 current mode controller 




192 



TYPICAL SWITCHING WAVEFORMS 



Ton - Drive waveforms 



T ff - Drive waveforms 




Upper trace: Qi - Gate to source voltage 
Lower trace: Qi - Gate current 




Upper trace: Qi - Drain to source voltage 
Lower trace: Primary current - Id 



Upper trace: +5V charging current 
Lower trace: +5V output ripple voltage 



193 



PERFORMANCE DATA 



CONDITIONS 


5V out 


12V out 


-12V out 


Low Line (95V ACl 

± 12 @ 100mA +5V @> 1 .0A 
4.0A 

± 12 @ 300mA +5V @ 1.0A 
4.0A 


5.211 
4.854 

5.199 
4.950 


12.05 
12.19 

11.73 
11.68 


-12.01 
-12.14 

-11.69 
-11.63 


Nominal Line (120VAC) 

± 12 @ 100mA +5V @ 1.0A 
4.0A 

± 12 @ 300mA +5V <s> 1.0A 
4.0A 


5.220 
4.875 

5.208 
4.906 


12.07 
12.23 

11.73 
11.67 


-12.03 
-12.18 

-11.68 
-11.62 


High Line (130VAC) 

± 12 <s> 100mA +5V @ 1 ,0A 
4.0A 

± 12V @ 300mA + 5V @ 1.0A 
4.0A 


5.207 
4.855 

5.200 
4.902 


12.06 
12.21 

11.71 
11.66 


-12.02 
-12.15 

-11.67 
11.61 


Overall Line and Load Regulation 


± 3.5% 


± 2.3% 


± 2.4% 



APPENDIX POWER TRANSFORMER -Tl 



Core: Ferroxcube EC-35/3C8 

Gap: 0.25mm. in each outer I 



NOTE : For reduced EMI put gap in center leg only. 
Use 0.5mm. 



o — ' 



— o 






!- N„ = 9 



TRANSFORMER CONSTRUCTION 



CONTROL WINDING 
NzlO,AWG30{0.25mm) -- 

2 IN PARALLEL 

+5V0UT, Nri.AWG 26,(0.tmm)_ 
6 IN PARALLEL 



2LAYERS 3M MYLAR TAPE 



:TYYYYXX 



5 



fYYYYYYYl 



BOBBIN-35PCB1 



2 LAYERS, 3M MYLAR TAPE 



±12V WINDINGS N = 9, AWG30(Q.25m 
2 WIRES IN PARALLEL, 
BIFILAR WOUND 

PRIMARY N = £S, AWG 26(0.4mm.l 



194 



APPLYING THE UC1840 

TO PROVIDE TOTAL CONTROL FOR 

LOW-COST, PRIMARY-REFERENCED 

SWITCHING POWER SYSTEMS 



INTRODUCTION 

There are many potential approaches to be con- 
sidered in switch mode power supply design; 
however, the contradictory requirements of mini- 
mum cost and compatibility with ever more de- 
manding line isolation specifications make primary 
control very attractive. Application of the UC1840 
as a primary-side, off-line controller presents an 



extremely cost-effective approach to supplying 
isolated power from a widely varying input line 
while maintaining a high degree of efficiency. 

Primary control means referencing all of the con- 
trol electronics along with the power switching 
device on the input line side of an isolation trans- 
former. An obvious advantage to this approach is 
the simplified interface between the control and 



Fig. 1 - The overall block diagram of the UC1840, an integrated circuit optimized for primary-side con- 
trol of off-line switching power supplies. 




(I6) 50 V REF 



3-OV flEF- 
EXT. STOP 0- ■ 



0V SENSE (3> 



195 



power switch. This eliminates many of the transi- 
tions across the isolation boundary which signifi- 
cantly increase the cost of the magnetics portion of 
the power supply's budget. 

There are two disadvantages to primary control: 
(1) operating or at least starting, the control elec- 
tronics from the line voltage (typically 300 VDC), 
and (2) providing adequate regulation (which re- 
quires feedback from the secondary across the iso- 
lation boundary). The capability of the UC1840 
Control IC to solve these problems while providing 
all of the regulating, sequencing, monitoring, and 
protection functions referenced to the primary 
side, makes this device very attractive. 



(5) Complete under-voltage, over-voltage, and 
over-current protection including program- 
mable shutdown and restart. 

(6) A high-current, single-ended PWM output 
optimized for fast turn-off of an external 
power switch. 

(7) Logic control for pulse-commandable or DC 
power sequencing. 

For an understanding of how these individual 
blocks work together in a typical, medium-power 
flyback power supply, reference should be made 
to Figure 2 and the functional description which 
follows. 



THE UC1840 CONTROLLER 

The overall block diagram of the UC1840, shown 
in Figure 1, includes the following features: 

(1) Fixed-frequency operation set by user- 
selected components. 

(2) A variable-slope ramp generator for constant 
volt-second operation providing open-loop 
line regulation and minimizing, or in some 
cases even eliminating, the need for feedback 
control. 

(3) A drive switch for low current start-up off 
the high-voltage line. 

(4) A precision reference generator with internal 
over-voltage protection. 



UC1840 FUNCTIONAL DESCRIPTION 

Power sequencing 

A simplified schematic of the UC1840's internal 
power turn-on circuitry is shown in Figure 3. The 
key elements of this function are: (1) the Driver 
Bias Switch, Q3, which keeps the loading on the 
control voltage line, V c , to a minimum during start 
up; (2) the Under-voltage Comparator which also 
functions as a Start Threshold Detector with pro- 
grammable hysteresis; and (3)an auxiliary, primary- 
referenced, low-voltage winding on the main 
power transformer which provides normal control 
power after turn-on. The sequence of events is as 
follows: 



Fig. 2 - A fully protected, isolated flyback power supply can be implemented with the UC1840, a high- 
voltage power switch, the transformer, and a small handful of passive components. 




«n 



DC INPUT LINE 



CONTROL VOLTAGE 



VREF 



" fV IN -f V REF OUT 



RlH ^RS V RE 

) 1 



R3| ! 

STOP ^^ 



PREC 
REE 



RAMP 
GEN 




™£<i.___ 



[-\ UC1840 __»^1_ 

|o>> <^_ 



REMOTE 
START/ 
STOP 



SLOW 
START 



"X~ 

196 




Fig. 3 - The UC1840's start circuitry requires low starting current from the DC input line with normal 
operating current supplied from a low-voltage feedback winding on the power transformer. 



NTRC VOLTAGE V.' 



tLORACK v 



R2 | 



' CvhJs'ewsis 



- L. 



.UV=AUL-| 



"SLC* + ' 



(2) 



While the control voltage, V c , is low enough 
so that the voltage on pin 2 is less than 3V, 
the Start/UV Comparator does the following: 

(a) A 200mA hysteresis current is flowing 
into pin 2 through Q1 causing an added 
drop across R2. 

(b) The drive switch is holding the Driver Bias 
transistor, Q3, OFF. This insures that the 
only current required through R1 is the 
start-up current of the UC1840, plus ex- 
ternal dividers (R2, R3, R s , etc.). 

(c) The Slow Turn-on transistor, Q2, is ON, 
holding pin 8 and Cs low. 

(d)The Start Latch keeps the under-voltage 
signal from being defined as a fault. 

The start level is defined by: 



V c (start)= 3 ( 



R2 + R3 
R3 



) + 0.2 R2. 



When V c rises to this level, the Start/UV. 
Comparator then does the following: 
(a) Turns off Q1 , eliminating the 200mA 
hysteresis current. This allows the voltage 
on V c to drop before reaching the under- 
voltage fault level defined by: 



V c (U.V. fault)= 3 ( 



R2 + R3 



R3 



(b)Sets the Start Latch to monitor for an 
under-voltage fault. 

(c) Activates Q3 providing Driver Bias to the 
power switch, pulling the added current 
out of C| N . 

(d) Turns off Q2 allowing for programmed 
slow turn-on defined by R s and Cs- 



(3) A normal start-up occurs with the control 
voltage, V c , following the path shown in 
Figure 4. If the power supply does not start, 
V c will fall to an under-voltage fault which 
will then either initiate a restart attempt or 
hold the power switch off, depending upon 
the status of the Reset terminal as defined 
under Fault Sequencing. If start-up does 
not occur because of some fault in the Driver 
Bias line, V c will continue to rise until 
the 40V zener across the reference circuit 
conducts. This will then clamp V c to that 
level, protecting the control chip. 

After start-up occurs, current will continue to flow 
in R1 providing a power loss of: 

(V|ine-V c ) 2 



Pd = 



R1 



Fig. 4 - 



Under a normal turn-on, the supply voltage 
to the UC1840, V c , would rise lightly 
loaded to the start level, fall under the 
turn-on load, and then regulate at some 
intermediate level. 




197 



If this loss is objectionable, it can be reduced more 
than an order of magnitude by the addition of a 
two-transistor switch shown in Figure 5. In this 
circuit, Q1 is initially driven on by current through 
R2. When the feedback winding starts to conduct 
through D1 , however, Q2 turns on leaving only R2 
conducting from the input line. 

Fig. 5 - The addition of Q1 and Q2 can eliminate 
the steady-state current through R1 after 
turn-on. Q2 is selected to pass all control 
current through its base-emitter junction. 



DC INPUT LINE 




D1. . POWER TRANSFORMER 



Slow turn-on circuit 

The PWM comparator input connected to pin 8 
accommodates several programming functions, 
shown in Figure 6. Since this comparator will only 
follow the lowest positive input, holding pin 8 low 
will effectively eliminate a PWM signal, regardless 
of the status of the Error Amplifier output. Prior 
to turn-on, and at all times when a fault has been 
sensed, Q1 is ON, holding pin 8 low. 



Fig. 6 - Pin 8 on the L/C 1840 can be used for both 
slow turn-on and duty-cycle limiting as 
well as a PWM shutdown port. 



5V ret OR 

DC INPUT LINE 




When Q1 turns off, allowing pin 8 to rise with a 
controlled rate will cause the output pulses to in- 
crease from zero to nominal widths at the same 
rate. This is accomplished by the addition of C s 

l - _l : „ „..~u — D *~ +u« CM 



such as R<=, to the 5V 



and a charging source, 
reference. 

Note that where starting energy is stored in an 
input capacitor, the time for PWM turn-on must be 
less than the time required for the added Driver 
Bias load current to discharge the input capacitor 
to the under-voltage fault level. In other words, 
referring back to Figure 4, the slow turn-on must 
be faster than the time required for V c to fall from 
level B to level E. 

Another function of pin 8 is to establish a maxi- 
mum duty cycle limit. This is achieved by clamping 
the voltage on pin 8 with a divider formed by 
adding R DC to ground. If R s is taken to the 5V ref- 
erence, the clamp voltage will be fixed, which is 
desirable if the ramp slope is also fixed. If the ramp 
slope is varied with the input line — for constant 
volt-second operation — then the clamp voltage on 
pin 8 must also vary. This is readily accomplished 



Fig. 7 - The pulse-width modulator within the UC1840 separates the ramp function from the fixed- 
frequency oscillator. 



DC INPUT LINE 




198 



by connecting R s to the DC input line. The divider 
voltage: 

'Pin 8 = <— — r£ > V DC input 



V c 



Re + R 



DC 



should be equal to the ramp voltage level that 
yields the desired maximum duty cycle, at the 
same DC input level. 



Ramp generator 

The ramp generator function of the UC1840 is 
shown in simplified form in Figure 9. 



Fig. 9- Current mirrors Q1-Q4 are used to make 
the ramp charging current / 2 , linearly 
proportional to the DC input line. 



PWM control 

Pulse-Width Modulation within the UC1840 con- 
sists of the blocks shown in Figure 7. This architec- 
ture, with the possible exception of the separation 
between the time-base and ramp functions, is 
fairly conventional. It is described in greater detail 
in the paragraphs which follow. 



Oscillator 

A constant clock frequency is established by con- 
necting R T from pin 9 to the 5V reference and Cj 
from pin 9 to ground. The frequency is approxi- 
mated by: 




f 



Ri 



where the value of R T can range from 1 kn to 
100Kn and C T from 300pF to O.ljuF. The best 
temperature coefficients occur with C T in the 
range of 1000 to 3000 pF. Although the clock out- 
put pulse is not available external to the UC1840, 
synchronization to an external clock can still be 
accomplished with the circuit of Figure 8, where 
R1 and C1 are selected to provide a 0.5V, 200 ns 
pulse across the 51 £1 resistor, and R T and C T 
define a frequency slightly lower than the synch- 
ronizing source. 



Fig. 8 - 



Synchronization to an external time base 
can be accomplished by adding a 5in 
resistor in series with Cy. 




To achieve minimum start-up current, the oscilla- 
tor is not activated until the input voltage is high 
enough to give a start command to the drive 
switch. 



The NPN and PIMP current mirrors provide a charg- 
ing current to Cr of: 

. _ . V|ine-0-7V V line 

'2 _ '1 



>R 



R F 



The current mirrors are useful over a current range 
of 1,uA to 1mA, but optimum tracking occurs 
between 30^A and 300/u.A. Since the voltage 
across Q1 is very small, \2 accurately represents the 
input line voltage. The ramp slope, therefore, is: 



dv 
dt 



Rt 



The peak voltage across Cr is clamped to approxi- 
mately 4.2V while the valley, or low voltage, is 
determined by the on-voltage of the discharge net- 
work, D1 and Q5. This is typically 0.7V. 

If line sensing is not required, R R should be con- 
nected to the 5V reference for constant ramp slope. 



Error amplifier 

This is a voltage-mode operational amplifier with 
an uncommitted NPN differential input stage and 
an output configuration as shown in Figure 10. 

The 1KJ) output resistor, R , is used both for 
short circuit protection and to limit the peak out- 
put voltage to less than 4.0V so it cannot rise 
above the clamped ramp waveform. At sink cur- 
rents less than 300 /uA, the low output level will be 
within 200mV of ground but it rises to 1V at 
higher current levels. 

The input common mode range is from 1V to 
within 2V of the input supply voltage. V in , and 
thus either input can be connected directly to the 
5V reference. 



199 



Fig. 10 - The output of the error amplifier oper- 
ates class A to 300\iA, but can source 
and sink more than 1 mA for fast 
response. 




5V, 



ef 



TO PWM COMP. 



(7) 6 COMPENSATION 

J300pA 



The small signal, open-loop gain characteristics are 
shown in Figure 11. The amplifier is unity-gain 
stable and has a maximum slew rate of just under 
1V/ms. 



PWM comparator and latch 

This comparator (see Figure 7) generates the out- 
put pulse which starts at the termination of the 
clock pulse and ends when the ramp waveform 
crosses the lowest of the three positive inputs. The 
clock forms a blanking pulse which keeps, the 
maximum duty cycle less than 100%. The PWM latch 
insures there will be only one pulse per period and 
eliminates oscillation at comparator cross-over. 



Fig. 11 - The U CI 840 error amplifier has a DC 
gain of 67 dB, a 2 MHz bandwidth, and 
phase margin of approximately 45°. 




PWM output stage 

In addition to the PWM output signal on pin 12, 
the UC1840 also includes an output gating, or 
arming function as Driver Bias on pin 14. Both 
functions should be considered together in inter- 
facing to the external high-voltage power switch. 
These are illustrated in simplified form in Figure 
12. 

At very low input voltages (V )N < 3V), both Q2 
and Q4 are OFF. This may necessitate the use of 
R2, but its value can be high since it does not have 
to turn the output switch off. It merely holds it in 
the off state during the early portion of start-up. 

Between V m = 3V and the start threshold (pin 2 = 
3V with hysteresis on), Q2 is OFF and Q4 is ON, 
clamping the power switch off with a low impe- 
dance. A start command (UV high) turns on Q2, 
applying {V iN - 2V) to R1. This provides a source 
for power switch activation; however, since Q4 is 
still conducting, the current through R1 is shunted 
to ground and the power switch remains held off. 



Fig. 12 - Interfacing the UC1840 PWM output stage to either Bipolar or Power MOS switche 
UC1840 

*°< 



START 
SIGNAL 




BIPOLAR 



DRIVE BIAS 



^\^ 



~^\ PWM OUT 



POWER MOS 



200 



At the same time Q2 turns on, the clamping transis- 
tor at the slow-start terminal, pin 8, turns off 
allowing the voltage on pin 8 to rise according to 
the external slow-start time constant described 
earlier. This allows PWM pulses to begin to activate 
Q4 — narrow at first and widening to the point 
where the error amplifier takes command. 

The interface between the UC1840 and the pri- 
mary power switch may be implemented in several 
different ways to meet varying system require- 
ments. One obvious application is when the use of a 
bipolar transistor switch requires more drive cur- 
rent than the Driver Bias output can provide. 
Figure 13 shows a more typical bipolar drive 
scheme where Q5 has been added to boost the 
turn-on current with the UC1840 still providing 
the high speed turn-off. The circuit now serves as a 
more efficient "totem-pole" driver since Q5 turns 
off when Q4 conducts. It also illustrates the use of 
a Baker Clamp to minimize storage time in Q6 and 
the capacitors for rapid turn-on and high-current 
pulse turn-off. 



Fig. 13 - Adding Q5 as a switched, drive-boost 
transistor provides added base drive for 
Q6 while reducing the steady-state cur- 
rent through both Q2 and Q4. 



circuitry has been included to sense over-voltage, 
under-voltage, or over-current conditions. Addi- 
tionally, high-speed, pulse-by-pulse digital current 
limiting is included as a separate function. The 
operation of these circuits is described below. 



Fig. 14 - Interfacing the UC1840 single PWM out- 
put to a two-transistor off-line forward 
converter which uses proportional base 
drive. 



- " K t 






r ,. 




-": 


r@- 






;,c?a«> 






4-4 ■» N 
A 5ic 




'\ 




-• 


?""..----» •-"■ 








1 







--©' 



?-€*» 



— K?2 



0*o JT +C^' 



— fe 



^B» ! 



Current limiting 

The current limit comparators have differential 
inputs for noise rejection but are intended to be 
used with ground-referenced current sensing as in 
Figure 15. Comparator A1 is delegated to pulse- 
by-pulse current limiting. The output of this com- 
parator drives the PWM comparator, where it acti- 
vates the PWM latch, terminating each pulse when 
the current sensed by R sc reaches a threshold 
defined by divider R1, R2, and the 5V reference. 



Another application is the two-transistor, off-line, 
forward converter topology shown in Figure 14. 
This circuit uses proportional base drive where the 
UC1840 need only supply a short, turn-off current 
pulse with transformer regeneration through T1 
providing the steady-state drive. The magnetizing 
current is controlled by R1, with Q5 added to 
rapidly recharge C1 from which the turn-off cur- 
rent is supplied. 



Fault protection 

A significant benefit in using the UC1840 is the 
multi-faceted fault-sensing and programming capa- 
bility built into the device. With the intent to pro- 
vide complete control to the power system under 
all types of potential malfunctions, fault-sensing 



Fig. 15- Current limiting and overcurrent shut- 
down are implemented with comparators 
of different thresholds and a single cur- 
rent sense resistor. 



PULSE BY PUlSE 



r- ---+- 




■ ■AOO mV I 
1 



& 



I |JR2 



201 



Since V c is intended to track the supply's output 
voltage, the addition of a resistor from pin 6 to V c 
will provide some foldback to the current limit 
characteristic. Since comparator A1 has zero offset 
voltage, it is activated when the voltage across Rsc 
equals that across R2. Comparator A2, with an 
offset voltage of 400 mV, will activate for over- 
current shutdown when the voltage across Rsc 
rises to 400 mV higher than the voltage across R2. 
Since the input bias to both comparators is less 
than 5 /iA, a low-pass filter for noise rejection may 
be inserted between R sc and the sense inputs. 
Activation of comparator A2 is defined as an over- 
current fault and it triggers the Error Latch. Its 
operation follows. 



Fault sequencing 




tion of the circuitry. Setting the Error Latch imme- 
diately turns on Q1 and Q2, discharging the slow- 
start capacitor and terminating the PWM output. 
Note that there is an additional path from the in- 
verted output of the Start/UV comparator through 
OR2 which keeps pin 8 low. This is to keep the 
slow-start low during initial turn-on which is not 
intended to be classified as a fault. 

The input to the Error Latch is from OR1 which 
triggers on signals resulting from four possible 
events'. 

(1) A voltage less than 3V (after prior turn-on) at 
the Start/UV sense terminal, pin 2. 

(2) A voltage greater than 3V at the Over-Voltage 
Sense terminal, pin 3. 

(3) A voltage of less than 3V on the Ext. Stop 
terminal, pin 4. 

(4) An over-current signal resulting in a differ- 
ential voltage between pins 7 and 6 of greater 
than 400 mV. 



Fig. 16 - Fault sequence logic is designed to insure a complete shutdown and fully controlled restart 
upon any of four possible fault conditions. 




-►tO DRIVE SWITCH 



TO PWM 
COMPARATOR 



5V 



START I ^ WoVl 
LATCH ■ 



EXT ST0P„ 
0V SENSE; 
0C SENSE 



UV 
FAULT 




^)oR?>"-Ko 



J 
■-KQ2 



Any of these inputs need only be momentary to 
set the Error Latch. Transient protection may be 
necessary to eliminate false triggering, but it can be 
readily accomplished as all the comparator inputs 
are high impedances requiring less than 2 nA of 
input current, and the 3.0V reference yields a high 
noise immunity. 

The Start Latch can be understood by recognizing 
that at initial turn-on it is reset with a low output. 
This prevents AND2 from transmitting a UV fault 
signal from the Start/UV non-inverting output to 
the Error Latch. At the start voltage level, defined 
by a high level on the Start/UV non-inverting out- 
put, the Start Latch sets but AND2 still provides 
no output. Only when the Start/UV input goes low 
again, with the Start Latch output held high, will 
AND2 yield an output into the Error Latch. 

The status of the Reset terminal, pin 5, determines 



what happens after the Error Latch is set. The 
choices are: 

(1) Latch off and require a recycle of input volt- 
age to restart. 

(2) Continuously attempt to restart. 

(3) Attempt some number of restarts and then 
latch off. 

(4) Latch off and await a momentary reset pulse 
to restart. 

To examine the operation of the Reset Latch, note 
that prior to setting the Error Latch, its low output 
is inverted to hold the reset input to the Reset 
Latch high. This forces the Reset Latch's output 
low, regardless of the voltage on pin 5, and, thus, 
insures no signal out of AND1 . With the setting of 
the Error Latch, the Reset Latch is free to take the 



202 



state commanded by pin 5: high if pin E is low and 
vice-versa. The latch allows merely a pulse to set 
the Reset Latch; the voltage on pin 5 need not be 
steady state. 

With a high Reset Latch output, the Error Latch 
still does not reset until a low signal is sensed on 
the Start/UV sense terminal. At that point, AND1 
then resets both the Error Latch and the Start 
Latch re-establishing the initial conditions for a 



normal start after fully charging the input capaci- 
tor. Of course, if the fault is still present, when the 
Start/UV input reaches the start level terminating 
the Error Latch reset signal, this latch will imme- 
diately set again. 

To aid in the understanding of this logic, Figure 17 
gives a pictorial representation of its operation 
with both steady-state and momentary signals on 
both the Ext. Stop and Reset terminals. 



Fig. 17 - The interrelationship between the functions controlled by the fault sequence logic is illustrated 
with both static and pulse commands on the ext. stop and reset terminals. 




DRIVER 
BIAS 

5L0W- 
START 

PWM 

OUTPJT 

EXT. 

STOP 



LTLTLT 



¥ 



¥ 




IBS T 



Note 1: V c represents an analog of the supply output voltage generated by a primary - referenced 
secondary winding on the power trasformer. It is the voltage monitored by the start/UV com- 
parator and in most cases is the supply voltage V, N for the UC1840 



EVENT 



INITIAL TURN-ON V c RISES WITH LIGHT LOAD 

START THRESHOLD DRIVER BIAS LOADS V r 

OPERATING PWM REGULATES V c 

STOP INPUT SETS. ERROR LATCH TURNING OFF PWM 

UV LOW THRESHOLD. ERROR LATCH REMAINS SET 

START TURNS ON DRIVER BIAS BUT ERROR LATCH STILL SET 

V c AND DRIVER BIAS CONTINUE TO CYCLE. 

STOP COMMAND REMOVED. 

ERROR LATCH RESET AT UV LOW THRESHOLD 

START THRESHOLD NOW REMOVES SLOW-START CLAMP 

RETURN TO NORMAL RUN STATE 

RESET LATCH SET SIGNAL REMOVED 

ERROR LATCH SET WITH MOMENTARY FAULT 

ERROR LATCH DOES NOT RESET AS RESET LATCH IS RESET 

V c AND DRIVER BIAS RECYCLE WITH NO TURN-ON. 

RESET LATCH IS SET WITH MOMENTARY RESET SIGNAL 
V c MUST COMPLETE CYCLE TO TURN ON 
START AND ERROR LATCHES RESET 
NORMAL START INITIATED. 
RETURN TO NORMAL RUN STATE 



203 



If Driver Bias turn-on is used to pump an incre- 
ment of charge into an integrating capacitor, and 
that capacitor voltage is applied to the Reset 
Terminal, some number of retrys could be pro- 
grammed to take place before the Reset voltage 
rises to 3V, which would then lock the output 
OFF. Since Driver Bias continues to cycle in the 
latched-off state, the Reset terminal will remain 
high until it is either remotely pulled low or the 
input voltage to the controller is interrupted. 

Note that an important element in any restart after 
a shutdown is the lowering of the voltage at the 
Start/UV terminal below its UV threshold. While 
this will occur normally in bootstrap-driven appli- 
cations, this device can also be used with a con- 
stant driving voltage by externally applying a 
momentary pull-down signal to the Start/UV input 
after a fault shutdown. 



CONCLUSION 

With the UC1840, power supply designers now 
have a device specifically developed for off-line, 
primary control and one which has addressed the 
problems of operation under less than "ideal" or 
normal conditions. Not only does this device make 
it easier to comply with stringent isolation require- 
ments by requiring a minimum of communication 
between primary and secondary, but it is also 
ideally suited for powering systems in remote loca- 
tions where only a simple transmitted pulse is 
available for power sequencing. 



© 1983 by Unitrode Corporation. All rights re- 
served, This bulletin, or any part or parts thereof, 
must not be reproduced in any form without per- 
mission of the copyright owner. 



204 



50W OFF-LINE 



SWITCHING POWER SUPPLY USING 
THE UC3840 



INTRODUCTION 

This power supply has been designed to pro- 
vide an easy way to gain familiarity with the oper- 
ating characteristics of the UC3840 PWM Control 
Circuit in a pratical off-line power supply appli- 
cation. As any switching power supply represents 
a series of compromises between size, cost, effi- 
ciency, performance, and many other variables; 
no claim is made that this supply optimizes any 
particular characteristics; only that it provides an 
easy means to gain an understanding which, 
hopefully, the designer can use to extrapolate to 
many specific applications. 

This power supply, shown schematically in Fig. 4 



implements a 50 watt discontinuous mode 
flyback power supply with multiple outputs, 
and features primary-side control with full pro- 
tection from fault conditions. Additional per- 
formance characteristics include simple off-line 
starting, voltage feed-forward for good line regu- 
lation (without feedback across the isolation 
boundary), pulse-by-pulse current limiting, over- 
and under-voltage sensing with protective shut- 
down and automatic restart, and freedom from 
the need for any circuit adjustments. 

For additional information on the operation of the 
UC3840, reference should be made to TN 168 
and data sheet. 



205 



POWER SUPPLY SPECIFICATIONS 

Input line voltage: 

With 110V jumper: 

With jumper 

removed: 
Input frequency: 
Switching frequency: 
Output power: 
Output voltages: 



Output current: 
Line regulation: 
Load regulation: 

Efficiency @ 50 watts 
V in = 90 VAC: 
V in = 130 VAC: 

Output ripple: 



90 VAC to 130 VAC 

180 VAC to 260 VAC 

50 or 60 Hz 

40KHz ± 10% 

50W maximum 

5V ± 5% 

1 2V ± 5% 

2.5 to 5A (5V) 

1 to 2A (12V) 

5V, 0.07% /V 

12V, 0.04% /V 

5V, 2. 5%/ A 

12V,2.5%/A 

70% 

65% 

5V @ 5A = 200mV 

12V @ 2A = 300mV 



OPERATING PRINCIPLES 

In an off-line switching power supply, the input 
voltage is immediately rectified and filtered, and 
the resulting DC voltage is chopped at a high 
frequency. Where 110/220 VAC operation is 
required, an input voltage doubler configuration 
is used for 110 VAC input, resulting in a nominal 
DC input voltage of 310V. The same nominal 
input voltage is obtained with full wave rectifica- 



tion of a 220 VAC line input. High frequency 
switching allows a very small transformer to be 
used to efficiently step down to lower output vol- 
tages. In the configuration shown in Figure 1 an 
additional low-voltage winding, N c , is used to pro- 
vide continuous operating power for the control 
and base drive circuits. However, initial energy to 
start the supply is taken from the line via R in and 
C m . An additional function on N c is to provide a 
primary-referenced feedback voltage that is pro- 
portional to the output voltages. This feedback 
voltage is sensed and regulated by the control 
circuitry, thereby eliminating the need for feed- 
back across the isolated boundary. 

The polarity of the transformer windings identi- 
fies this configuration as a flyback supply. When 
transistor Q s conducts, all output diodes are 
reverse biased and the energy is stored in the 
primary inductance. When Q 5 turns off, the vol- 
tage polarity of winding N p reverses (flies back) 
and the energy is delivered to the output circuits. 
This circuit operates in the discontinuous mode 
in which all the energy stored in the trasformer 
inductance is completely transferred to the load 
during every cycle, i.e. transformer current goes 
to zero before the end of each cycle. Although 
this approach yields higher peak current com- 
pared to other topologies, it is usually chosen 
because of its less stringent requirements on the 
transformer, its faster transient response, and its 
easier stabilization. To insure discontinuous 
operation and core reset, the volt-second pro- 
duct across the transformer primary during reset 
must be allowed to equal or exceed the volt- 
seconds applied during the on-time of Q s . 



Fig. 1 — Simplified block diagram of a flyback power supply with primary control 

PRIMARY DC V n 




206 



DESIGN CONSIDERATIONS 

The following description of the design decisions 
made for this power supply will be with respect to 
the complete schematic shown in Fig. 4. No 
significant theoretical discussion is offered and 
only nominal values are used in the analysis, but 
hopefully the equations given can be used to 
either extrapolate to other design problems or to 
optimize the supply to a particular characteristics. 

Input section 

Input bridge D1 rectifies the line voltage while 
resistors R1 and R2 are used to limit the peak 
charging current to capacitors C1 and C2. The 
values for C1 and C2 are usually determined by 
either the ripple voltage allowable for V DC or the 
minimum hold-up time. 

Ripple calculations are worse-case for the 110V 
voltage doubler configuration where: 

RMS line voltage = 90 to 130 VAC 
peak no-load input = 253 to 368 volts. 

At the minimum line voltage, each capacitor 
alternately charges to a peak of 126 volts. Allow- 
ing for a total input voltage sag at full load of 50 
volts, the minimum capacitor voltage must be 
held to 92 volts. Since each capacitor must pro- 
vide one-half the energy requirements of the power 
supply, the required energy for each line cycle is: 



W, 



Power out 



50 



Efficiency x Frequency 0.7 x 60 



1.2 Joule 



and the capacitor value can be calculated from: 



KWm-KC! (V pk 2 -V mln 2 )or 



normally required between regulation, leakage 
inductance (and corresponding transistor stress), 
isolation, size, and cost. In this application, the 
core selected is a Ferrox-cube EC35-3C8 which has 
the following characteristics: 

Effective core area, A e = 0.84 cm 2 
Max flux density, B^ = 2800 gauss 
Bobbin = 35 PC B I 

The design starts with a calculation of maximum 
duty cycle which is defined by the voltage capa- 
bility of the power switch. This voltage was allo- 
cated as follows: 



VDC max 
Reset voltage 
Leakage inductance spike 
Max total voltage 



= 370V 
= 120V 
= 100V 
= 590V 



With a reset voltage of 120V, at minimum input 
voltage, 



120V 



120V + 200V 



= 37.5% 



The primary inductance can then be calculated as: 



Efficiency 
2P„ f 



(Vim 



x D_ 



0.7 (200 x 0.375) 2 
2 x 50 x 40 x 10 3 



1mh 



C, =■ 



W ir 



1.2 



'pk 



126 2 -92 2 



= 162mF 



If, instead of ripple voltage, we choose the input 
capacitors to hold the input DC above 200 volts 
for a least two cycles of line drop-out, then: 

2 (Po/2) (no. of cycles drop-out) 1/f 



Efficiency (V pk 2 
2(25) (2) 1/60 



0.7 (126 2 -92 2 ) 



331mF 



In this application, 470/jF was picked as a stand- 
ard size which would allow loose tolerances. 



The peak current at full load is: 
2P n 



eff < V in min * Dmax) 
2x 50 



0.7 x 200 x 0.375 



= 1.9A 



The maximum energy storage requirement within 
the primary is calculated on the basis of maximum 
current, in this case assumed to be short circuit 



W = CiL U 



y=(1 x 10" 3 ) (2.3) 2 = 2.65 m Joule 



The equation defining energy storage in an in- 
ductor is: 



Transformer 

A major task with any flyback power supply is the w = V. BAcH e x 1 0" 8 iQU \ cz 



design of the transformer as many tradeoffs are 

207 



0.477 



Therefore, 



H£e= (0.4tt 



2Wx 10 8 
BA r 



0,4tt x 2x 2.65 x lO" 3 x 10 s 



282 Gilberts 



2800 x 0.84 
Since H^e = 0.47rNI, on the basis of l sc = 2.3A, 



N n = 



282 



p 0.4 it l 5C 0.4u x 2.3 



; 98 turns 



The air gap for the core is determined by kno- 
wing that 



H = — = 2800 Oersteads 

M 



And assuming that with an air gap 
l e «> l g . , then 

i rsA Nl 0. 4 7T (98) 2.3 n 1 ^ m 

n = 0.4 n = = 0.1 cm 

9 H 2800 



With the primary turns defined, each secondary 
can be calculated from: 



N N p (V + rectifier V f ) (1 - D max ) 

"in (min) D max 

With minor adjustments to give an integral number 
of turns, the final transformer winding specifi- 
cations are: 

First winding — primary — 97 turns, AWG 24 
Second winding — 5 volt — 4 turns, 4 parallel 

AWG 22 
Third winding — 12 volt— 9 turns, 2 parallel 

AWG 22 
Last winding — control — 9 turns, AWG 24 evenly 

spaced along the full bobbin length 



Power switch and drivers 

In this application, the peak switch current is 2.3 
amps and the peak collector voltage will be ap- 
proximately 590 volts including the spike caused 
by leakage inductance. The switching transistor 
selected is the MJE13005 which has the following 
characteristics relative to this application: 



BV rPn 


= 400V 


BV cer 


= 700 V 


(contl 


= 4A 


n fe 


= 8 -40C42A 


U 


= 1 ,5;us 


*r 


= 0.28ms 


tf 


= 0.25ms 



While offering inexpensive, high-voltage swit- 
ching, the MJE13005 needs some support to pro- 
vide adequate base drive and minimize storage 
time. This is readily accomplished with the cir- 
cuitry shown in Figure 2. Prior to obtaining a 



Fig. 2 — The high voltage power switch, Q3, and its driver interface circuitry 



CONTROL VOLTAGE Vi n 



PRIMARY V n 




208 



start-up signal, the Drive Bias transistor in the 
UC3840 is off insuring that there is no quiescent 
current being drawn by any of this interface cir- 
cuitry. At start-up, the Drive Bias switch turns on 
providing a pull-up for the UC3840's PWM out- 
put. The current through R16 is multiplied by the 
gain of Q1 to provide a forward base drive in 
excess of 250mA for the power switch Q3. Diodes 
D5 and D6 form a Baker clamp to keep Q3 out of 
hard saturation and improve turn-off, especially 
al lower collector currents. 

Transistor Q2, driven on by the turn-off of Q1 , 
provides a low-impedance path for reverse base' 
current of Q3, and together with the use of the 
Baker clamp, results in a storage time for Q3 of 
less than 800nsec. 



C11 = 



50 x 10-s (2.3P 



(120+ 100) 2 



120 2 



: 0.0078 » 10nF 



Resistor R26 is selected to discharge C1 1 during 
the remainder of the period leaving a residual 
voltage equal to the reset voltage at the time 
turn-off next occurs. 



R26=- 



/ reset + A V pp ) 0.63 t 



220 0.63 (25 x 10" 6 ) 



100 



(0.01 x 10" 6 ) 



= 3.5KH 



Snubbing circuits 

There are two snubber circuits incorporated 
into this supply. The network of C12, D7, and 
R27 is used for load line shaping of transistor 
Q3 by delaying the voltage rise at the collector of 
0.3 while the current falls at turn off. 

The values for the components in this network 
are calculated as follows: 



In this application, R26 was increased to 4.7k due 
to second order effects such as reverse recovery of 
D2 which aids in discharging C1 1. 

The power loss in R26 comes from the energy 
stored in the leakage inductance which is 

P = 1 /2l_p 



! f = 1 /*50x 10" 6 (2.3) 2 40 x 10 3 



P «= 5.3 watts 



C12 



Isctf 



2 V, 



n(max) 



2.3 x 0.25 x 10-* 
2x 370 



but here again, second order effects tend to 
680pF reduce this value to less than 3 watts in this power 
supply. 



The resistor R27 is selected to discharge C12 
with a time constant of one-half the minimum on 
time, which - under short circuit conditions - is 
approximately 2.5ms. 



R27 = 



ton (mln) 
2C12 



2.5 x 10" 



2 x 680 x 10~ 12 



The power dissipated in this resistor is 



« i.8Kn 



Operating frequency 

The frequency is set by R14 and C4 as 



1 



Rt C 



1 



10 3 



T^T 



U4 c 4 12 x 0.0022 



■■ 40kHz 



P = , /*C12(V inmax) * 
40 x 1 3 

P « 2 watts 



f = % (680x1 0" 15 ) (370) 2 



The second network of R26, C1 1, and D2 limits 
the voltage spike at turn off caused by the leak- 
age inductance of the power transformer. The 
energy stored in this inductance is transferred 
into C11 via D2 after the power switch turns off 
and the voltage rises above the supply plus reset 
voltage. 

C1 1 is defined by: 



C11 



Preset + AV PP ) 2 



Where L 6 = Leakage inductance (« 50mH) 
v reset = Reset voltage across transformer (120V) 
Vpp = Allowable leakage inductance 

Voltage spike (100V) 



Supply start-up 

The supply must reliably start with V DC minimum 
= 250V. The value of R3 + R4 is defined by the 
total current requirement of the control electronics 
prior to start. If a start threshold of 12 volts is 
assumed, total control current is: 



UC3840 max = 7.0mA 

R7 + R8 = 0.70mA 

R10+R11 = 0.27mA 

C4 charging current = 0.40mA 

R17 + R18 = 0.22mA 

Total Turn-On Current 8.59mA 



and R3+ R4 = 



250-12 
8.59 



-= 27Kft 



209 



Note that R3 and R4 also provide a bleeder path 
to discharge C1 and C2. 

Once start-up is initiated, the control current 
becomes: 

UC3840max = 15mA 

R16 = 6mA 

Q3 lb (x 0.375 duty cycle) = 94mA 



Total run current 



= 115mA 



This current must come from C3 until power is 
available from control winding, N4. This, in con- 
junction with the start-up time, defines a min- 
imum value for C3. 

Although a small soft-start capacitor is incorpo- 
rated in this supply, its time constant is much 
shorter than the time to charge the output capac- 
itors with the duty cycle defined by the ramp 
waveform and the pulse-by-pulse current limit. 
With the supply fully loaded, start up takes ap- 
proximately 5msec. During this time, the vol- 
tage on C3 cannot fall below the under-voltage 
threshold. 

In defining the start and UV thresholds, one other 
consideration is the state of the error amplifier. As 
defined further below, the error amplifier is going 
to force V c to 1 2 volts. If the start threshold is set 
above this value, the start signal will release the 
soft-start clamp and arm the driver bias but no 
PWM output will appear until V c droops below 12 
volts and the output of the error amplifier goes 
high To insure soft-start action, the start thre- 
shold has been set at 11 volts and the under- 
voltage level is 8 volts. 

Now the value for C3 can be determined from: 



C3 — •-. - * (start) to n _ 



. 3VIR7 + R8) „ w 
V c (UV fault) = ^ = 8V 



This second equation may be subtracted from 
the first to yeald R7 = 15KJ7, which then defines 
R8 -9.1KH. 

An over-voltage fault in terms of Vqc can be cal- 
culated by equation: 



V DC (OV fault) = 3V J55_LM = 400V, or 



3 (min) 



AV r 



= (115 x IP' 3 ) (5x 10' 3 ) = i 92;UF 
(11 -8) 

The start and under-voltage thresholds are defined 
by R7 and R8 conjunction with the 3 volt threshold 
and the hysteresis current of the comparator on 
pin 2 of the UC3840. As the voltage rises on pin2, 
that pin is sinking 200/uA of current causing an 
added voltage drop across R7. When pin 2 reaches 
3 volts, turn-on is initiated and — at the same time 
the hysteresis current is removed causing the vol- 
tage at pin 2 to jump above 3 volts. 

Now, as the power supply attempts to start, the 
voltage on pin 2 falls and, if it reaches 3 volts 
from this direction, an under-voltage fault is sensed. 

The start voltage at V c is defined by: 



R6 



R5 = 132 R6 



Small capacitors (10nF) have been added to both 
comparator inputs to minimize noise sensitivity. 



Feed-forward 

This function provides a variable-slope ramp 
waveform on pin 10 which is one of the inputs to 
the PWM comparator. This signal is compared 
with the output from the error amplifier on pin 1, 
and the pulse width is defined by the time it takes 
the ramp to rise to the level of the error amplifier's 
output. If the ramp slope is made proportional to 
the DC input voltage, a rising input voltage will 
immediately increase the ramp slope, and cor- 
respondingly reduce the pulse width with no change 
required from the error amplifier's output. The 
result will be a constant volt-second product 
delivered to the transformer primary resulting in 
good open-loop line regulation. 

The design procedure used to define the ramp 
characteristics is to set the ramp slope such that 
it reaches its peak value at a time equal to the 
maximum pulse width allowed by the transformer 
design. This was set at 43% with minimum input 
voltage and a potential shorted output. The time 
for the ramp to go from its minimum to maximum 
value is then: 



on (max) 



f 



__043 

40 x V0 3 



10.75/isec 



and the slope is: 



dv 
dT 



V„ 



(min) 



'pk " "valley 
ton (max) 



= A2_ J1 1 5_ = o.344V//Jsec 
10.75 



3 V (R7 + R8) 
V c (start) = —^ + 0.2mA (R7) = 1 1 V and since the slope is determined by: 



R8 



while the under-voltage threshold is: 



dv V DC 



dt R15C8 



210 



R15C8 : 



200V 



0.34V//JS 



= 581/Jsec 



With the knowledge that the ramp generator has 
greatest linearity with currents in the 100mA to 
300mA range, we can pick: 



R15 = 1.5 MO and C8 = 390pF. 



Duty cycle clamp 

The above analysis has provided a maximum duty 
cycle of 43% at minimum operating voltage. When 
the AC line voltage is removed, however, the input 
voltage will fall below 200 volts with the supply 
still running. As this voltage falls, the ramp slope 
will reduce and at the same time the error amplifier 
output will increase in an attempt to maintain 
regulation. This could extend the pulse width 
beyond 43% except for the action of the duty 
cycle clamp divider of R19 and R20 which is set 
to provide 3.9V at pin 8 with V DC = 200V. 
Therefore, as V DC falls, the voltage on pin 8 will 
also fall, taking command away from the error 
amplifier and maintaining a constant pulse width 
until the Under-Voltage sensing circuit gives a 
shutdown command. 



Voltage control 

In this power supply, output voltage regulation is 
controlled from the primary side by sensing Vq 
with R10 and R11 and closing a control loop 
with the error amplifier and 5V reference in the 
UC3840. The output voltage is then: 



V n (5V) 



N2 
N4 



V ref 



R10 + R11 
R11 ' 



Although the UC3840 optimizes this approach 
by the use of feed-forward which provides first- 
order automatic line regulation, there will still be 
inaccuracies caused by inadequate coupling beet- 
ween the windings, IR drops within the wind- 
ings, and unequal losses in the rectifiers. If greater 
voltage accuracy is required, the feedback loop 
must be connected directly to one of the outputs 
with either on optical coupler or the UC1901 
Isolated Feedback Generator used to maintain 
isolation. 



where K is defined by the feed-forward slope as 
(Max duty cycle) (V in min) 43 x 2 00 



K = 



Ramp peak - Ramp valley 4.2 - 0.5 



and the minimum load resistance reflected to the 
primary control supply is: 



V 2 



^L min _ „ 

PO max 

"Q _ 0.43x200 
v c " 4.2-0.5 

= 4.41 = 13db 



50 



: 2.88H 



25 x 10~ 6 x2.88 . 
2x 1-x 10" 3 



Fig. 3 - Power supply loop gain and phase 

















ER'-iOR 

AMP 

GAIN 








I__ 




n& 


Sq 






$ 




i \ 










* 
\ 

\ 

\ 
\ 
* 





10K f(Hz) 




The gain and phase plots for this supply are shown 
in Figure 3. Overall loop stability is aided by the 
fact that a discontinous-mode flyback topology 
is inherently a single pole system defined by the 
output load. Its transfer function, excluding the 
error amplifier, is shown by the dashed curve of 
Figure 3. The DC gain from the modulator input 
v c , to the output, v , is: 



= K 



T R 



L mln 
~2~U 



The effective output capacitance, 
to the control supply, is: 



also reflected 



C P = C14 



4700 



3328m F 



N2 



C13 



/N3_\ 2 
I N4 / 



+ C3 



+ 2200 



(-1-)' 



+ 200 



211 



The yields an output pole at 



fi =• 



2ttR l C e 



10 6 
~638 l~278~8)~3328~ 



: 16.6Hz 



The error amplifier is set up for an added DC gain 
of approximately 35db and a second pole at 
8kHz - a frequency well above the overall unity 
gain point and yet below the roll-off frequency of 
the error amplifier. 



Current limiting 

The UC3840 limits current through the power 
switch, Q3, by sensing the voltage across R25. 
Pulse-by -pulse current limiting is defined by the 
divider R 1 7, R1 8, and the value of R25 as: 



V 



REF 



R18 



R25 (R17+ R18) 



5 .0 (1 0k) _ 
in (12k +'Toi<) 



2.2 amps 



If the required pulse width becomes too narrow 
for the pulse-by-pulse circuitry to respond, the 
UC3840 contains a second level of protection by 
initiating a fault shut-down if the voltage across 
R25 rises to 400mV above the voltage established 
by R17 and R18 on pin 6. Care must be taken 
that this threshold is not exceeded by a leading 
edge spike which might be present on the cur- 
rent waveform. 



Fault protection 

The UC3840 defines four functions as faults. 

1. An under-voltage signal on pin 2 (after a start 
command) 

2. An over-voltage signal on pin 3 

3. An external stop command on pin 4 

4. An over current shut-down from pin 7 

Any of these functions will initiate a complete 
shutdown of the controller with restart defined by 
the voltage on the reset terminal, pin 5. 

If pin 5 is high or open, any fault will latch the 
supply off and it can only be restarted by reducing 
the input voltage to zero or by momentarily 
pulling pin 5 low. Alternatively, grounding pin 5 
will cause an automatic restart after any fault 
shut-down. 



CONSTRUCTING THE KIT 

It is assumed that the user possesses reasonable 
electronic assembly skills and therefore detailed 



step-by-step instructions have not been consi- 
dered necessary. Rather, a general assembly pro- 
cedure is outlined below which, if followed care- 
fully, should offer no problems. Assembly starts by 
properly orienting the PC board with the assembly 
drawing shown in Figure 5. This drawing is of the 
component side of the board - etch side down - 
with the "Warning - HighVoltage" label at the 
lower left hand edge. 



Test and tie points 

Pads have been provided on the PC board for input 
and output connections and for many internal test 
points so that complete operation of all portions 
of the control circuitry can be evaluated. These 
points are noted in Figure 5 and are listed below: 



AC input . . 

DC input 

+ 12V output 

+ 5V output . 



H.V. Switching 
Transistor . . . 



(2 pads) 
(2 pads each- 
note that the 
commons may be 
separated for 
alternate polarities) 



... (3 pads) 

Note: 600V pulses will appear at the collector. 
BE CAREFUL OF THIS TEST POINT. 



Control Voltage V c . 
Primary Common . . 
E/A Compensation . . 
5.0V Reference . . . . 

E/A input 

Drive Bias 

PWM Control 

Ramp Waveform . . . 
S/S Duty Cycle Limit 
Oscillator Frequency . 
C/L Limit Sense . . . 
C/L Threshold . . . . 

Reset input 

Ext. Stop Input .... 
OVP Sense Input . . . 
UV/Start Input . . . . 



ICpi 


IC pi 


IC pi 


IC pi 


IC pi 


ICpi 


IC pi 


IC pi 


ICpi 


ICpi 


IC pi 


IC pi 


IC pi 


ICpi 


ICpi 


IC pi 



n 15 
n 13 
n 1 
n 16 
n 17 
n 14 
n 12 
n 10 
n8 
n9 
n7 
n6 
n5 
n4 
n3 
n2 



2 pads) 



No connections to these points have been in- 
cluded in this kit. It is suggested that the user 
either supply terminals or solder in small stubs or 
loops of bus wire so that connections to these test 
points can easily be made on the component side 
of the PC board with scope probes or other test 
instrumentation leads. 



Jumpers 

There are four jumpers required which are also not 
included in this kit. Use solid bus wire or a section 
clipped from the ends of the small resistors. These 
jumpers are: 



AC input jumper for 1 10V operation 
(leave out if 220 VAC is to be used) 
PWM jumper to pin 12 
UV/sian jumper to pin 2 



212 



Reset jumper on pin 5 
(leave out if it is desired to latch the supply off 
after any fault) 

Note that there is nothing connected to pin 4. A 
low signal here will shut down the supply. 



Small signal diodes 

The seven small axial lead diodes, D2 through 
D8 should next be installed insuring correct pola- 
rity as shown in Figure 5. 



Passive devices 

Install the low-power resistors and small capacitors 
first. Follow with the four high-power resistors, 
R3, R4, R26 and R27. When inserting R26, keep 
the body of the resistor » % inch above the PC 
board. This resistor will get hot and it is best to 
have it above, rather than next to C11. At this 
time, the input diode bridge, D1, and the IC socket 
can be inserted. Note that pin 1 of the UC3840 is 
to the front of the PC board. 



Large components 

Assembly can be completed by installing the 
remaining components as follows: 

a. Two small signal transistors, Q1 and Q2 

b. Transformer 

c. Electrolytic capacitors: C1, C2, C3, C13 and 
C14. Check polarity against signs of foil side 
of PC board. 

d. Power transistor Q3 inserts with its front to the 
left, or input, inside of the PC board. Inser- 
tion is easier if the heat sink is clipped on first. 

NOTE: THIS HEAT SINK IS AT THE SAME 
POTENTIAL AS THE COLLECTOR AND WILL 
HAVE UP TO 600 VOLTS PRESENT: KEEP IT 
CLEAR OF OTHER COMPONENTS, TEST 
LEADS, AND YOUR FINGERS. 

e. Install the 5 volt output rectifier, D9 with its 
front facing the right, or output side of the 
board. It also gets a clip-on heat sink. 

Check to see that all components are installed and 
match the drawing of Fig. 5 . Insert the UC3840 
into the socket. 



CHECKOUT PROCEDURES 

With the power supply fully assembled, the fol- 
lowing checkout procedure is recommended 
before any input voltage is applied. This proce- 
dure is also useful for trouble-shooting a unit 
which is not operating properly. Checkout will be 
aided if the user has installed test points at all in- 
dicated positions in the PC board. Reference 
should be made to Figure 5 for test point locations. 



1 . Insure that there is no AC input voltage applied 

2. Double check all connections including diode 
and capacitor polarities. Insure that the UC3840 
is correctly inserted into the socket. 

3. Connect a minimum load on one or both out- 
puts equivalent to 25 watts total, i.e., 2n on 
the 5V output and 12n on the 12V output. Be 
careful of the heat from these loads. 

4. Install a temporary jumper shorting the base 
and emitter of Q3 together. Use test points 
provided on PC board. 

5. Connect a to 30 volt, 500mA lab supply to 
simulate the control voltage, Vc- Connect the 
positive lead to IC-15 and ground to IC-13. 
Note that IC-13 will be the ground reference 
point for all primary side measurements. Set 
V c = Zero volts and add a 1kn, Vi W resistor 
in shunt across the power supply terminals. 

6. Increase V c to 10 volts and check the following: 

a. IC-16: should have 5V if the reference is 
working. 

b. IC-2: Should be 2.3V if hysteresis cur- 
rent is on. 

c. IC-14: Should be < 0,1V as Driver Bias 
is off. 

7. Increase V c to 14 volts and ckeck the following: 

a. IC-2: Should be 4.7 volts if hysteresis 
current is off. 

b. IC-14: Should be 12 volts with Driver 
Bias on. 

c. IC-9: Oscillator should show 40kHz ex- 
ponential waveform. 

d. Return V c to Zero volts but leave con- 
nected. 

8. Apply the high voltage, V DC . This can be done 
either with a DC lab supply with 300V capa- 
bility or the input AC line voltage. 

A fuse rated at no more than two amps should 
be in series with the input line to prevent 
excessive damage in the event of a failure. 

NOTE: BE SURE TO USE AN ISOLATION 
TRANSFORMER WHEN LINE POWER IS 
USED AS PRIMARY GROUND IS ONE SIDE 
OF THE LINE. 

An AC variac will also be helpful in varying the 
input voltage. 

If a DC power supply is used, connect the po- 
sitive line to the V DC test point at the top of 
the board. The negative line will connect to 
ground on IC-13. Insure that the base-emitter 
short is still connected to Q3. 

9. WithV DC = 200 volts, set V c = 10 volts and 
check the following: 

a. IC-14: Should be < 0.1V if Driver Bias 
is off 

b. IC-8: Should be < 0.1V of Slow Start 
clamp is on. 

c. IC-6: Should be 2.3V to establish current 
limit threshold. 



213 



a. 
b. 



d. 



10. With V DC = 200 volts, increase V c to 14 volts 
and check the following: 

IC-14: Should be 12V with Driver Bias on. 
IC-8: Should be > 3.9V with Soft-Start 
clamp off. 

IC-10: Ramp waveform with linear rising 
slope extending for approximately Vi the 
total duty cycle. Note: scope probe input 
capacitance can affect this measurement. 
IC-1: Should be < 0.5V at output of error 
amplifier, 
e. IC-12: Should be still clamped to < 1.0V 
with no output pulses. 

11. Reduce V c to 10 volts and check the fol- 
lowing: 

a. IC-1: Error amp output should now mea- 
sure « 4.1V 

b. IC-12: PWM output should have pulses of 
approximately 2V amplitude with a duty 
cycle of « 40% 

1 2. Reduce V c to 7 volts and check the following: 

a. IC-14: Driver Bias should be off. 

b. IC-8: The soft-start clamp should be on. 

13. Check the fault protective measures by fol- 
lowing the sequence below: 

a. Start the supply by raising V c above 14 
volts and then returning it to 10 volts. Set 
high voltage to 200 volts. Monitor IC-12. 

b. Simulate a fault by performing each of 
the following, in sequence: 

(DWith an additional lab supply momen- 
tarily apply 3.5V to the OVP on IC-3, or 



(2) Again using an external supply, momen- 
tarily apply 3.0V to the current sense 
point, IC-7, or 

(3) Momentarily short the stop terminal, 
IC-4, to ground. 

c. In each case, the signal on IC-12 should 
case and IC-8 should clamp low. 

d. To restart the supply after a fault, V c must 
go below 8 volts to reset the error latch; 
above 11 volts to restart; and then slightly 
below 1 2 volts to obtain a PWM output. 

14. Remove all external supplies and remove the 
base-emitter shorting jumper on Q3. Reconnect 
the high voltage source and raise the voltage to 
obtain V D c= 250 volts. The supply should be 
running. Q3 collector voltage can be monitored 
with the use of a high-voltage scope probe. 

WARNING: PULSES UP TO 600V ARE ON Q3'S 
COLLECTOR 

Normal power supply evaluation tests of line and 
load regulation, etc., may now be conduced. 



NOTE: In experimenting with this supply, the 
most probable mode of failure is the shorting of 
the high-voltage transistor, Q3. Should this occur, 
transistor Q2 will also go. A two amp input fuse 
will normally protect the input diodes, R1, R2 and 
the current sense resistor, R25, although these 
should be checked before reapplying power. 
Diodes D5 and D6are normally adequate to protect 
Q1 and the IC. 



PARTS LIST 



ICs 




Resistors 




Miscel 


aneous 


U1 


UC3840N 


FM, R2 


1S2, KW 


HS1 


HS2.Heat Sink Thermalloy 6043 






R3 




15k 2W 


Tl 


Transformer 


Transistors 




R4 




12k, 2W 




Coilcraft, E - 4140 - B 


Q1, Q2 


2N2222 


R5 




750k 






Q3 


MJE 13005 


R6 

R7 




5.6k 
15k 






Diodes 




R8 




9.1k 






D1 


VM68 Bridge 


R9 




unused 






D2, D6, D7 


1N3614 


R10 




26.7k, 1% 






D3, D4 


1N3612 


R11 




17.8k, 1% 






D5 


1 N4946 


R12 




1.5M 






D8 


UES1103 


R13, 


R14 


12k 






D9 


USD735 


R15 
R16 




1.5M 
1.5k 






Capacitors 




R17 




12k 






C1, C2 


470mF, 250V 


R18 




10k 






C3 


200,uF, 25V 


R19 




750k 






C4 


2200pF, 10% 


R20 




15k 






C5, C6 


10nF, 50V 


R21 




33 n, SW 






C7 


22pF 


R22 




15k 






C8 


390pF, 10% 


R23 




4.7k 






C9, C10 


10nF, 50V 


R24 




2.0k 






C11 


lOnF, 400V 


R25 




1.0S1.1W 






C12 


680pF, 800V 


R26 




4.7k, 4W 






C13 


2200mF, 16V 


R27 




1.8k, 2W 






C14 


4700/uF, 10V 













214 



Fig. 4 - UC3840 PWM control circuit 




215 



Fig. 5 — P.C. board components layout of the Fig. 4(1: 1 scale) 




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216 



A SECOND-GENERATION IC SWITCH MODE 

CONTROLLER OPTIMIZED FOR 

HIGH FREQUENCY POWER MOS DRIVE 



INTRODUCTION 

Since the introduction of the SG1524 in 1976, 
integrated circuit controllers have played an im- 
portant role in the rapid development and exploita- 
tion of high-efficiency switching power supply 
technology. The 1524 soon became an industry 
standard and was widely second-sourced. 
Although this device contained all the basic control 
elements required for switching regulator design, 
practical power supplies still required other func- 
tions which had to be implemented with additional 
external discrete circuitry. 

An additional development within the semiconduc- 
tor industry was the introduction of practical 



Power Mos which offered the potential of higher 
efficiencies at higher speeds with resultant lower 
overall system costs. 

In order to be able to take full advantage of the 
speed capabilities of power MOS, it was necessary 
to provide high peak currents to the gate during 
turn-on and turn-off to quickly charge and dis- 
charge the gate capacitances of 800 to 2000pF 
present in higher current units. 

The development of a second-generation regulating 
PWM IC, the SG1525A, and its complimentary 
output version, the SG1527A, was a direct result 
of the desire to add more power supply elements 
to the control IC, as well as to optimize the in- 
terfacing of high current power devices. 



Fig. 1 - The SG 1524 regulating PWM block diagram 

This design was the first complete I. C. control chip for switch mode power supplies. 



REE 
REG. 



OSC OUT 
3 O 



Ct 
1 O- 



r 



_U 



FLIP 
FLOP 



Y R£F 

O 16 



COMPENSATION 



INV. INPUT 

1 o — 



N.], INPUT 

2 



GNO 
SO— 



1 






•SENSE 

-O 4 



-SENSE 
O 5 



SHUTDOWN 
O 10 



217 



INTEGRATING MORE POWER SUPPLY 
FUNCTIONS 

Having achieved the greatest level of acceptance 
among users of first generation control chips, the 
1524 became the starting point for expanding IC 
controller capabilities. This early device, shown in 
Figure 1 , contains a fixed-voltage reference source, 
an oscillator which generates both a clock signal 
and a linear ramp waveform, a PWM comparator, 
and a toggle flip-flop with output gating to switch 
the PWM signal alternately between the two 
outputs. 

With this circuitry already defined, a two pronged 
development effort was initiated: 1) to add addi- 
tional features required by most power supply 
designs and 2) to improve the utility of features 
already included within the 1524. The resultant 
block diagram for the SG1525A is shown in 
Figure 2. Two general comments should be made 
relative to the overall block diagram. First, in opti- 
mizing the output stage for bi-directional, low im- 



pedance switching, commitments had to be made 
as to whether the output should be high or low 
during the active, or ON state. Since this is applica- 
tion defined there are needs for both output states, 
so both were developed with the SG1525A device 
defined by an output configuration which is high 
during the ON pulse, and the SG1527A configured 
to remain high during the OFF state. This dif- 
ference is implemented by a mask option which 
eliminates inverter Q 4 (see Figure 3) for the 
SG1527A. In all other respects, the 1525A and 
1527A are identical and any description of the 
1525A characteristics apply equally to the 1527A. 
Second, a major difference between this new con- 
troller and the earlier 1524 is the deletion of the 
current limit amplifier. There are so many system 
considerations in providing current control that it 
is preferable to leave this as a user-defined external 
option and allocate the package pins to other, 
more universally requested functions. Current 
limiting possibilities are discussed further under 
shutdown options. 



Fig. 2 — The SG 1525A family represents a "second generation" of IC controllers. 



GROUND 
12 O- 




218 



"TOTEM-POLE" OUTPUT STAGE 

One of the most significant benefits in using the 
SG 1525A is its output configuration. For the first 
time it has been recognized in an IC controller that 
it is more difficult to turn a power switch off than 
turn it on. With the SG1525A,a high-current, fast 
transition, low impedance drive is provided for 
both turn-on and turn-off of an external power 
transistor or Power MOS. The circuit schematic of 
one of the two output stages contained within the 
device is shown in Figure 3. This is a two-state out- 
put, either Q 8 is on, forming a low saturation 
voltage pull-down, or Q 7 is on, pulling the output 
up to V c . Note that V c is a separate terminal from 
the V, supply to the rest of the device. 
This offers the benefits of potentially operating the 
output drive from a lower supply than the rest of 
the circuit for power efficiencies, jdecoupling of 
drive transients from more sensitive circuits, and a 
third terminal for extracting a drive signal. Note 
that even though V c can be set either higher or 
lower than Vj.the output cannot rise higher than 
approximately 1 1 / 2 volts below \A. 



Fig. 3 — One of two power output stages contained 
within the SG1525A which conduct alter- 
nately due to the internal flip-flop. 



™=-0 ©■' 





n Rtt o; 

CD — -ir£ 

, y 77^-+-'* 


'•'C 


i ^ ^ 



During the transition between states, there is a 
slight conduction overlap between source and sink 
which results in a pulse of current flowing from V c 
to ground. However, due to the high-speed design 
configuration of this stage, this current spike lasts 
for only about 100 ns. A typical current waveform 
at V c is shown in Figure 4. This transient will 
normally be decoupled from the rest of the control 
power by a 0.1 mF capacitor from V c to ground 
but it should not, otherwise, cause a problem 
unless very high frequency operation is contem- 
plated where it will contribute to overall device 
power dissipation, by becoming a significant por- 
tion of the total duty cycle. 

The output saturation characteristics of this stage 
are shown in Figure 5. The source transistor, Q 7 is 



a straight forward Darlington and its saturation 
voltage remains between 1 and 2V out to 400 mA 
under the assumption that V, > V cc . The sink 
transistor, Q 8 , however, has a non-uniform charac- 
teristic which needs explanation. At low sink 
currents, the 1mA current source through Q 5 
insures a very low saturation voltage at the output. 
As load current increases past 50 mA, Q 8 begins to 
come out of saturation for lack of base drive but 
only up to about 2V. Here diode D 2 becomes 
forward biased shunting a portion of the load 
current through Q 5 to boost the base current into 
Q 8 . With this circuit, the sink transistor can both 
support high peak discharge currents from a capa- 
citive load, as well as insure the low static hold-off 
voltage required for bipolar transistors. 

Fig. 4 - Current "spiking" on the V q terminal 
caused by conduction overlap between 
source and sink is minimized by high-speed 
design techniques. 




HORIZONTAL = 500ns/DIV 

Fig. 5 — The output saturation characteristics of 
the SG1525A provide both high drive cur- 
rent and low hold-off voltage. 




A typical output configuration for a push-pull bi- 
polar transistor power stage is shown in Fig. 6. With 
a steady state base drive current from the SG1 525A 
of 100mA, this stage should be able to switch 1 to 
5A of transformer primary current, depending 



219 



upon the choice of transistors. The sum of Rj and 
R2 determine the maximum steady state output 
current of the SG1525A while their ratio defines 
the voltage across C2 which, at turn off, becomes 
the reverse V BE for Qj . With the values given, the 
output current and voltage waveforms are shown in 
Figure 7 for a one microsecond pulse. If power 
MOS are used for the output switches as shown 
in Figure 8, the interfacing circuitry can become 
even simpler with only a small series gate resistor 
potentially required to damp spurious oscillations 
within the power device. 



Fig. 6 — A typical push-pull converter power stage 
using external bipolar power transistor 
switches. 




to the secondary side of an off-line power system, 
and to provide level shifting of drive signals for vi 
bridge and full bridge switching. The configuration 
of Figure 9 has a couple of important advantages. 
First, by connecting the drive transformer primary 
directly between the outputs of the SG1525A, no 
center-tap is needed and the full primary is driven 
with opposite polarities. Secondly, between each 
output pulse, both outputs are pulled to ground 
which effectively shorts the two ends of the pri- 
mary winding together coupling a low-impedance 
turn-off signal to the switching transistors. 

A useful single-ended configuration, typical of 
buck regulators, is shown in Figure 10. Here the 
SG1525A outputs are grounded and the PWM 
signal is taken from the V c terminal which switches 
close to ground during each clock period as the in- 
ternal source transistors are alternately sequenced. 



Fig. 8 — Replacing bipolar transistors with power 
MOS provides even greater simplicity due 
to the low driving impedances of the 
SG1525A in each transition. 




Fig. 7 — Base current waveforms (Figure 6 circuit) 
show the enhanced turn-on and turn-off 
current possible with the SG1525A. 




HORIZONTAL • 500ns/DIV 



Push-pull direct transformer drive is also particu- 
larly advantageous with SG1525A as shown in 
Figure 9. A version of this configuration is required 
for isolation when the control circuit is referenced 



Fig. 9 - The SG1525A is ideally suited for driving 
a low-power base drive transformer and 
eliminates the need for a primary cen- 
tertap. 



>«s o 




9,2 

I — 



220 



Fig. 10— A single-ended ground-referenced power 
stage for a flyback or boost regulator. 



-^ 





I 


R2 










^3 










♦v c 




1 1 






SG1525A 


B 


U 












GND 












12 

















POWER SUPPLY 



CONTROLLING 
START-UP 

Although the advantages of the SG1525A's output 
stage will often be reason enough for its selection, 
there are several other important and useful fea- 
tures incorporated within this product. One pro- 
blem previously overlooked in PWM circuits is 
keeping the output under control as the supply 
voltage is turned on and off. Undefined states, 
particularly the possibility of turning on an output 
before the oscillator is running, can be quite awk- 
ward, if not catastrophic. To prevent this, the 
SG1525A has incorporated an under-voltage 
lockout circuit which effectively clamps the out- 
puts to the off state with as little as 2 1 / 2 V of supply 



voltage which is less than the voltage required to 
turn the outputs on. This clamp is maintained until 
the supply reaches approximately 8V insuring that 
all the remaining SG1 525A circuitry is fully opera- 
tional prior to enabling the outputs. The clamp 
reactivates when the supply is lowered to approxi- 
mately 7.5V. There is about 500mV of hysteresis 
built in to eliminate clamp oscillation at threshold. 

Another important aspect of power sequencing is 
restraining the outputs from immediately com- 
manding a 100% duty cycle when they are acti- 
vated. This is accomplished by a slow turn on 
(soft-start) which is defined by an internal 50 mA 
current source in conjunction with an externally 
applied capacitor. The details of this power se- 
quencing system are shown in Figure 1 1 . 

0-3 and Q-4 are the output gates normally driven by 
the oscillator through D 2 to provide output blank- 
ing between pulses. (One of these transistors is 
shown as Q 2 in Figure 3). At low supply voltages, 
Q 2 conducts with base drive from the 20mA cur- 
rent source. Q 2 provides three functions. First, cur- 
rent through R 4 activates the output gates with 
minimum voltage drop. Second, current through 
R5 activates the shutdown transistor Q 5 holding 
the soft-start capacitor, C ss , discharged. Third, R 2 
provides a small bucking voltage across R 3 for 
hysteresis at the switch point. 

When the input voltage becomes high enough to 
provide a little more than one volt at the base of 
Qt, that transistor turns on. This turns off Q 2 , 
activating the outputs and allowing C ss to begin to 
charge from the internal 50 uA current source. The 
time to reach approximately 50% duty cycle will be 

t= ( 2volts ) c 
50 M A ° ss 



Fig. 11 - The internal power turn-on, soft-start, and shutdown circuitry of the SG1525A. 

v , o- -• -» 



2lz. 



CLOCK 
BLANKING 



[500/jA j 20AJA i REF 



6V 



Q3 j di. j 



OUTPUT GATES 



CD 



TO PWM 
' COMPARATOR 



f * — o , 

Q5 J SOFT-START I 




221 



POWER SUPPLY SHUTDOWN 

An important part of any PWM controller is the 
ability to shut it down at any time for a variety of 
reasons, including system sequencing requirements 
or fault protection. Several options are available to 
the user of the SG1525A, which require an under- 
standing of the capability of the shutdown termi- 
nal, pin 10. Referring to Figure 1 1 , the base of Q 5 
is turned on by a signal which is clamped to ap- 
proximately 1.4V by the action of Dj and the 
V B f£ of gates Q3 and Q4. This holds the outputs 
off and keeps Cgs discharged by Q5 which, with 
R9, becomes a 100,uA net current sink. 

If, during normal operation, pin 10 is pulled high, 
three things happen. First, the outputs are turned 
off within 200ns through D : . Second, the PWM 
latch is set by Q.(, so that even if the signal at pin 
10 were to disappear, the outputs would stay off 
for the duration of that period, being reset by the 
next clock pulse. Third, Q 5 is activated commenc- 
ing a 100/jA discharge of C ss . However, if the 
activation pulse on pin 10 has a duration shorter 
than '/ 3 of the clock period, the voltage on Cgg 
will remain high and soft-start will not be reacti- 
vated. Naturally, a fixed signal on pin 10 will 
eventually discharge C S s. recycling soft-start. 

Thus, the shutdown pin provides both sequencing 
capability as well as a convenient port for protec- 
tive functions, including pulse-by-pulse current 
limiting. 



REGULATING PWM PERFORMANCE 
IMPROVEMENTS 

The SG1525A also offers significant performance 
and application improvements in almost all of the 
additional basic functions of a PWM over those 
obtainable with earlier devices. A general descrip- 
tion of these features is outlined below: 

Reference Regulator: The output voltage of this 
regulator is internally trimmed to 5.1V ± 1% 
during manufacture, eliminating the need for ad- 
justing potentiometers in most applications. 



Error Amplifier: SG1525A uses the same basic 
transconductance amplifier as the SG1524 with an 
important difference: it is powered by V, rather 
than V RE p- Now the input common-mode range 
includes V REF eliminating the need for a voltage 
divider with its attendant tolerances. An additional 
feature relative to the error amplifier is that the 
shutdown circuitry feeds into a separate input to 
the PWM comparator allowing pulse termination 
without affecting the output of the error amplifier 
which might have a slow recovery, depending upon 
the external compensation network selected. An 
important benefit of a transconductance amplifier 
is the ease with which its current mode output can 
be over-ridden by other external controlling 
signals. 



PWM Comparator: The significant benefit of the 
SG1525A's PWM comparator is in its following 
latch. A common problem with earlier devices was 
that any noise or ringing on the output of the error 
amplifier would affect multiple crossings of the 
oscillator ramp signal resulting in multiple pulsing 
at the comparator's output. The SG1525A's latch 
terminates the output pulse with the first signal 
from the comparator, insuring that there can be 
only a single pulse per period, removing all jitter or 
threshold oscillation from the system. Another 
important advantage of this latch is the ability to 
easily implement digital or pulse-by-pulse current 
limiting by merely momentarily activating the 
shutdown circuitry within the SG1525A. This 
could be as simple as connecting pin 10 to a 
ground-referenced current sensing resistor. For 
greater accuracy, some added gain may be advanta- 
geous. Once a current signal causes shutdown, the 
output will remain terminated for the duration of 
the period, even though the current signal is now 
gone. An oscillator clock signal resets the latch to 
start each period anew. 

Oscillator: The functions of the oscillator within 
the SG1525A have been broadened in two import- 
ant aspects. One is the addition of a synchroniza- 
tion terminal, pin 3, allowing much easier inter- 
facing to an external clock signal or to synchronize 
multiple SG1525A's together. The other is the 
separation of the oscillator's discharge network 
from its charging current source for deadtime 
control. Reference should be made to the schematic 
of Figure 12 for an understanding of the operation 
of this circuit. The heart of this oscillator is a 
double-threshold comparator, Q 7 and Qg, which 
allows the timing capacitor to charge to an upper 
threshold by means of the current source defined 
by R T and mirrored by Q1 and Q2. The compara- 
tor then switches to a lower threshold by turning 
on Qjo and discharges C T through Q3 and Q4 with 
a rate defined by R D . As long as Cy is discharging, 
the clock output is high, blanking the outputs. 

Since the overall oscillator frequency is defined by 
the sum of the charge and discharge times, there 
are three elements now in the frequency equation 
which is approximately : 

C T (.07 R T + 3 R D ) 

External synchronization can easily be accom- 
plished with a 2.8V positive pulse at pin 3. This 
will turn on Q9, lowering the comparator threshold 
below wherever the voltage on C T may happen to 
be. Two factors should be considered: First, the 
voltage on C T determines the amplitude of the 
PWM ramp, and if the sync occurs too early, the 
loop gain will be higher and the resolution may be 
worse. Second, the sync circuit is regenerative 
within 200ns; and, while a wider pulse can be 
used, Cj will not begin to recharge as long as the 
sync pin is high. For synchronizing multiple 
SG1525A devices together, one need only to 
define a master with the correct R-fC-p time cons- 
tant, connect its output pin to the slave sync pins, 
and set each slave R T C T for a time constant 10- 
20% longer than the master. 



222 



Fig. 12 - A simplified schematic of the SG1525A's oscillator circuitry. 




RAMP 
TO ,-WM 



Fig. 13 - 200W, Off-Line Forward Converter. 




223 



OFF-LINE, FORWARD 



A 200 WATT, 
CONVERTER 

The ease of interfacing the SG1525A into a prac- 
tical power supply system can be illustrated by the 
off-line, power converter shown in Figure 13. This 
200W supply places the control circuitry on the 
primary side of the power transformer where direct 
coupling can be used to drive the power switch. 
While simplifying the drive electronics, this con- 
figuration usually requires an isolated voltage feed- 
back signal which is most easily accomplished by 
an optocoupler driven by some type of voltage re- 
gulator IC such as a L123 or LM723. One other 
undefined block in Figure 13 is the auxiliary power 
supply which supplies the low voltage, low current 
bias supply for the SG1 525A and the drive for Q x . 
the power switch. The choice of the SGSP479 
power MOS for this switch keeps the total power 
requirements from the auxiliary supply at less than 
1W; readily implemented with a small, line-driven 
transformer. 

This converter is designed to operate at 150kHz 
which is accomplished by running the SG1525A at 
300kHz and using only one of the outputs. This 
also automatically insures that the duty cycle can 
never be greater than 50%, a requirement of the 
power transformer in this configuration. The high 
operating frequency allows the output filter's 
roll-off to be set at 12kHz, greatly simplifying the 
overall loop stability considerations as adequate 
response can be achieved with only the single-pole 
compensation of the error amplifier provided by 
the 0.05/uF capacitor on pin 9. 

The totem-pole output of the SG1525A is used to 
advantage to drive Qj by providing a 400 mA peak 
current to charge and discharge the power MOS 
gate capacitance while keeping overall power dissi- 
pation low. Waveform photographs of this opera- 
tion are shown in Figure 14. 





Fig. 14— Current and voltage waveforms for the 
200W off-line forward converter with a 
SG1525A direct driven power MOS 
switch (operating frequency is 150kHz 
with output current equal to 40A). 




Vs/div 
a) Wavelorms o f i 



When operating at full load, the efficiency of this 
converter is 73% with by far the greatest power 
losses occurring in the output rectifiers-even 
though Schottky devices have been selected. 

Switching tosses have been minimized by the fast 
current transitions, primarily defined by the 
leakage inductance of the transformer. Although 
this switching time could probably be even further 
reduced, there could be problems with current 
spikes during rise time due to Schottky rectifier 
capacitance. 

Current limiting for this converter is provided by 
measuring the current in SGSP479 with the 0.1 Q. 
resistor in series with the source and using this 
voltage to activate the shutdown circuitry within 
the SG1525A. While this will provide a fast-acting 
short circuit protection on a pulse-by-pulse basis, 
a comparator may need to be added for a more 
accurate current limit threshold. 



224 



Fig. 15 - 500W, 100 kHz Half-Bridge Schematic. 



<>-: 



1*. 



-i— Htt" 




Hh 



" IP" 



<DO 



-Ch 




Transformer Winding Data 

500W, 100kHz, Off-Line, Half-Bridge Converter: 

T1 Core: Ferrox 486T250-3C8 
Pri: 14T #22AWG 
Sec (2): 7T #22AWG 

T2 Core: Ferrox EC52-3C8 (EE) 

Pri: 14T, 2 layers, 2 #16AWG in parallel 

Sec (2): each 2T, C.T., copper strap 0.01" x0.8" 



T3 Core: Ferrox 486T250-3C8 
Pri: 1T 
Sec: 20T,C.T. #22AWG 

T4 117V/220V, 25V, 0.1 5A, 50-60 Hz 

L1 Core: Ferrox IF30-3C8 

4 turns, 5 #1 2AWG in parallel 



500 WATT, OFF-LINE. 
CONVERTER 



The circuit shown in Figure 15 uses a pair of 
SGSP479 power MOS in a half-bridge configura- 
tion with the SG1525A chip referenced to the 
secondary side of the power transformer. 
The power MOS gates are driven directly from the 
control chip output through step down and iso- 
lation transformer T1. The SG1525A output 
terminals (pins 11 and 14) provide active pull-up 
and pull-down (dual source/sink) for the primary 
of T1 . This provides the fast, high current turn-on 
and turn-off pulses needed for the power MOS 
gates. In addition, the two ends of the primary 
windings are shorted to ground during deadtime, 



HALF-BRIDGE which prevents accidental turn-on by transients. 
Note that the current supplied by the SG1525A 
outputs drops to a small value when the gate capa- 
citance has been charged or discharged to the 
desired gate voltage. Damping resistors with series 
blocking capacitors across the two secondaries of 
T1 minimize ringing due to the power MOS gate 
capacitance and the inductance of T1 and lead in- 
ductance, particularly during deadtime. 

Deadtime for the SG1525A is set very simply by a 

single resistor between pins 5 and 7. Only a small 

amount of deadtime is needed since the power 

MOS have no storage time and a very short delay 

time. 

Slow turn-on is accomplished by a single capacitor 

at pin 8. 



225 



Current limiting is provided by current transformer 
T3 in series with the primary of the power trans- 
former T2. The signal is rectified, threshold ad- 
justed and sent to the shutdown terminal, pin 10, 
of theSG 1525A. 

Waveforms of the converter are shown in the scope 
photos of Figure 16. Current rise and fall times are 
20ns and 10ns. 

Fig. 16 - Performance waveforms for the half- 
bridge, 500W, 100kHz converter with 
output current of 80A. 



,A- 



o*- 




2^s/div 
a) Waveforms of i c , \ G V G 





IMPROVED PERFORMANCE; 
LESS COMPLEXITY 

Although power supply designers for some time 
now have had an ever widening inventory of IC 
components available to ease their design tasks, the 
final measure of improvement has to be in terms of 
system performance versus cost. With fewer in- 
terface components to the power stages, freedom 
from potentiometer adjustments, protected start-up 
and shut-down, a built in soft-start network and 
several additional system-level features, the 
SG1525A provides a significant contribution to 
both performance and costs while simultaneously 
making the designer's task easier. With these ac- 
complishments, it is clear that this device truly 
does represent a step-function improvement, in- 
troducing a second-generation of power control 
components. 



© 1984 by Unitrode Corporation. All rights reserved. 
This bulletin, or any part or parts thereof, must 
not be reproduced in any form without permission 
of the copyright owner. 



226 



A DESIGNER'S GUIDE TO THE 
L200 VOLTAGE REGULATOR 



Delivering 2A at a voltage variable from 2.85V to 36V, the L200 voltage regulator is a versa- 
tile device that simplifies the design of linear supplies. This design guide describes the oper- 
ation of the device and its applications. 



The introduction of integrated regulator circuits 
has greatly simplified the work involved in design- 
ing supplies. Regulation and protection circuits 
required for the supply, previously realized using 
discrete components, are now integrated in a single 
chip. This has led to significant cost and space 
saving as well as increased reliability. Today the 
designer has a wide range of fixed and adjustable, 
positive and negative series regulators to choose 
from as well as an increasing number of switching 
regulators. 

The L200 is a positive variable voltage regulator 
which includes a current limiter and supplies up 
to 2A at 2.85 to 36V. 

The output voltage is fixed with two resistors or, if 
a continuously variable output voltage is required, 
with one fixed and one variable resistor. 

The maximum output current is fixed with a low 
value resistor. The device has all the characteristics 
common to normal fixed regulators and these are 
described in the datasheet. The L200 is particularly 
suitable for applications requiring output voltage 
variation or when a voltage not provided by the 
standard regulators is required or when a special 
limit must be placed on the output current. 

The L200 is available in two packages: 

Pentawatt — Offers easy assembly and good relia- 
bility. The guaranteed thermal resistance 
< R th j-case' IS 3 r C/W (typically 2 C C/W) while if 
the device is used without heatsink we can con- 
sider a guaranteed junction-ambient thermal 
resistance of 50 C C'W. 



TO-3 — For professional and military use or where 
good hermeticity is required. 
The guaranteed junction-case thermal resist- 
ance is 4 C C/W, while the junction-ambient 
thermal resistance is 35°C/W. 



The junction-case thermal resistance of this 
package, which is greater than that of the 
Pentawatt, is partly compensated by the lower 
contact resistance with the heatsink, especially 
when an electrical insulator is used. 

CIRCUIT OPERATION 

As can be seen from the block diagram (fig, 1) the 
voltage regulation loop is almost identical to that 
of fixed regulators. The only difference is that the 
negative feedback network is external, so it can be 
varied (fig. 3). The output is linked to the refer- 
ence by: 



V n 



'ref 



(1 + 



R2 
R1 



(1) 



Considering V out as the output of an operational 
amplifier with gain equal to G v = 1 + R2/R1 and 
input signal equal to V ref , variability of the output 
voltage can be obtained by varying R1 or R2 (or 
both). It's best to vary R1 because in this way the 
current in resistors R1 and R2 remains constant 
(this current is in fact given by V ref /R1). 

(Equation (1) can also be found in another way 
which is more useful in order to understand the 
descriptions of the applications discussed. 

Vout= R1 ii + R2 i 2 

and since in practice i^ > i 4 O4 has a typical value 
of 10 /uA) we can say that 

V,, 



V r 



Therefore 



R1 i x + R2 i x with i 1 = 



'ref 



R1 



Vout= -~V ref + V ref = V ref (1 ' R2 



R1 



R1 



In other words R1 fixes the value of the current 
circulating in R2 so R2 is determined. 



227 



Fig. 1 - Block diagram 



O ■ 

NPUT 



t 



PASS 

ELEMENT 



S.O.A 
PROTECTION 



-CURRENT 
/LIMITING 



CURRENT 
SOURCE 



REFERENCE 



ERROR 
AMPLIFIER 



THERMAL 
PROTECTION 



VOLTAGE 
' REFERENCE 



CJ3 GROUND 



Fig. 2 - Schematic diagram 




Fig. 3 



v 

f— « 1 COMP 




'♦y 



228 



Overload protection 

The device has an overload protection c 
which limits the current available. 

Referring to fig. 2, R24 operates as a cu 
sensor. When at the terminals of R24 there 
voltage drop sufficient to make O.20 conduct 
begins to draw current from the base of the 
transistor (darlington formed by Q22 and 
and the output current is limited. The iim 
pends on the current which Q21 injects n t> 
base of Q20. This current depends on the dror 
and the temperature which explains the tret 
the curves in fig. 4. 

Fig. 4 



' is a 
Q19 
ower 
Q23) 
t de- 
3 the 
}-out 
id of 




Thermal protection 

The junction temperature of the device may reach 
destructive levels during a short circuit at the out- 
put or due to an abnormal increase in the ambient 
temperature. To avoid having to use heatsmks 
which are costly and bulky, a thermal protection 
circuit has been introduced to limit the output 
current so that the dissipated power does not bring 
the junction temperature above the values allowed. 
The operation of this circuit can be summarized 
as follows. 

In Q17 there is a constant current equal to: 



Current limitation 

The innovative feature of this device is the possi- 
bility of acting on the current regulation loop, i.e. 
of limiting the maximum current that can be 
supplied to the desired value by using a simple 
resistor (R3 in fig. 2). Obviously if R3 = the 
maximum output current is also the maximum 
current that the device can supply because of its 
internal limitation. 

The current loop consists of a comparator circuit 
with fixed threshold whose value is V sc . This com- 
parator intervenes when l • R3 = V sc , hence 

v sc 
l = ~— (V sc is the voltage between pins 5 and 

R 3 
2 with typical value of 0.45V). 

Special attention has been given to the comparator 
circuit in order to ensure that the device behaves as 
a current generator with high output impedance. 



TYPICAL APPLICATIONS 
Programmable current regulator 

Fig 5 shows the device used as current generator. 
In this case the error amplifier is disabled by short- 
circuiting pin 4 to ground. 



Fig. 5 




The output current l is fixed by means of R: 



R 

The output voltage can reach a maximum value 
= V; - 2V (V^Qp depends on l ). 



V; 



V 



drop 



V 



ref 



■ V 



BE17 



R17 + R16 



(V ref = 2,75V typi 



The base of Q18 is therefore biased at 


V BE18 = 


_^e L -_VBEl7_. R16 ^ 

R16 + R17 


Therefore ->* 


T -- 2b C Q18 is off (sir 


needed fo; 


: to st'Kt conducting; - 


of a silicon 


.-'^■■TOr dec-eases by uo 


Q18 starts;. 


induct -:q at the junction 


_ 


600-3b0 _ . r . 



300 mV is 



'BE 
' C 



Programmable voltage regulator 

Fig. 6 shows the device connected as a voltage 
regulator and the maximum output current is the 
maximum current that the device can supply. The 
output voltage V Q is fixed using potentiometer R2. 
The equation which gives the output voltage is as 
follows: 



V,. 



V 



ref 



(1 + -— ) 
R1 



By substituting the potentiometer with a fixed 
resistor and choosing suitable values for R 1 and R2, 
it is possible to obtain a wide range of fixed output 
voltages. 



229 



Fig. 6 



Fig. 7 







=1 






, 


L200 


2 




t 






' ' t 



^=A^ 




0.22 ; j 



I e 2 o n. 



± 



The following formulas and tables can be used tocal- Digitally selected regulator with inhibit 

culate some of the most common output voltages. The output voltage of the device can be regulated 

digitally as shown in fig. 8. The output voltage 
depends on the divider formed by R5 and a combi- 
nation of R1, R2, R3 and P2. The device can be 
switched off with a transistor, 
and the When the inhibit transistor is saturated, pin 2 is 
brought to ground potential and the output voltage 
does not exceed 0.45V. 



Having fixed a certain V , using the previous 
formula, the maximum value is: 



'ref max 



(1 



R2 

~rt; 



minimum value is: 



V. 



= V 



ref m 



nd + 



R2, 



R1 



) 



The table below indicates resistor values for typical 
output voltages: 



V ± 4% 


R1 ± 1% 


R2 ± 1% 


5V 


1.5 kn 


1.2 kn 


12V 


1 kn 


3.3 kn 


15V 


750 n 


3.3 kn 


18V 


330 n 


1.8 kn 


24V 


510 n 


3.9 k.Q 



Fig. 8 







5 










. 1 


L200 


2 ikfl 




> 

i ■ 








\ 


: v 




3 




1* 




f: 

it 


;0.22.(jF 


R1 [ 


]r2[]r3[ 


I /inputs 


0.1 fl 


















S-25 


43/2 



Programmable current and voltage regulator 

The typical configuration used by the device as a 
voltage regulator with external current limitation is 
shown in fig. 7. The fixed voltage of 2.77V at the 
terminals of R1 makes it possible to force a cons- 
tant current across variable resistor R2. If R2 is 
varied, the voltage at pin 2 is varied and so is the 
output voltage. 

The output voltage is given by: 



V = v re 



(1 + 



R2 
R1 



), with V ref = 2.77V typ 



and the maximum output current is given by: 



V 



5-2 



R3 



with V 5 _ 2 = 0.45V typ. 



Reducing power dissipation with dropping 
resistor 

If may sometimes be advisable to reduce the power 
dissipated by the device. A simple and economic 
method of doing this is to use a resistor connected 
in series to the input as shown in fig. 9. The input- 
output differential voltage on the device is thus 
reduced. 

Fig. 9 



Ov„ 



To maintain a sufficient current for good regu- 
lation the value of R1 should be kept low. When 
there is no load, the output current is V ref /R1. 
Suitable values of R1 are between 500n and 1.5 
kn. If the load is always present the maximum 
value for R1 is limited by the current value(IO^A) 
at the input of the error amplifier (pin 4). 




230 



The formula for calculating R is as follows: 



V; 



<V r 



V 



drop 



Therefore the output reaches its nominal value 



after the time t n 



V n -V 5 



Where V drop is the minimum differential voltage 
between the input and the output of the device at 
current l . V in min is the minimum input voltage. 
V is the output voltage and l the output current. 

With constant load, resistor R can be connected 
between pins 1 and 2 of the IC instead of in series 
with the input (fig. 10). In this way, part of the 
load current flows through the device and part 
through the resistor. This configuration can be 
used when the minimum current by the load is: 



/ drop 



(V o -0.45) 
045 



R -= 



CVpR 
0.45 



(instant by instant) 



Light controller 

Fig. 12 shows a circuit in which the output voltage 
is controlled by the brightness of the surrounding 
environment. Regulation is by means of a photo- 
resistor in parallel with R1. In this case, the output 
voltage increases as the brightness increases. The 
opposite effect, i.e. dimming the light as the 
ambient light increases, can be obtained by con- 
necting the photoresistor in parallel with R2. 



Fig. 10 



Fig. 12 








= 1 








L 200 




1 


i-i 


J_ 


3 


R 1 -- 1 * 


S - ?S2I 



Soft start 

When a slow rise time of the output voltage is re- 
quired, the configuration in fig. 1 1 can be used. The 
rise time can be found using the following formula: 
CVo R 
ton= ^045 

At switch on capacitor C is discharged and it keeps 
the voltage at pin 2 low; or rather, since a voltage 
of more than 0.45V cannot be generated between 
pins 5 and 2, the V follows the voltage at pin 2 at 
less than 0.45V. 



Fig. 11 





*l 


I 


+ V '°X 

T 


L 200 - 


1 
2 i k n. 

R [ 


_ 


3 U^t 


_J 


1 


_L S- 39 2 



Capacitor C is charged by the constant current i c 
V C1 - 



Light dimmer for car display 

Although digital displays in cars are often more 
aesthetically pleasing and frequently more easily 
read they do have a problem. Under varying am- 
bient light conditions they are either lost in the 
background or alternatively appear so bright as to 
distract the driver. With the system proposed here, 
this problem is overcome by automatically adjust- 
ing the display brightness during daylight condi- 
tions and by giving the driver control over the 
brightness during dusk and darkness conditions. 

The circuit is shown in fig. 13. The primary supply 
is shown taken straight from the car battery 
however it is worth noting that in a car there is 
always the risk of dump voltages up to 120V and 
it is recommended that some form of protection is 
included against this. 

Under daylight conditions i.e. with sidelights off 

and T1 not conducting the output of the device is 

determined by the values of R1, R2 and the photo- 

resitor (PTR). The output voltage is given by 

R2 

V out = V ref H + ) 

out ret PTR//R1 

tf the ambient light intensity is high, the resistance 
of the photoresistor will be low and therefore 
V out will be high. As the light decreases, so V out 
decreases dimming the display to a suitable level. 



231 



Fig. 13 



SIDELIGHT- SWITCH 




In duskconditions.when the sidelights are switched 
on, T1 starts to conduct with its conduction set by 
the potentiometer. With the potentiometer wiper 
at its uppermost position the sidelights are at their 
brightest and current through T1 would be a 
minimum. With the wiper at its lowest position ob- 
viously the opposite conditions apply. 

The current through T1 is felt at the summing 
node A along with the currents through R2 and the 
parallel network R1, PTR. Since V ref is constant 
the current flowing through R1, PTR must also be 
constant. Therefore any change in the current 
through T1 causes an equal and opposite change in 
the current through R2. Therefore as l T1 increases, 
V out decreases i.e. as the brightness of the side- 
lights is increased or decreased so is the brightness 
of the display. 

The values of R2 and PTR should be selected to 
give the desired minimum and maximum brightness 
levels desired under both automatic and manual 
conditions although the'minimum brightness under 
manual conditions can also be set by the maximum 
current flowing through T1 and, in any case, this 
should not exceed the maximum current through 
R2 under automatic operation. 

The circuit shown with a small modification can 
also be used for dimmers other than in a car. Fig. 
15 shows the modification needed. The zener 
diode should have aV F >2.5Vatl = 10 /iA. 



Fig. 14 



Fig. 15 



Vref 



PTR 




R2 




S4- 



Higher input or output voltages 

Certain applications may require higher input or 
output voltages than the device can produce. The 
problem can be solved by bringing the regulator 
back into the normal operating units with the help 
of external components. 

When there are high input voltages, the excess 
voltage must be absorbed with a transistor. Figs. 16 
and 17 show the two circuits: 

Fig. 16 




Fig. 17 




" z T T 



232 



The designer must take into account the dissipated 
power and the SOA of the prereguiation transistor. 
For example, using the BDX53, the maximum 
input voltage can reach 56V (fig. 16). In these 
conditions we have 20V of V CE on the transistor 
and with a load current of 2A the operation point 
remains inside the SOA. The prereguiation used in 
fig. 16 reduces the ripple at the input of the device, 
making it possible to obtain an output voltage with 
negligible ripple. 

If high output voltages are also required, a second 
zener, V z , is used to refer the ground pin of an IC 

Fig. 18 




■J Q22UF 



Fig. 19 




Fig. 20 



to a potential other than zero; diode D1 provides 
output shortcircuit protection (fig. 18). 

Positive and negative voltage regulators 

The circuit in fig. 19 provides positive and negative 
balanced, stabilized voltages simultaneously. The 
L200 regulator supplies the positive voltage while 
the negative is obtained using an operational am- 
plifier connected as follower with output current 
booster. 

Tracking of the positive voltage is achieved by 
putting the non-inverting input to ground and 
using the inverting input to measure the feedback 
voltage coming from divider R1 -R2. 

The system is balanced when the inputs of the 
operational amplifier are at the same voltage, or, 
since one input is at fixed ground potential, when 
the voltage of the intermediate point of the divider 
goes to Volts. This is only possible if the negative 
voltage, on command of the op-amp, goes to a 
value which will make a current equal to that in 
R1 flows in R2. The ratio which expresses the 
negative output voltage is: 

R2 



V 



V + 



R1 



(If R2= R1, we'll get V"= V + ) 



Since the maximum supply voltage of the op amp 
used is ± 22V, when pin 7 is connected to point B 
output voltages up to about 18V can be obtained. 
If on the other hand pin 7 is connected to point A, 
much higher output voltages, up to about 30V, 
be obtained since in this case the input voltage can 
rise to 34V. 

Fig. 20 shows a diagram is which the L165 power 
op amp is used to produce the negative voltage. In 
this case (as in fig. 19) the output voltage is limited 
by the absolute maximum rating of the supply 
voltage of the L165 which is ± 18V. Therefore to 
get a higher V out we must use a zener to keep the 
device supply within the safety limits. 

If we have a transformer with two separate secon- 
daries, the diagram of fig. 21 can be used to obtain 
independent positive and negative voltages. The 
two output diodes, D1 and D2, protect the devices 
from shortcircuits between the positive and nega- 
tive outputs. 




A: for ± 18V < V; < 32V 

Note: V z must be chosen in order 
to verify 2 V r V z = 36V 

B: for V) < + 18V 



233 



Fig. 21 



Fig. 23 








— 






! 




■ 










r-^i i i 








i 


: 












i 










I 
























i 











Compensation of voltage drop along the 
wires 

The diagram in fig. 22 is particularly suitable when 
a load situated far from the output of the regulator 
has to be supplied and when we want to avoid the 
use of two sensing wires. In fact, it is possible to 
compensate the voltage drop on the line caused by 
the load current (see the two curves in fig. 23 and 
24). R K transforms the load current l L into a pro- 
portional voltage in series to the reference of the 
L200. R K 1 1 is then amplified by the factor 

R2 + R1 _ 



R1 
With the values of R z , R2 and R1 known, we get: 

R = R RJ 

R1 +R2 
Rz, R1 and R2 are assumed to be constant. 
If R K is higher than 10 n, the output voltage 
should be calculated as follows: 



lr 



<K 



+ v r 



R2+ R1 
R1 



Fig. 24 













I 




























































































— 

















Fig. 22 





234 



Motor speed control 

Fig. 25 shows how to use the device for the speed 
control of permanent magnet motors. The desired 
speed, proportional to the voltage at the terminal 
of the motor, is obtained by means of R1 and R2. 



Vr 



To obtain better compensation of the internal mo- 
tor resistance, which is essential for good regu- 
lation, the following equation is used: 



R3 < 



R1 
R2 



This equation works with infinite R4. If R4 is 
finite, the motor speed can be increased without 
altering the ratio R2/R1 and R3. Since R4 has a 
constant voltage (V ref ) at its terminals, which does 
not vary as R4 varies, this voltage acts on R2 as a 
constant current source variable with R4. The volt- 
age drop on R2 thus increases, and the increase is 
felt by the voltage at the terminals of the motor. 
The voltage increase at the motor terminals is: 

v ref 

V M = — • R2. 

M R4 +R3 

A circuit for a30Wmotor with R M = 4tt, R1 



R2 = 4.3 kn, R4 
been realized. 



Fig. 25 



«i„o - 



1 kn, 

22 kH and R3 = 0.82n has 




^ — 



i 2 = _ i 3 with i 3 : 



R3 



-(for X r < R3) -Therefore: 



v n =R2 



R3 



R2. 



An application is shown in fig. 27. If the DC level 
is to be varied but not the AC gain, R1 should be 
replaced by a potentiometer. 



Fig. 26 




Fig. 27 



V' Kn 



Power amplitude modulator 

In the configuration of fig. 26 the L200 is used to 
send a signal onto a supply line. Since the input 
signal V, is DC decoupled, the V is defined by: 

R2 
R1 



V, 



V 



ref 



(1 + 



-) 



The amplified signal V, whose value is: 

G v =--^- 2 - 
R3 

is added to this component. By ignoring the current 
entering pin 4, we must impose ij = i 2 + i3 (1) 
and since the voltage between pin 4 and ground 
remains fixed (V ref ) as long as the device is not in 
saturation, ij = and equation (1) becomes: 



HIGH CURRENT REGULATORS 

To get a higher current than can be supplied by a 
single device one or more external power tran- 
sistors must be introduced. The problem is then to 
extend all the device's protection circuits (short- 
circuit protection, limitation of Tj of external 
power devices and overload protection) to the 
external transistors. Constant current or foldback 
current limitation therefore becomes necessary. 

When the regulator is expected to withstand a 
permanent shortcircuit, constant current limitation 
becomes more and more difficult to guarantee as 
the nominal V increases. This is because of the 
increase in V CE at the terminals of the transistor, 
which leads to an increase in the dissipated power. 
The heatsink has to be calculated in the heaviest 
working conditions, and therefore in shortcircuit. 
This increases weight, volume and cost of the 
heatsink and increase of the ambient temperature 
(because of high power dissipation). Besides heat- 
sink, power transistors must be dimensioned for 
the short-circuit. 



235 



This type, of limitation is suited, for example, 
with highly capacitive loads. Efficiency is increased 
if preregulation is used on the input voltage to 
maintain a constant drop-out on the power ele- 
ment for all V out , even in shortcircuit. Foldback 
limitation, on the other hand, allows lighter short- 
circuit operating conditions than the previous case. 
The type of load is important. 

If the load is highly capacitive, it is not possible to 
have a high ratio between l max and l sc because at 
switch-on, with load inserted, the output may not 
reach its nominal value. 

Other protection against input shortcircuit, mains 
failure, overvoltages and output reverse bias can be 
realized using two diodes, D1 and D2, inserted as 
indicated in fig. 28. 



Fig. 28 







Use of a PNP power transistor 

Fig. 29 shows the diagram of a high current supply 
using the current limitation of the L200. The out- 
put current is calculated using the following 
formula: 



lr 



V 



SC 



0.45V 



4.5A 



R sc o.m 

Constant current limitation is used; so, in output 
shortcircuit conditions, the transistor dissipates a 
power equal to: 

Vsc 



PD ■■ 



V;-I r 



; V : 



^SC 



Fig. 29 




The operating point of the transistor should be 
kept well within the SOA; with Rsc= O.m, V, 



must not exceed 20V. Part of the l crosses the 
transistor and part crosses the regulator. 

V F 
The latter is given by: Ireq = 'b 



'BE 



Ft 



where lg is the base current of the transistor 
(-100 mA at l c = 4A) and V BE is the base-emitter 
voltage (-1V at l c = 4A); with R = 2.5n, Ireq= 
s 500 mA. 

Use of an IMPN power transistor 

Fig. 30 shows the same application as described in 
figure 29, using an NPN power transistor instead 
of a PNP. In this case an external signal transistor 
must be used to limit the current. Therefore: 



V 



BE Ql 



R 



SC 



As regards the output shortcircuit, see par. 1.5. 
Fig. 30 




t.J^., j 



l ]820Jl|' 4.7KQ, 



r 



12V 4A Power supply 

The diagram in fig. 31 shows a supply using the 
L200 and the BD705. The 1 kn potentiometer, 
PT1, together with the 3.3 kil resistor are used for 
fine regulation of the output voltage. 

Current limitation is of the type shown in fig. 32. 
Trimmer PT2 acts on strech AB of characteristic. 
With the values indicated (PT2= 1 kn, PT3= 470f2, 
R = 3 kn), currents from 3 to 4A can be limited. 
The field of variation can be increased by increas- 
ing the value of R sc or by connecting one terminal 
of PT3 to the base of the power transistor, which, 
however, provides less stable limitation. If section 
AB is moved, section BC will also be moved. 

The slope of BC can be varied using PT3. The 
voltage level at point B is fixed by the voltage of 
the zener diode. The capacitor in parallel to the 
zener ensures correct switch-on with full load. 
The BD705 should always be used well within its 
safe operating area. If this is not possible two or 
more BD705s should be used, connected in parallel 
(fig. 33). 

Further protection for the external power tran- 
sistor can be provided as shown in fig. 34. The 
PTC resistor, whose temperature intervention point 
must prevent the Tj of the power transistor from 
reaching its maximum value, should be fixed to 
the dissipator near the power transistor. Dimen- 
sioning of R A and R B depends on the PTC used. 



236 



Fig. 31 



'•SENSE 




- O 1 * 



Fig. 32 



Fig. 34 



Vo 














(V) 










4 








































^ '/! 












^ "" 


/ ' ' 






,-- 




c/ 


/ : 










Kr 


lo 




'< 



"Tgr 




:@- 



F/g. 33 




I.— I 



Voltage regulator from OV to 16V - 4.5A 

Fig. 35 shows an application for a high current 
supply with output voltage adjustable from OV to 
16V, realized with two L200 regulators and an 
external power transistor. With the values in- 
dicated, the current can be regulated from 2A to 
4.5A by potentiometer PT2. PT1 , on the other 
hand, is used for constant current or foldback 
current limitation. The integrated circuit IC2, 
which does not require a heatsink and has excellent 
temperature stability, is used to obtain the OV 
output. It is connected so as to lower pin 3 of IC1 
until pin 4 reaches OV. Q1 and Q2 ensure correct 
operation of the supply at switch-on and switch- 
off. 



237 



Fig. 35 




Power supply with V„= 2.8 to 18V, l„= 
to 2.5A 

The diagram in fig. 36 shows a supply with output 
voltage variable from 2.8V to 18V and constant 
current limitation from OA to 2.5A. The output 
current can be regulated over a wide range by 
means of the op. amp. and signal transistor TR2. 
The op. amp. and the transistor are connected in 
the voltage-current converter configuration. The 
voltage is taken at the terminals of R3 and con- 
verted into current by PT 2 . 

I n is fixed as follows: 



R4 I, 



ll (*) 



Ur = 



V 



SC 



PT 2 R2 

When li = l sc , the regulator starts to operate as a 



current generator. By making 
get: 

R4 ,„ .-., 

; therefore l n = 



) equal to (**) we 



SC 



v 



SC 



' PT, 



PT 2 R2 ° R2 • R4 ' 2 ' 

Diodes D1 and D2 keep transistor TR 2 in linear 
condition in the case of small output currents. 
If it is not necessary to limit the current to zero, 
one of the diodes can be eliminated: the second 
diode could also be eliminated if TRj were a 
darlington instead of a transistor. 

The op. amp. must have inputs compatible with 
ground in order to guarantee current limitation 
even in shortcircuit. With a negative voltage avail- 
able, even of only a few volts, current limitation is 
simplified. 



Fig. 36 




238 



LAYOUT CONSIDERATIONS 

The performance of a regulator depends to a great 
extent on the case with which the printed circuit is 
produced. There must be no impulsive currents 
(like the one in the electrolytic filter capacitor at 
the input of the regulator) between the ground pin 
of the device (pin 3) and the negative output 
terminal because these would increase the output 
ripple. Care must also be taken when inserting the 
resistor connected between pin 4 and pin 3 of the 
device. 

The track connecting pin 3 to a terminal of this 
resistor should be very short and must not be 

Fig. 37 



crossed by the load current (which, since it is gene- 
rally variable, would give rise to a voltage drop on 
this stretch of track, altering the value of V ref and 
threfore of V . 

When the load is not in the immediate proximity 
of the regulator output "+ sense" and "— sense" 
terminals should be used (see fig. 37). By connec- 
ting the "+ sense" and "— sense" terminals directly 
at the charge terminals the voltage drop on the 
connection cable between supply and load are 
compensated. Fig. 37 shows how to connect 
supply and load using the sensing clamps terminals. 




O 



R L n *c 



Fig. 38 




6 6 6 6 



HEATSINK DIMENSIONING 

The heatsink dissipates the heat produced by the 
device to prevent the internal temperature from 
reaching values which could be dangerous for 
device operation and reliability. 

Integrated circuits in plastic package must never 
exceed 150°C even in the worst conditions. This 
limit has been set because the encapsulating resin 
has problems of vitrification if subjected to tem- 
peratures of more than 150°C for long periods or 
of more than 170°C for short periods (24 h). In 
any case the temperature accelerates the ageing 
process and therefore influences the device life; an 
increase of 10°C can halve the device life. A well 
designed heatsink should keep the junction tem- 
perature between 90°C and 110°C. Fig. 39 shows 



the structure of a power device. As demonstrated 
in thermodynamics, a thermal circuit can be consi- 
dered to be an electrical circuit where R1, 2 
represent the thermal resistance of the single 
elements (expressed in °C/W); 



Fig. 39 



PLASTIC PACKAGE 




-•—HEATSINK 



239 



Fig. 40 



*® Hh 



Hh 



^1. 



C1 , 2 the thermal capacitance (expressed in = C/W) 
I the dissipated power 

V the temperature difference with respect to 
the reference (ground). 

This circuit can be simplified as follows: 
Fig. 41 



& 



— t-n-iV-ih 



Where C e is the thermal capacitance of the die plus 

that of the tab. 

C n is the thermal capacitance of the heatsink 

Ri, 



Jjc 



is the junction case thermal resistance 
R n is the heatsink thermal resistance. 

But since the aim of this section is not that of 
studing the transistors, the circuit can be further 
reduced. 



characteristics we get Rj_ c = 3°C/W) 
90-40- 3-6 



■>h 



= 5.3°C/W 



Using the value thus obtained in (1), we get that 
the junction temperature during the overload goes 
to the following value: 



T, 



60 



(3 + 5.3) • 9.6 = 140°C 



If the overload occurs only rarely and for short 
periods, dimensioning can be considered to be 
correct. Obviously during the shortcircuit, the 
dissipated power reaches must higher values (about 
40W for the case considered) but in this case the 
thermal protection intervenes to maintain the tem- 
perature below the maximum values allowed. 

Note 1: If insulating materials are used between 
device and heatsink, the thermal contact resistance 
must be taken into account (0.5 to 1°C/W, depen- 
ding on the type of insulant used) and the circuit 
in fig. 43 becomes: 

Fig. 43 




Fig. 42 




•1 „„ 



If we now consider the ground potential as am- 
bient temperature, we have: 



Ti= T a + (R ic + R n ) P c 
D _ Ti-T a -R ic -P d 

T c = T a + R h • P d 



(1) 

(1a) 

(2) 



For example, consider an application of the L200 
with the following characteristics: 



14V 



'o typ 



1A 



T^ 40° C 



22V 



14V 



V„ 

'o max 
T a = 60° C 



1.2A 



„ d typ 



= (V h 



V n ) • I, 



typical conditions 



overload conditions 



(20-14) '1=6™ 



p dmax= (22-14). 1.2 = 9.6W 

Imposing T, = 90 G C of (1a) we get (from L200 



Note 2: In applications where one or more external 
transistors are used together with the L200, the 
dissipated power must be calculated for each com- 
ponent. The various junction temperatures can be 
calculated by solving the following circuit: 

Fig. 44 




This applies if the various dissipating elements are 
fairly near to one another with respect to the heat- 
sink dimensions, otherwise the heatsink can no 
longer be considered as a concentrated constant 
and the calculation becomes difficult. 

This concept is better explained by the graph in 
fig. 45 which shows the case (and therefore junc- 
tion) temperature variation as a function of the 
distance between two dissipating elements with the 
same type of dissipator and the same dissipated 
power. The graph in fig. 45 refers to the specific 
case of two elements dissipating the same power, 
fixed on a rectangular aluminium plate with a ratio 



240 



of 3 between the two sides. The temperature jump 
will depend on the dissipated power and one the 
device geometry but we want to show that there 
exists an optimal position between the two de- 
vices: 



side of the plate 



Fig. 46 shows the trend of the temperature as a 
function of the distance between two dissipating 
elements whose dissipated power is fairly different 
(ratio 1 to 4). 



This graph may be useful in applications with the 
L200 + external transistor (in which the transistor 
generally dissipates more than the L200) where the 
temperature of the L200 has to be kept as low as 
possible and especially where the thermal protec- 
tion of the L200 is to be used to limit the transis- 
tor temperature in the case of an overload or ab- 
normal increase in the ambient temperature. In 
other words the distance between the two elements 
can be selected so that the power transistor reaches 
tne T j max (200°C for a TO-3 transistor) when the 
L200 reaches the thermal protection intervention 
temperature. 



Fig. 45 



T c CO 




Fig. 46 




A : Position of the device with high power dissipation (10W) 
B : Position of the device with low power dissipation (2.5W) 



241 



CONTROL OF A DC MOTOR USING TRANSPACK 

microprocessor based fully integrated solution 



INTRODUCTION 

This article covers the design of a controller for a 
DC permanent magnet motor. The design is pre- 
ceded by a mathematical simulation of the con- 
troller. The controller design is complete with 
working drawings and a programme for the micro- 
processor. A comprehensive collection of diagrams 
and photos shows the operational performance of 
the design under normal and adverse working con- 
ditions. 



Simulation of Motor Behaviour 

The motor chosen for the design is a constant 
current type with a permanent magnet with a 
stator flux nearly constant and a good power to 
weight ratio compared with classic DC motors. 

Simulation forcast: - Max. peak current, Ripple 
current at various chopper frequencies, Response 
speed of the system. Function in steady state. 

The parameters are studied for extreme working 
conditions to optimise the choice of inverter 
components. 



The Control Hardware 

The hardware design is implemented with a micro- 
processor, D/A converter, switchmode driver and 
two power modules for the high current drive for a 
simple and integrated solution. 

The bridge is constructed with two TO-240 



TRANSPACK power modules of half bridge con- 
figuration, SGS30DB040D which permit fast 
acceleration of the motor and a compact structure. 

The microprocessor allows simplicity and flexibility 
e.g. motor speed is controlled by a six bit word 
which accurately sets the speed between 0.5% and 
maximum. 



Study of the System Behaviour 

The system behaviour is studied to analyse the maxi- 
mum stress conditions on the bridge corresponding 
to possible operating conditions, the algorithm of 
acceleration, braking, and inversion of the speed 
are demonstrated. The objective is to obtain the 
maximum performance possible with the tran- 
sistors chosen for the bridge. 



Balance of the Bridge 

The evaluation of power absorbed by the various 
parts of the system demostrates the efficiency of 
the design. 

Detailed analysis of power absorbed in the motor 
and power dissipated in the bridge qualifies this 
design. 

This study involves particularly heavy operating 
conditions for the power circuitry which verifies 
the excellent performance of the TRANSPACK 
devices above all in terms of switching speeds and 
low losses i.e. efficiency. 



243 



Laboratory implementation of the hardware 




Motor Specification 

Nominal Current 
Nominal Supply Voltage 
Peak Torque 

Maximum Working Speed 
Absolute Maximum Speed 
Rotor Inertia 
Torque Constant 
Resistance 
Inductance 

Demagnetisation Current 
Nominal Power 
Back EMF Constant 



Drive Specification 

Maximum Motor Current 
Maximum Supply Voltage 
Minimum Speed Variation 
for each direction 
Chopper Frequency 
4 Quadrant Control 



Ia 


= 1.8A 


Vp 


= 200-220V 


T 


= 6Nm 


n 


= 15000 rpm 


n,' 


= 20000 rpm 


J 


= 0.6 10~ 7 Kg.m 


K T 


= 0.17Nm .A" 1 


R 


= 0.96S1 


L 


= 6.6mH 


'rim 


= 105A 


P 


= 200W 


K„ 


= 0.17 V.s 



permanent magnet hence with a stator flux nearly 
constant and a good power to weight ratio com- 
pared with classic DC motors. The electrical 
circuit used for simulation is: 

Fig. 1 



30A 
400V 

1/32 maximum speed 
21.7KHZ 



Simulation of Motor Behaviour 

The motor is a (DC) constant current type with a 



For the mathematical model it was decided to 
neglect the variation of stator flux due to the in- 
ductive reaction, hence considering the flux gen- 
erated by the permanent magnets to be constant. 

This simplification has little effect on the repre- 
sentation of motor behaviour but it simplifies the 
calculations. 

The equations which form the model are the 



244 



following: 

1) V A = RA l A + LAdi A /dt + E 

2) Cm = J dn/dt + DJ2 + Cr 

3) E = K,0I1 

4) C M = K T l A 



Where: 
V A 

Ia 

Ra 
La 

E 

C M 
C r 

J 

n 



D 

K v 

K T 



Armature Voltage (Volts) 

Armature Current (Ampere) 

Stator Resistance [i~L) 

Stator Inductance (H) 

Electro Motive Force (Volts) 

Torque (Nm) 

Friction (Nm) 

Inertial Moment (Kg.m 2 ) 

Angular Velocity (rad/sec) 

Stator Magnetic Flux (Weber) 

Kinetic Friction (Nm) 

Back EMF Constant (V.s) 

Torque Constant (Nm A' 1 ) 



From the balance of energy: 

C.Sl = E. I A where C equals the motor output (Watts) 
E 

K c o l A from which K c = K v 



K v 

The differential equations were resolved by the 
Runga - Kutta method for solving non linear 
equations. 

With the simulation it was proposed to forecast 
the following behaviour: 

— Maximum Peak Current 

— Ripple current at various chopper frequencies 

— Response speed of the system 

— Function in steady state 



The phenomena were studied with the intention 
of seeing the maximum values of the observed 
parameters rather than instantaneous values in 
order to optimise the choice of inverter com- 
ponents. The simulation was made supposing a 
supply voltage of 200V. 



N.B. - In Appendix A 

the simu lation 1 1 



the programme used for 
on VAX 



Figures 2, 3 & 4 illustrate tne simulated motor 
currents at chopper frequencies of 5, 10 & 20 
KHz with the motor blocked and a 50% duty 
cycle (A = 5). 

It can be seen that ripple current decreases in a 
practically linear relationship to the frequency, 
passing from 3A at 5KHz, to 0.9A at 20KHz. 

The average of the current is zero as is the torque. 
The absorbed power is however dissipated in the 
motor, becoming lower as the chopper frequency 
increases. 

Figures 5 & 6 show the trend of velocity, at 10 

6 20KHz, with a 70% duty cycle (A = 7) and 
load torque zero. Also the ripple on the speed 
is strongly influenced by the chopper frequency, 
going from 4.22% at lOKHz to 0.84% at 20KHz. 
Assuring a steady state speed of 237 rad/sec the 
ripple varies from 10 rad/sec at 10KHz to 2 rad/ 
sec at 20KHz. 

Under identical conditions (frequency and duty 
cycle) the motor current analysis shown in figures 

7 & 8 was made. 

The ripple current and hence the torque merit 
observations similar to those made for the speed. 
From the simulations it was decided to operate 
with a frequency close to 20KHz both in terms 
of reduced losses in the motor as well as the ripple 
effects on speed and torque. 



Fig. 2 




TIME (SEC) 



245 



This choice is made possible by the availability of 
power transistors with very low switching losses. 

Also there is the advantage of much reduced in- 
terference on the supply. 

From the performance reported in figures 5 & 6 
the estimated acceleration time is around 80ms 



for a steady state speed of 237 rad/sec. 

The data supplied from the simulation has also 
enabled an estimate that with a duty cycle of 
70% the peak current amounts to around 30A. 

This data has led to the choice of the SGS30DB040D 
for the power bridge. 



Fig. 2a 



r 






CM f 



-H — I — | — I — t—t — t— | — I— -I — I — I — (—4— ! — H-l--f- »— *—* — *—\ — t—t- +—*— f-H — I — I— I — \— t — t—i — I — |~t— t— 1 — I — -j — -I — H — I — I — | — I — I — I — P — I 



0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 

TIME (SEC) *10T-2 



Fig. 3 




0.10 0.10 

TIME (SEC) 



246 



Fig. 4 




.040 0.060 0.080 0.100 
TIME (SEC) 



0.120 0.140 0.160 0.180 0.200 



Fig. 5 




0. 100 



-+-+- 



' ' I 



' I ' 

0.400 



' I ' 
0.500 



TIME (SEC) 



247 



Fig. 6 




0. iaa 0.200 0.300 

TIME (SEC) 



0.800 



Fig. 7 




_h ~_ 



-H 1 ( 1 H- 

0. 100 



-H 1 1 1 1 1 h- 

0.300 
TIME (SEC) 

248 



->— h 



-H 1 J 1 1 1 t— 



0.200 



Fig. 8 



0.000 




0.100 0.200 0.300 0.400 

TIME (SEC) 



0.500 



Fig. 9 




0.20 0.40 

VELCRflD/SEC) 



0.80 



1.00 



249 



The Controller Hardware 

With the objective of analysing all the stresses on 
the components it was prefereble to construct an 
open loop control which thanks to the lack of 
compensating feedback, permits an immediate 
study of the phenomena. 

In order to operate with the maximum flexibility 
the system was designed to be microprocessor 
controlled using a NBZ80ASED "nanocomputer". 



The digital to analogue conversion and drive 
waveform generation was realised with the SGS 
L291 and L292 for a simple and efficient in- 
tegrated solution. 

The bridge was constructed with two TO-240 
TRANSPACK power modules of half bridge con- 
figuration, SGS30DB040D, which permit fast 
acceleration of the motor and a compact structure. 

The block diagram is shown in figure 10. 



Fig. 10 - Block diagram 



LOGIC 

INTERFACE 

HARDWARE 



V 



POWER 
DRIVER 





The Controller Schematic 

The complete schematic of the controller is de- 
scribed as follows: 

Fig 11 shows the control portion. A 6 bit word, 
generated by the microcomputer, representing the 
required speed of the motor, is converted into an 



analogue current. This D/A conversion is carried 
out by the L291 . The analogue signal is then 
used to drive the L292 which generates pulses of 
variable duty cycle. This device, normally used to 
drive low power motors, offers the advantage of 
outputs of two complementary signals of variable 
frequency between 1 and 30KHz. 



Fig. 1 1 - Control section 



H2V +12V +18V 



i_r 




-12V 



250 



Also it is possible to impose a delay between th° 
end of one signal and the start of the complement, 
essential to avoid the short circuit condition on 
the bridge. The transfer of the signal from the con- 
troller to the high side of the bridge is via Q5 and 
Q6. These transistors are power devices working in 
the active zone with very low current and must 
sustain a voltage 5V greater than the voltage 
applied to the motor (fig. 1 1a). 

This solution avoids the use of a transformer and 
is aimed towards the eventual integration of the 
power stage. The drive of the transistors in the 
bridge was realised with a simple integrated solu- 



tion of the SGS L149, whose power for the high 
side is referred to the voltage at the motor terminals 
which follows the variations. 

The power for the motor is provided by a full bridge 
circuit permitting operation in all 4 quadrants. 

The two half bridge TRANSPACK, SGS30DB040D, 
are built using darlingtons without integrated col- 
lector - emitter diodes which permits full use of 
the fast freewheel diodes incorporated in the 
power module and high frequency drive of the 
motor. The voltage waveforms on the motor are 
illustrated in photo 1 . 



Fig. 11a 



(Vf+SlV 




Photo 1 - Motor voltage 



Photo 2 A - Ripple of 3 A at 5KHz 








wIUUmsjH 

MB 




WMr<flAlM 


a 






■til 






■ffll 



V = 50V/div 
t = 10,us/div 



I =0.5A/div 



251 



The principle characteristics of the darlington are Photo 2B - Ripple of 0.9A at 20KHz 
as follows: 

- V CEO = 400V 



H FE = (l c = 30A) 50 
V CE(sat) = <l C = 30A, l E 
t s (storage time = 1.2ms 
t f (fail time) = 0.2ms 



: 2A) = 1.5V 



The main parameters of the diode are: 



- V F = 1.2V 

- t RR < 0.2ms 

- I F RM = 250A 



30A, 



(l F = 30A) 
di/dt = 100A/ms) 



Photo 2 shows the behaviour of the motor, cur- 
rents at chopper frequencies of 5KHz and 20KHz. 
It is possible to note in photo 2A (5KHz) a ripple of 
3A in agreement with the simulated data, while in 
photo 2B one sees a ripple at 20KHz of around 
0.9 A. 




I = 0.5A/div 



Fig. 12 - Assembly of the circuit board 

V E -S V E *5 V t -5 V E *5 



____*"__ J 



IZZ1R22 
CZJR23 

I IR11 



R13 



O R20 R21 

\>^R8 □ CZ3 



]R10 

RHCZj CZ1R5R4C3 

| CZJR18 CZ1R2 C2Q CZDR17 

C^]R9 dTDR3R15r^l C3R16 4 






Ei.ELn_anjzLariEL 



en 

R7 



COMPONENTS LIST 



Components 


Quantity 


Value 


Note 

TRANSPACK 


Components 

R16, R17 


I 

Quantity 

1 - 


Value 


Note 


SGS30DB040D 


2 




100.Q 




L149 


4 




Driver 


R18, R19 


2 


2.7KS! 




L291 


1 




d/a converter 


R20, R21 


2 


670fi 




L292 






PWM generator 


R22, R23 


2 


10KS! 




R1 




4.9 Kf 2 




R24, R25 


2 


5<> 




R2 




3.9KS2 




R26, R27 


2 


bil 




R3 




22K<7 




CI 


1 


100riF 




R4 




8,4Ki> 




C2 


1 


1000,jF 




R5 




5K<> 




C3 


1 


22nF 




R6, R7 


2 


15KS2 




Q1.Q2, Q3, Q4 


4 




2^4033 


R8 , R9 


2 


3.8KS! 




Q5, Q6 


2 




1IP50 


R10, R11 


2 


1KS1 




B1 , B2 


2 






R12, R13 


2 


1.5KU 




B3, B4 


2 






R14, R15 


2 


470S! 


_._ J 


11 






i . 



252 



Study of the system behaviour 

To analyse the maximum stress condition on the 
bridge corresponding to possible operating con- 
ditions, the algorithm of acceleration, braking and 
inversion of the speed were performed- The ob- 
jective was to obtain the maximum performance 
possible with the transistor s chosen for the bridge. 

The strategy followed was to choose a speed of 
3000rpm analysing the time needed to reach the 
speed. 



Acceleration Tests 

Firstly the motor was accelerated with a duty cycle 
corresponding to the chosen speed (steady accelera- 
tion with a drive signal duty cycle of 70%). The 
result of this test is shown in photo 3 & 4. 



Photo 5 - The trend of the velocity with four 
progressive steps of voltage at intervals 
of 25ms (560 rpm/div) 




Photo 3 - Trend of the speed with only voltage 
changing (560 rpm/div) 



Photo 6 - 



The trend of the current under 
conditions of photo 5 (5A/div) 



the 




Photo 4 - Trend of the current under the same 
conditions as photo 3 (5A/div) 




In photo 4 it is seen that the current reaches a 
peak of 23A in a limited number of pulses and 
then goes to full speed much more slowly, with a 
current of 0.6A. Regarding the speed, the period 
of the transition may be estimated as around 1.2s. 



Also a ramp of acceleration was tested imposing 
4 increases in duty cycle of 5% with a 25ms delay 
between each (photo 5 & 6). 

In this way the maximum current during accelera- 
tion is reduced to 20A without any significant 
variation of the time to reach full speed. 

Photo 7 - The trend of the speed with the drive 
of figure 13 (560 rpm/div) 




253 



Fig. 13 

DUTY CYCLE ■' 
% 

80 

70 

60 



Photo 9 - Trend of velocity with an initial drive 
to produce 3750 rpm followed after 
300ms by a drive to produce 3000 rpm 
(560 rpm/div) 



TIME (msec) 



Photo 8 - Trend of the current with the drive of 
figure 13 (10A/div) 





Photo 10 - Trend velocity with an initial drive to 
produce 3750 rpm followed after 
180ms by a drive to produce 2250 rpm 
and finally after 100ms by a drive to 
produce 3000 rpm (560rpm/div) 



Other test of acceleration are shown in photos 
9, 10 & 11 



A series of tests were performed attempting to 
obtain a determined speed in the minimum pos- 
sible time, working with duty cycles above and 
below that of steady state with the appropriate 
delays. 

The best result was obtained driving with the 
sequence of duty cycles illustrated in fig. 13 as 
shown in photo 7. 

One notes that the duration of the transient may 
be estimated to be around 500ms, notably below 
the 1.2s in the case shown in photo 3, cor- 
responding to an average acceleration of 628 
rad/sec 2 and with an instantaneous acceleration of 
7500 rad/sec 2 , corresponding to a maximum 
current of 26A shown in photo 8. 




DUTY CYCLE 
% 
















60 


u 




180 


100 


T,M 



254 



Photo 11 



Trend of velocity with a initial drive 
to produce 3750 rpm followed after 
160ms by a drive to produce 2250 rpm 
and finally after 50ms by a drive to 
produce 3000 rpm 



Photo 12- Trend of velocity (1090 rads/sec/div) 




Speed Reversal 



Having reached the maximum, the objective was to 
achieve the maximum steady acceleration and to 
estimate the time needed to achieve an inversion 
of the speed passing from +3000rpm to -3000rpm 
having supposed that this is the most critical 
stress on the bridge. 




The behaviour of the relevant currents are shown 
in photo 13 where points shown by the arrows 
are relative to the transformation of the motor 
into a generator. 

Photo 13 - Current absorbed by the motor with 
the described speed invertion f10A/div) 




Both the tests of acceleration and speed reversal 
were made with repetitive cycles, with appropriate 
programmes in the Nanocomputer® , for periods 
of several hours without creating problems for 
the SGS30DB040D. 



There was first analysed the phenomena of braking 
and it was seen that braking too quickly may 
cause a change of function, making the motor a 
generator and creating excess emitter base voltage 
up to a situation intolerable for correct operation 
of the bridge components. 

This phenomena was taken into account to achieve 
the most rapid braking possible without over- 
stressing the bridge components. 

We succeeded in this way to obtain a time, from 
+ 3K to - 3Krpm, of about 500ms, as shown in 
photo no. 12 where the achievment of a steady 
state is not considered but only the transition 
from one speed co another. 



Balance of the Bridge 



The evaluation of the power absorbed by the 
various parts of the system is analysed in the 
following paragraph. 

The estimates obtained give an indication of the 
efficiency of the control system in that it permits 
a ratio of the power absorbed to that of the motor. 

The power was measured using the following 
system (fig. 14). 

The chosen conditions were: 

— Duty cycle of 76% 

— Average motor current 1 .25A 



255 



Fig. 14 



POWER 
SUPPLY 


P*L 
































Pal aus 


DC:,T 




6R.0GE 




AUXILIARY 
SUPPLY 


Ph 




















The load was simulated by a generator connected 
to the motor and a rheostat of 200H. 

In this situation the power taken from the supply 
was: 

- P AL = 200V x 0.83A = 166W 

The power absorbed by the drive circuit was: 

- P AL Auxiliary = 7. 86W 

The power absorbed by the motor was: 

- Pm = V av x l A = 123.2V x 1.25A= 154W 
Hence the power absorbed the bridge was: 

~ P BRIDGE= 1 2W 

Thus one has a dissipation of power in the bridge 
of 7.2%. 



Power Absorbed by the Motor 

Photo 13 shows the waveforms of current and 
voltage on one arm of the bridge. The power in 
the motor was computed as the difference of 
the power absorbed during the conducting phases 
of the bridge less that returned during the conduc- 
tion of the free wheel diodes. 



Photo 14 



Photo 13 




Photo 14 represents the power absorbed. The 
energy corresponds to the area under the curve 
in a period. Given that: 



E = 9.47mJ, 



r ABS- MOT 



F = 21700Hz 

ExF = 9.47 10 3 -21.7 10 3 = 205.6W 




The power returned from the motor is shown in 
photo 15. 

- E = 2.38mJ 

- F = 21700Hz 

- Pgen.mot. -51.6W 

Thus the total power absorbed by the motor is: 



r TOT. MOT. " 
= 205.6 -51.6 ■ 
Photo 15 



ABS. MOT. 
= 1 54W 



GEN. MOT. 



.wtt-.m luzKj-j 






■ sy 


\ 




\ 


■ 


:••.•■ 




\ ■ 

. -%; ;.. .. 


\ 


ill 




\ 


\ 




Tt 
























"1 




»VC»0 • -6.843 


: 
2.38 







Power Dissipated in the Bridge 

The power dissipated in the bridge was analysed 
in a more detailed manner by measuring the 
power dissipated in one transistor (high side) 
both in the turn-on and turn-off phases and 
estimating the dissipation during the on period. 

The waveforms of voltage and current during an 
entire period can be seen in photo 16. 



256 



Photo 16 



Photo 19 




The power dissipated during the turn-on phase Photo 20 
and the respective voltage and current waveforms 
are shown in photos 17 & 18. 
Photo 17 




From the photo of the power it is possible also 
to measure the energy dissipated. This corresponds 
to an average power of: 

Pqn = E x F = 189.6mJ x 21700Hz = 4.1W 

The power dissipated during the turn-off phases 
and the respective waveforms are shown in photo 
19&20. 

The energy dissipated in this case is 118mJ thus: 
P OFF = ExF = 118.5 x 21700 = 2.47W 




The dissipation of the conduction phase is not 
conveniently measured by the method used so it 
was preferred to make an estimate. 

At the average current of 1.25A from the charac- 
teristic curves a V CE ( Sat ) of 0.8V is found. 

p COND. = 1 -25A x 0.8V x 0.76 = 0.76W 

Taking into consideration that the conduction 
phase is 76% of the full period: 

The power dissipated in a transistor of the bridge 
is thus: 

P TOT = P N + POFF + PCOND = W-1 + 2.57 + 
+ 0.76) W = 7.43W 



CONCLUSION 

During this work a study was made, both in theory 
and application, of the control of a DC motor. 
For this study, advantage was taken of the flexi- 
bility offered by using a microprocessor to make 
many tests. This allowed a comprehensive analysis of 
the behaviour of the SGS30DB045D TRANSPACK. 
This involved the recreation of particularly heavy 
operating conditions for the power circuitry, 
which verified the excellent performance of the 
TRANSPACK devices, above all in terms of 
switching speed and low losses. Also studies 
were made of a number of drive circuits for the 
power transistors, useful for future projects. 



257 



APPENDIX A 



# TY Motor For 

DIMENSION Y [20) , YF [ 20 J 

EXTERNAL FUNG 

REAL KC.KV 

OPEN (UN.IT = 7,FILE= 'MIKE, DAT' , ST ATUS= ' NEW ' ) 

OPEN (UNIT= 8,FILE= 'MIKE1 , DAT ' , ST ATUS= ' NEW ' ) 

OPEN (UNIT=9,FILE='MIKE2 , DAT ' .STATUS- 'NEW' ) 

OPEN (UNIT=10,FILE= ' MIKE3.DAT ', STAT US= 'NEW'] 

OPEN (UNIT=1 1 ,FILE=' MIKE4.DAT ' , STATUS" 'NEW ' ) 

WRITE (*,30) 
30 FORMAT( 1X , 'INTRODUOI H , NS , NT , CR , T , A ' ) 

READ (*,*j H,NS,NT,CR,T, A 

TI = A*T/ 10 

T2 = T-T 1 

L=H*NS*NT/T 

WRITE(*,*) 'VUOI I GRAFICI? (SI=1)' 

READ (*,*) AAA 

WRITE (*,*) 'LA MACCHINA E' QUELLA SOLITA? [SI=1] 

READ (*,*) Z 

IF (Z,NE, 1 j GO TO 40 

X = 0. 

N-2 

Y ( 1 )=0. 

Y (2)=G. 
RA=0.96 
XLA-0.006 
FL=1 . 
RJ=. 00056 
Kc=. 17 
Kv=. 17 

GO TO SO 
40 WRITE (* , 17 j 

17 FORMAT ( IX , 'INTRODUOI X,N,Y ( I ) , RA , XLA , FL , R J , Kc , Kv ' ] 

READ (*,*) X,N, (Y(I) ,1=1 ,N) , RA , XLA , FL , R J , Kc , Kv 
BO CONTINUE 

00 2 J=1 , NT 

00 1 K=1,NS 

CALL RKUI'TA(N , X , Y , FUNC , H , XF , YF , CR , RA , XLA , FL , CM , E , R J 
# Kc ,Kv,L,T,T1 , T2) 

X = XF 



20 
15 
333 



DO 1 1=1 ,N 




Y(I]=YF(1) 




CONTINUE 




CM=Kc*FL*Y (1) 




E-KV*FL*Y (2) 




IF (AAA.EQ. 1 ) GO TO 333 




WRITE (*,20) 




FORMAT ( 1X , 'TEMPO ', 7X , 'IA ' , 


10X, 'VEL ' 


WRITE (*, 15) X, (Y(I) ,1=1 ,N, 


I ,CM,E 


FORMAT (5 E12.S] 




00 TO 2 




WRITE (?,*) X,Y (2) 




WRITE (8,*) X , Y ( 1 ) 




WRITE (9,*j X,OM 




WRITE (10,*)X,E 




WRITE (11,*) Y (2) ,0M 




CONTINUE 




CLOSE i'UNIT = 7l 




CLOSE (UNIT=8) 




CLOSE (UNIT=9) 




CLOSE (UNIT=10) 





,9X, 'CM' , 10X, 'E' ) 



258 



APPENDIX A (continued) 



CLOSE (UNIT=11 

STOP 

END 



SUBROUTINE RKUTT A ( N , X , Y , FUNC , H , XF , YF , CR , RA , XL A , FL , CM , E , R J , 

Kc ,Kv,L, T,T1 , T2) 

DIMENSION Y ( 20 ) , Y I ( 20 ) , YF ( 20 ) , D ( 20 ) , A ( S ) 

REAL KC.KV 



A 


[1) 


= 


H/2 


A 


(2) 


= 


A (1) 


A I 


[3) 


= 


H 


A I 


[4) 


= 


H 


A I 


[5] 


= 


A (2) 


XF = 


= X 






DO 


10 


IO 


= 1 ,N 


YF 


IK) 




" Y (K) 


YI 


(K) 




■ Y (K) 


DO 


20 


J' 


= 1,4 



10 

CALL FUNC (XF , YI , N , D , CR , RA , XLA , FL , CM , E , R J , Kc , Kv , L , T , T 1 ,T2) 
XF=X+A (J) 
DO 20 K=1 ,N 
YI(K)=Y(K)+A(J)*D(K) 

20 YF(K)=YF(K)+A( J+ 1 )*D(K)/3 
RETURN 

END 

SUBROUTINE FUNC ( X , Y , N , D , CR , RA , XLA , FL , CM , E , R J , Kc , Kv , L , T , T 1 , T2 
DIMENSION Y (20), D (20) 
REAL KC.KV 
DO 16 M = 0, (L-1 ) 
IF(X-M*T) .LE.T1 ) GO TO 11 
IF((X-M*T) .LE. (T1 + T2) ) GO TO 12 
18 CONTINUE 

11 VA=400. 
GO TO 2 1 

12 VA = - 400. 
GO TO 21 

21 CONTINUE 

D (1) = (VA-E-RA*Y( 1))/XLA 

D (2) =(CM-CR)/RJ 

RETURN 

END 



259 



APPENDIX B (continued) 



ft > tup* dr i ve . is I 
' cic motor control ' 
In aadr ob.i code t 



i 1 i ne 



st at 4 i 



snt 



1 



7 


0800 


3E0F 


8 


0802 


D30B 


V 


0804 


'Sl.^ 


IB 


D806 


D30B 


11 


D808 


3 EC 7 


12 


D80A 


0310 


13 


D80(J 


3E01 


14 


D80E 


0310 


15 


D810 


16F1 


16 


0812 


1E1F 


17 


D814 


0636 


18 


D816 


0E36 


IV 


D818 


131808 


20 


03 IB 


C9 


21 


D81C 


78 


9 '7 


08 ID 


B7 


23 


D81E 


CA31D8 


24 


D«21 


78 


25 


D822 


D61C 


26 


0824 


FA2C08 


27 


D827 


05 


28 


0828 


15 


2 V 


0829 


835108 


30 


082C 


05 


31 


0820 


14 


32 


082E 


C35108 


33 


0831 


79 


34 


0832 


B7 


35 


0833 


LA46D6 


36 


0836 


79 


37 


0837 


D61C 


38 


0839 


FA41D8 


39 


D83C 


00 


40 


0830 


10 


41 


D63E 


C35108 


42 


0841 


00 


43 


0842 


1C 


44 


0843 


C 35 108 


45 


D846 


16FF 


46 


0848 


1E1F 


47 


084A 


0636 


43 


0840 


0E36 


49 


D84E 


C351D8 


50 


0851 


73 


51 


0852 


B7 


>jZ 


0853 


CA5C08 


53 


0856 


7 A 


54 


0857 


1)3 0? 


55 


0859 


C35FD8 


56 


085C 


7B 


•j / 


0650 


0309 



4 

6 
7 
8 
9 
10 
11 
12 
13 
14 
15 
16 
17 
18 
19 
20 
21 



^/ 
28 
29 
30 
3i 



36 
37 
38 
39 
40 
41 
42 
43 
44 
45 
46 
47 
48 
49 
50 
51 



i n i t 1 
p i od 
p i oc 
ctc0 



indl 



i nd2 



in. 13 



i nd4 



out 



e;-; i t 1. 



.t itlt 
. equ 
.equ 
.equ 
.equ 
.or q 
Id 
out 
id 
out- 
id 
out- 
id 
out 
Id 
Id 
Id 
id 

IP 

ret 
id 

or 

JP 
td 
sub 

.IP 

dec. 

dec 

JP 
dec 

i nc 
-IP 
Id 
or 

JP 
Id 
sub 

JP 

dec 

dec 

JP 

dec 

i nc 

.IP 

Id 

id 

Id 

id 

IP 
id 
or 
-IP 
id 
out 

.IP 
id 
c u t 



" ' dc motor control' 

0d800h 

09h 

0bh 

10h 

I n i 1 1 

a 7 0fh 

(p i oc ) , a 

a,07h 

(p i oc ) , a 

a,0c7h 

(ctc0) .a 

a . 1 h 

(ctc0) . a 

d,0ifh 

e^lf'h 

b,36h 

c,36h 

m a i n 

a.b 

a 

z . i n d 2 

a.b 

lch 

m , indl 

b 

d 

out 

b 

d 

out 

a.c 

a 

z, i nd4 

a,c 

lch 

m . i n d 3 

c 

out 

c 

e 

out 

d.0ffh 

e.lfh 

b.36h 

c . 36h 

o u t 

a.b 

d 

z.exitl 

a.d 

( p i o d ) . a 

*Xit2 

a . e 

( p i c- d ) . a 



260 



APPENDIX B (continued) 



' dc motor control ' 
In addr ob.j code t 



1 


08SF 


3E62 


^ 


D861 


26FF 


3 


0863 


2EFF 


4 


D865 


20 


5 


08 6 c 


C265D8 


6 


0869 


25 


7 


086A 


C26308 


8 


0360 


30 


9 


D86E 


C261D8 


10 


D871 


79 


11 


0872 


B7 


12 


0873 


C21CD8 


13 


08/6 


16FF 


14 


0878 


1E1F 


15 


DS7A 


0608 


16 


D87C 


0E08 


17 


08 7 E 


7 A 


18 


087F 


0309 


1? 


0881 


3E08 


20 


0883 


26FF 


21 


0885 


2EFF 


'A v. 


0867 


20 


*c.%J 


0888 


C28708 


24 


D88B 


25 


^!o 


088C 


C28508 


26 


D88F 


30 


27 


D89w 


C28308 


28 


0893 


78 


29 


0894 


E.7 


30 


0895 


CAAC08 


31 


0898 


78 


32 


0899 


0605 


33 


089 B 


FAA508 


6*i 


089E 


05 


35 


089F 


15 


36 


O8A0 


15 


3/ 


08 A 1 


15 


38 


08 A 2 


C3C508 


3? 


D8A5 


05 


40 


D8A6 


14 


41 


D8A7 


14 


42 


D8A8 


14 


43 


08A9 


C3C508 


44 


D8AC 


79 


45 


08A0 


B7 


46 


D8AE 


CAC5D8 


47 


D8B1 


79 


48 


D8B2 


0605 


49 


D8B4 


FABE08 


50 


08B7 


00 


51 


08B8 


10 


u'2 


08B9 


ID 


53 


08BA 


10 


54 


D8BB 


C3C5D8 


55 


D8BE 


00 


5 6 


08 BF 


IC 




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1C 



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source 


stateme 


it 


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e>:i t2 


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e 


114 




i nc. 


e 



261 



APPENDIX B (continued) 



' dc motor control ' 
In addr ob j code t 



i I i ne 



source statement 



1 D8C1 1C 

2 D8U2 C3C5DS 

3 D8U5 7b 

4 D8C6 E7 

5 D8C7 CAD0D8 

6 D8LA 7A 

7 D8CB D309 

8 D8CD C3D308 
V D8D0 _ 7B 

10 0SD1 D309 

11 D8D3 3E01 

12 D805 262F 

13 D8D7 2E5F 

14 DSD? 2D 

15 DSD A L2D9D8 

16 D8DD 2b 

17 D8DE C2D7D8 

18 D8E1 3D 

IV D8E2 C2D5D8 
26 D8E5 79 

21 D8E6 B7 

22 D8E7 C293D8 

23 D8EA 16FF 

24 D8EC 1E1F 

25 D8EE tt>6<A8 

26 DSFm 0E08 

27 D8F2 7A 

28 D8F3 D309 

29 D8F5 3E08 
3« D8F7 26FF 

31 D8F9 2EFF 

32 D8FB 2D 

33 D8FC: C2fBDS 

34 D8FF 25 

35 0904) C2F9D3 

36 D903 3D 

37 D9«4 S2F7DS 

38 D907 78 

39 D908 B7 

40 D909 CA20O9 

41 D9t>C 78 

42 D90D D605 

43 D90F FA19D9 

44 D912 05 

45 D913 15 

46 D914 15 

47 D915 15 

48 D916 C339D9 

49 D919 05 

50 D91A 14 

51 D91B 14 

52 D91C 14 

53 D910 C339D9 

54 D920 79 

55 D921 B7 

56 D922 CA69D9 

57 D925 7V 



115 inc 

116 .ip 

117 outl Id 

118 or 
11V ip 

120 Id 

121 out 

122 .ip 

123 exit4 Id 

124 out 

125 exits Id 

126 loop 7 Id 

127 loopS Id 

128 loop9 dec 

129 ,ip 

130 dec 

131 ip 

132 dec 

133 ,,p 

134 Id 

135 or 
13c, jp 

137 init3 Id 

138 Id 

139 Id 

140 Id 

141 Id 

142 out 

143 Id 

144 loopl0 Id 

145 loop 11 Id 

146 loop 12 dec 

147 ,jp 

148 dec 

149 jp 

150 dec 

151 jp 

152 exit6 Id 

153 or 

154 jp 

155 Id 

156 sub 

157 jp 

158 dec 

159 dec 

160 dec 

161 dec 

162 .jp 

163 inds dec 

164 inc 
1 6 5 inc 
i66 inc 

167 j P 

168 indv Id 

169 or 

170 ip 

171 Id 



outl 

a,b 

a 

z r *xit4 

a,(i 

(p i od) , a 

exits 

a . e 

( p i o d ) . a 

a , 1 h 
h.2th 

1,5th 

I 

nz, loopV 

h 

nz, loops 

a 

nz, loop 7 

a .c 

a 

nz.ex i t3 

d.0+fh 

e.lfh 

b 7 08h 

c .08h 

a,d 

( p i o d ) , a 

a , 08h 

h.0ffh 

1.0ffh 

I 

nz, loop 12 

h 

n 

a 

n 

a.b 



loop 11 
loop 10 



z. ind? 

a.b 

05h 

m, i ndS 

b' 

d 

d 

d 

out 2 

b 

d 

d 

d 

out 2 

a .c 

a 

z.out2 

a , c 



262 



APPENDIX B (continued) 



' dc motor control' 
In addr ob.i cod* t 



1 


D926 


0605 


2 


0928 


FA32DV 


3 


D92B 


00 


4 


DV2C 


ID 


O 


D92D 


ID 


6 


D92E 


10 


7 


D92F 


C339D9 


8 


D932 


00 


9 


0933 


1C 


10 


0934 


1C 


11 


D935 


1C 


12 


D936 


C33909 


13 


D939 


78 


14 


093A 


B7 


15 


D93B 


CA4409 


16 


D?3t". 


7 A 


1/ 


D93F 


D309 


18 


D941 


C347U9 


1? 


D944 


7B 


20 


D945 


0309 - 


21 


D947 


3E01 


22 


D949 


265F 


23 


094B 


2E5F 


24 


D94D 


20 


2 b 


094E 


C24D09 


26 


D951 


'- lcr i 


2/ 


D952 


C24BD9 


J2& 


D.9-55. 


30 


29 


D956 


C249D9 


30 


D959 


79 


31 


D95A 


B7 


32 


D95B 


C207D9 


33 


D95E 


16FF 


34 


D960 


0604 


3 j 


D962 


7 A 


36 


D963 


0309 


37 


D965 


3E08 


38 


D967 


26FF 


3? 


0969 


2EFF 


40 


D96B 


20 


41 


D96C 


C26B09 


42 


D96F 


25 


43 


9 7 


C269D9 


44 


D9 73 


30 


45 


D974 


C267D9 


46 


D977 


78 


4/ 


D978 


B7 


48 


D979 


CA80D9 


49 


D97C 


05 


50 


D97D 


15 


51 


D97E 


15 


b2 


D97F 


15 


53 


D980 


7 A 


54 


D981 


0309 


55 


0983 


3E01 


56 


D985 


265F 


57 


0987 


2E5F 



i ne 


source 


stat- 


172 




sub 


173 




JP 


174 




dec 


175 




dec 


176 




deo 


177 




dec 


178 




JP 


179 


i n d 1 


dec 


180 




i nc 


181 




i nc 


182 




i nr. 


183 




IP 


184 


out 2 


Id 


185 




or 


186 




JP 


187 




Id 


188 




o u t 


189 




JP 


190 


e;-;i t9 


Id 


191 




out 


192 


*>!it7 


Id 


193 


loop 13 


Id 


194 


loop 14 


Id 


195 


loop 15 


dec 


196 




.'IP 


197 




dec 


198 




JP 


199 




dec 


200 




JP 


201 




Id 


202 




or 


20 3 




JP 


20 4 


i n 1 1.4 


Id 


205 




Id 


206 




Id 


2 7 




out 


208 




Id 


209 


I oop 16 


Id 


210 


1 o o p 1 7 


Id 


2 1 1 


loop 18 


dec 


212 




JP 


213 




dec 


214 




JP 


215 




dec 


216 




JP 


217 


ex 1 18 


Id 


218 




or 


219 




JP 


220 




dec 


221 




dec 


2 2 2 




dec 


223 




dec 


224 


i n d 1 1 


Id 


225 




out 


226 




Id 


227 


loop 19 


Id 


228 


loop 2 


Id 



lent- 



05h 

m T i ndl0 

c 



out2 
c 



01. 


t2 


a . 


b 


a 




z . 


ex i t9 


a . 


d 


<P 


i o d ) . a 


e> 


it/ 


a. 


e 


<P 


i o d ) , a 


a . 


01h 


h. 


5fh 


1. 
i 


5fh 


L 

n; 


, loop 15 


h 




n; 


, loopl4 


8 




nr 


.loop 13 


a , 


c 


a 




n: 


T e>;it6 


d 


0tf h 


b. 


04h 


a. 


d 


<f 


i od ) . a 


a 


08h 


h. 


0ffh 


1 


0ffh 


L 
n: 


:. loop 18 


h 




m 


! . loop 1 / 


a 




n: 


; . loop 16 


a 


b 


a 




z 


indll 


b 




d 




d 




d 




a 


d 


( p i o d ) . a 


a 


01h 


h 


5fh 


1 


5fh 



263 



APPENDIX B (continued) 



* clc motor contro t ' 
In addr ob.j cod-: 



6 
7 
ft 
9 
10 
ii 
12 
\"6 
14 
15 
16 
17 
18 
19 
20 
21 

O 9 

23 
24 
25 
2o 
2/ 
28 
29 
30 
31 



37 
38 
3? 
40 
41 
42 



D989 

D98A 

098D 

D98E 

D991 

D992 

D995 

D996 

D997 

D99A 

D99C 

DWE 

D9A0 

D9A1 

D9A4 

D9A5 

D9AS 

D9A9 

D9AC 

D9AE 

D9AF 

D9B1 

D9B2 

U9B3 

D9B6 

D9B7 

D9B8 

D9B9 

D9BB 

D9BD 

D9BF 

D?C1 

D9C2 

D9C5 

D9C6 

D9C9 

D9CA 

D9CD 

D9CE 

D9CF 

D9D2 



20 

C289U9 

2b 

C287D9 

3D 

U285D9 

78 

B7 

C277D9 

3E2F 

26FF 

2EFF 

2D 

C2Ay|j9 

25 

C2VFD9 

C2VC09 

060C 

7A 

0309 

78 

67 

CAB8D9 

05 

14 

7 A 

D3y9 

3E01 

26FF 

2£FF 

2D 

C-2C1D9 

C2BFD9 

30 

C2BDD9 

78 

B7 

C2B1D9 

C31CD8 



I i ne 


source 


stateiiii 


snt 


2 2 y 


Loop 2 1 


dec 


1 


230 




JP 


nz r loop 21 


231 




dec 


h 


2si2 




IP 


nz, loop 20 


233 




dec 


3 


234 




JP 


nz, loop 19 


235 




Ld 


a,b 


236 




or 


3 


237 




IP 


nz.ex i t8 


238 




Id 


a,02fh 


239 


loop 22 


Id 


h.yfth 


240 


loop23 


Id 


l.0f+'h 


241 


loop 24 


dec 


1 


242 




JP 


nz . loop24 


24jj 




dec 


h 


24't 




JP 


nz, loop 23 


2 '■, 5 




dec 


3 


24o 




JP 


nz, loop 22 


247 




Id 


b , 0ch 


248 




Id 


a^d 


249 




out 


(p i od) , a 


250 


ex it Id 


ld 


a r b 


251 




or 


a 


252 




JP 


2, indl2 ■ 


253 




dec 


b 


25-t 




i nc 


d 


' ■' 5 5 


i ndl2 


id 


a-d 


^Ju 




out 


(p i od) , a 


2 5 /' 




Id 


a r 01h 


258 


loop25 


Id 


h, 0f f h 


259 


loop 26 


Id 


l.tfffh 


260 


loop2/ 


dec 


I 


261 




JP 


nz. 1 oop 27 


262 




dec 


h 


2o3 




JP 


nz, loop26 


2o4 




dec 


a 


265 




JP 


nz , loop 25 


2&6 




Id 


a.b 


267 




or 


a 


268 




JP 


nz.ex i tl» 


269 




JP 


m a i n 



error (s ) 



.end 



264 



TRANSISTOR OVERSTRESS IN BRIDGE CIRCUITS 
FOR MOTOR CONTROL APPLICATIONS 

Interference by the anti -parallel diodes 



INTRODUCTION 

Certain industrial drives used in robots, servos and 
avionics must be capable of exceptional perfor- 
mance to allow for very rapid speed variations. 
The phenomena involved, especially when braking, 
has been analysed to determine the stresses on the 
power devices in a bridge circuit driving a small 
dc permanent magnet motor. Although this inves- 
tigation was carried out on a dc motor, the con- 
clusions are of general validity for almost all motors. 
The purpose of the investigation was to locate 
the dangerous conditions created by the reciprocal 
influence of the power transistor (or darlington) 
and the associated fast recovery diode. 



When braking the motor abruptly, the motor 
current reverses with respect to the previous phase, 
this is a consequence of the rotational energy 
stored in the motor which is converted into elec- 
trical energy and fed back to the filtering capacitor 
in parallel with the bridge. 

Very high di/dt values are associated with these 
conditions due to both the switching of the bridge 
components and the fact that the supply generator 
faces a low impedance. These are highly critical 
conditions and the result can be very dangerous 
for the electronic components. 



Fig. 1 - Current flows during normal drive and braking conditions 

V r 




SU -1001 



Continuous line - current path during normal drive conditions 
Dashed line - current path during braking when Q2 and Q3 are off 
Dash-dot line - current path during the conduction of Q2 and Q3 



265 



PINPOINTING THE PROBLEMS 

A) Diode peak forward voltage - during the condit- 
ions mentioned above the bridge components 
experience a transient voltage due to an over- 
shoot of the forward voltage drop of the diodes 
at turn-on (V Fdyn ), which is particularly high 
if the di/dt is large. This voltage is a transient 
high, negative V CE value for the transistor in 
parallel with the diode. 

B) Positive steady state V F - The transistors 
are not in the normal bias condition for the 
entire period of conduction of their associated 
diodes (i.e. Q1 and Q4 in Fig. 1 ). 

C) Recovery of the CB junction - By far the most 
serious phenomenon occurs when the diode 
turns-off and the transistor, although forward 
biased does not conduct. The recovery of the 



diode takes place in parallel with the recovery 
of the base-collector junction of the transistor, 
this junction acts as a slow recovery diode. 



FAILURE ANALYSIS 

The failure mode of the device has been simulated 
on a curve tracer by forcing a reverse breakdown. 
The component put under the extreme conditions 
of failure in a real application was a SGS50DB045D 
TRANSPACK module in half bridge configura- 
tion implementing the left or right hand side 
of the circuit in Fig. 1. i.e. Q3, Q4 and the as- 
sociated fast recovery diodes. Each transistor is 
made up of three fast darlington chips in parallel 
without parasitic c-e diodes and each diode is a 
single chip fast recovery epitaxial diode. 



Darlington type SGSD310 
Diode type SGS8R20 



Photo 1 - Darlington chip inside a SGS50DB045D which failed under extreme working conditions 




Photo 2 - A magnification of the damaged area 




266 



To make measurement easier a single chip darlington 
type SGSD310, analogous to the SGS50DB045D, 
was damaged intentionally on the curve tracer 
by a reverse collector to emitter breakdown 
(the SGSD310 chip can typically withstand up to 



12 or 14V in this condition). 

It is evident that the failure mechanism is the same 
in both cases and consequently, the operating con- 
ditions that can force the transistors into reverse 
conduction must be investigated. 



Photo 3 - The SGSD310 chip which failed during simulated overstress conditions 




PEAK FORWARD VOLTAGE OF 
THE DIODE 

The peak forward overvoltage (Vpp) on the 
bridge diodes is generated by very rapid current 
variations. In order to evaluate these variations 
a discrete bridge was constructed to make the 
diodes accessible for measurement. Each switch 
in the bridge was made up from three SGSD310 
darlington transistors and one SGS8R20 diode, 
i.e. the configuration as one switch inside the 
TRANSPACK module. 

The motor was accelerated abruptly bringing 
the duty cycle from 50% (zero speed) to 85% , 
and then braking to zero speed again in four 
subsequent steps. Values of di/dt as high as 50A/ms 
caused by the current generated during braking 
were observed on the diodes. 

Taking into account that the discrete simulation 
implies stray inductances substantially larger than 
those inside the TRANSPACK module, the di/dt 
values inside the TRANSPACK are expected to 
be greater. In practice the connections inside 
a TRANSPACK are approximately 3cm long, 
while in the bridge constructed with discrete 
devices they are about 15cm long. 



Fig. 2 ■ 



Waveform of the braking current through 
the diode 




Following the above findings, some SGS8R20 
diodes were tested with di/dt = 50A/ms using the 
circuit shown in Fig. 3. 

Fig. 3 - Basic schematic of the circuit used to 
measure V p 



O- 




O v cc 



The peak voltages obtained under these con- 
ditions (V F dyn.) range from 7 to 9V. 

A direct measurement of Vpp inside the 
TRANSPACK module was also carried out. A 
special configuration was used putting a 2.2KH 
resistor in series with the diode chip where the 
forward voltage peak was measured. In this case 
peak voltages of about 18V were recorded, such 
a high value is due to both the V F p of the diode 
as well as the stray inductance of internal con- 
nections. The oscilloscope photograph (Photo 5) 
shows the diode peak forward voltage inside 
the TRANSPACK module. 

In the cases described the energy level is never 
high enough to imply transistor failure, due to 
the relatively low voltage and short length of 
time under stress. 



267 



Photo 4 - 



Vpp and current waveforms measured 
on the diode in fig. 3 




V FP at di/dt = 50A/ms: 

— Upper waveform V F (5V/div) 

— Lower waveform I (1A/div) 



Photo 5 - Peak forward voltage in the TRANSPACK 
diode: 10V/div, W^s/div 




At diode turn-on, the transistor base is normally 
in the off-bias condition. There might be cases 
(in exceptional transistory conditions) of positive 
base bias at diode turn-on, mainly if the mech- 
anical load accelerates the motor shaft instead 
of breaking it. However not even in this extreme 
case can the forward voltage peak cause transistor 
failure. 



junction is positively biased and consequently 
heavily saturated, with the emitter acting as a 
collector and vice-versa. In these conditions the 
turn-off time of the device is quite long, in the 
range of a few microseconds. 

This inverse conduction of the transistor takes 
place during the conduction phase of the relevant 
anti-parallel diode. However, currents and voltages 
involved are small, and consequently during this 
"steady state" phase no overstressing of the tran- 
sistor due to power dissipation occurs. 



RECOVERY OF THE CB JUNCTION 

There is a substantial power dissipation at diode 
turn-off when V CE becomes high whilea significant 
time elapses before the current through the col- 
lector dissappears. This is mainly because the col- 
lector to base junction, forward biased during anti- 
parallel conduction, is slow in removing the stored 
charge when its biasing is reversed. 

This situation is shown in Photo 6 (waveforms 
refer to Q4 in Fig. 1) where it can be noted that 
at a V CE of 170V (the upper switch in the bridge 
has turned on), a current as much as 4A still 
remains in Q4, because the c-b junction has not 
yet depleted the stored charge from the previous 
phase of conduction. 



Photo 6 - 



Current and voltage waveforms during 
inverse conduction 




Upper waveform : V C p (50V/div) 
Lower waveform: l c (2A/div) 



TRANSISTOR BEHAVIOUR 
POSITIVE STEADY STATE V F 

During the braking phase another important 
phenomenon occurs: 

Transistors Q1 and Q4 (see Fig. 1) are negatively 
biased (collector to emitter by the conduction of 
their anti-parallel diodes). Their base to emitter 



It is important to understand why a transistor 
that is supposed to receive a negative base bias, 
during conduction of the anti-parallel diode, 
conducts even though it is in reverse mode. 

This actually happens when, instead of a negative 
bias, there is an unexpected positive base bias. 
In most cases an effective negative bias is applied 
to the base to turn off the transistor, and shortly 
after the turn-off phase a resistive path from 
emitter to base (Rbe' maintains the off -state. 



268 



During the braking phase (when the anti-parallel 
diode conducts) the base to emitter resistance 
becomes a path for positive base current when the 
emitter is more positive than the collector. This 
is the origin of reverse conduction in a transistor 



(or a darlington which has an integrated Rg£ in 
the final transistor). The value of Rbe ' s of P r in"> e 
importance as the smaller it is, the larger the 
reverse conduction current. 



Fig. 4 - The Rg£ of the final transistor becomes a positive bias element if the collector is negative 



9 + 



< 



<BE 




<? + 



4A) Positive collector: R BE sinks the leakage current and ensures the off-state. 



-1V 




-IV 



< 



=< 



Rbe 



SU-1002 



4B) Negative collector (V F of the anti-parallel diode) 

— The emitter acts as a collector and vice- 
versa; 

— Rg^ acts as a negative base current; 

— I B is multiplied by the gain (in reverse 
mode); 



A substantial charge is stored in the 
forward biased collector to base junction. 
It can take a few microseconds for this 
junction to recover to the off-state when 
the collector becomes positive again. 



CONCLUSIONS 

The analysis shows that the biasing of the col- 
lector-emitter junction of the bridge transistor by 
conduction of the free-wheeling diode, can over- 
stress it and even induce a failure. The origin of 
the failure is not only due to the peak overvoltage 
of the diode, since its duration is too short (about 
100ns) but primarily to the reverse conduction of 
the transistor during turn-off of the bridge switch. 
The c-b junction therefore acts as a slow recovery 



anti-parallel diode and if charge has been stored 
in this junction it causes the greatest stress on the 
device. 

The transistor failure (disregarding the overstresses 
induced on purpose), is in practice triggered by 
more than the single switching phase described 
above, it is more a series of subsequent stresses 
at each switching cycle which leads the device 
into a critical state. It is also easy to appreciate 
that the failure concludes a phase of abnormal 
heating in a concentrated spot on the chip. 



269 



Whenever possible it is advisable to avoid alternate 
switching of the bridge diagonals, and only turn 
on one pair of the transistors when their conduc- 
tion is required. 

The overstress could be avoided by negatively 
biasing the base-emitter junction during the period 
of possible reverse conduction of the transistor. 
To maintain a negative V BE is certainly a solution, 
but its implementation could be costly with an 
auxiliary negative supply for each switch. On the 
other hand it is not possible to use a simple 
capacitor to store the charge for this purpose, as 
a motor drive circuit has a substantial duty cycle 
variation and a single value capacitor can only 
satisfy a fixed turn-off time. 

Another more classical solution could be the in- 
troduction of a low voltage (both forward and 
reverse diode) diode in series with the collector, 
as shown in Fig. 5. The drawback in using this 
method is the additional power dissipation, while 
there is the advantage of simple implementation 
in open loop systems. 



Fig. 5 ■ 



Circuit solution with a low voltage diode 
D1 




SU-1009 



BIBLIOGRAPHY 



national 



1. "Driving a DC Motor using TRANSPACK 3. "Fast Switching Diodes" 
SGS30DB040D" SGS Internal Note -January 1985 
SGS Internal note -January 1985 

4. Basics of Fast Recovery Diodes in Switching 

2. "Improved Transistorised Bridge Converters" Circuits" 

Philippe Naugest - Power Conversion Inter- SGS Internal Note - June 1985 



270 



PARALLELING TRANSPACK MODULES 

A practical example 



INTRODUCTION 

The requirement for a higher current rating than 
a single module can provide is not uncommon, 
but the circuit designer probably questions the 
practical feasibility of paralleling large transistor 
modules such as the SGS TRANSPACK. 

Although these device are more complex than 
discrete transistors, in practice they can be par- 
alleled quite easily, the main point to keep in mind 
is current sharing between the paralleled modules 
during turn-off when loaded inductively. 



THE MOST COMMON CASE 

Different kinds of SGS TRANSPACK modules 



offer practically the same power switching capa- 
bility. If a device is rated for a higher voltage, it 
will consequently be rated for a lower current. 

As a result, it is clear that the most common case 
of paralleling occurs with high voltage parts. 

The SGS30DA070D has been selected for this 
example as it represents the highest current rating 
in the high voltage range of TRANSPACK modules. 



SGS30DA070D IN PARALLEL 

Four modules were used for the practical in- 
vestigation and the relevant h FE curves versus 
l c can be seen in Fig. 1 . 



Fig. 1 - hp E curves of four SGS30DA070D modules 

h F E 

1000 



100 



10 



o 


VCE " 5 VOLT 


: i^=^_ 




■ 




: 


: 



A=h FE (3) 30A 3V TYP 60 

B 100 

C - " - 130 

D 250 



20 30 50 

271 



100 



The h FE variation between module A (h FE typical 
60) and module D (h FE typical 250) represents a 
significant spread and by using one with high gain 
and two with low gain in parallel it has been pos- 
sible to simulate extreme operating conditions. 



Fig. 2 - Output characteristics of three paralleled 
modules 



Fig. 4 - 




Turn-off transition of three SGS30DA070D 
modules in parallel 




t = 200ns/div. 
V CE = 50V/div. 
I c 1,2,3 = 5A/div 
V cc = 200V 



BE (extraction; 



'B (extraction) 
l stg (storage) = 



= -3V 
17A 



27,us 



In the oscilloscope photograph the three collector 
currents are shown seperately, the device with the 
higher h FE exhibits a current overshoot and as 
consequence an increased storage time. 



The curve tracer photograph Fig. 2 shows the 
output characteristics of the three SGS30DA070D 
TRANSPACK power modules in parallel and 
Fig. 3 shows the forward bias safe operating area 
for the same parallel circuit. It can be seen from 
these SOA characteristics that for normal pulsed 
operation, the paralleled modules can safely handle 
very high power levels. 



Fig. 5 - RBSOA test driving circuit 



Fig. 3 - Safe operating area (forward bias) 
three SCS30DA070D in parallel 



of 




The most important point for consideration is the 
turn-off switching transition shown in Fig. 4, the 
three modules have a seperate bias circuit which 
consists of two resistors (3.3k and 100f2) and a 
single speed-up diode. 




li «c.a 



6-5 



Fig. 6 - RBSOA of a single SGS30DA070D 




272 



The reverse bias safe operating area was obtained 
using the test driving circuit shown in Fig. 5. The 
RBSOA characteristics for a single module (Fig. 6) 
and the three modules in parallel (Fig. 7) show 
that the high voltage boundary is the same for both 
arrangements. 

Fig. 7 - RBSOA of the three devices in parallel 



50 -r - ~ 






' ^CEIcl 



The addition of a 1.2S1 resistor in the test driving 
circuit to limit the negative base current improves 
the high voltage boundary of both RBSOA charac- 
teristic curves, the dotted line corresponds to the 
new boundary. 



THE BEST CHOICE 

This example demonstrates the performance of 



devices which were not specifically selected for 
the test. A further improvement can be achieved 
if parts with very close h FE values are paralleled 
together, ideally the three parts should remain 
within a ± 10% h FE range. 

h FE matching ensures that the paralleled parts 
have almost the same storage time and that none 
of them supports the entire load current, duringthe 
interval between turn-off of one module and 
turn-off of the other two. 

The high switching speed of SGS devices helps 
to minimise any minor variations between matched 
modules. 



CONCLUSIONS 

Care must be taken to ensure that current is 
equally shared between paralleled modules and 
layout is optimised to reduce stray inductance in 
the interconnection leads. 

The easiest way to ensure a fair sharing of the cur- 
rent is by adding a seperate speed up diode and 
bias resistor network to each module. However, 
this will not prevent the possibility of current 
overshoot in one module during turn-off (as shown 
in Fig. 4) so for optimum results it is best to ensure 
current matching during turn-off. 

The most practical way is to use parts with h FE 
values within a ± 10% band for paralleled ope- 
ration. SGS TRANSPACK power modules can 
be supplied in gain groups to suit customer ap- 
plications. 



273 



ROBUSTNESS OF HIGH VOLTAGE POWER 
TRANSISTORS 



INTRODUCTION 

Most semiconductor manufacturers publish safe 
operating area (SOA) curves of some form in 
their data-sheets. These published curves are 
intended to convey to the user, the electronic 
equipment designer, a measure of the device 
robustness. The forward bias safe operating area 
(FBSOA) indicates the collector emitter voltage 
and current capability with the base emitter 
junction forward biased. The reverse bias safe 
operating area (RBSOA), as the name implies, 
indicates the collector emitter voltage and current 
capability with the base emitter junction reverse 
biased. This curve is used to determine the locus 
of the transistor operating point during the tran- 
sition from forward biased conduction to the 
cut-off state. 

Generally speaking, safe operating area curves 
have been published for the transistor case tem- 
perature at 25° C. Derating is required, the amount 
being dependent on the transistor operating tem- 
perature and the temperature derating factor. Dif- 
ferent derating factors are applied by some manu- 
facturers to different parts of the SOA curve, 
depending on the failure mechanism which limits 
the transistor performance in that area. Thus, it is 
common to see both 'power derating' and 'l 5 y b 
(second breakdown) derating' factors published. 
Additions to the standard SOA curves are being 
made as the capabilities and the understanding of 
the process technology are improved. In particular, 
extensions above the Vfj EO rating of the transistor 
are seen in both FBSOA and RBSOA curves to 
indicate the transistor capability during 'switch-on' 
and 'switch-off transitions. 

Non repetitive overload safe area curves are also 
appearing, and these will be found particularly 
useful in the motor control area However, a degree 
of caution is necessary on the part of the design 
engineer in interpretation of this additional in- 
formation. The semiconductor manufacturer will 
have defined the test conditions for which the 
overload safe area curve applies. Disparity between 
the application circuit and the semiconductor 
manufacturers test circuit, including any precon- 
ditioning, can cause significant differences in the 
ability of the transistor to withstand an overload. 



FORWARD BIAS SAFE OPERATING AREA 

The forward bias safe area for the SGS BUX48/ 
SGS BUV48 transistor families is shown in figure 
1. The curves apply for a case temperature of 
25°C. The lower curve represents the continuous 
conduction case, with collector current, l c , limited 
to 15 amps and collector emitter voltage, V^e 
limited to 400V, or 450V for the 'A' part, 600V 
for the 'B' part or 700V for the 'C part. Beyond 
the 15A 10V point on the curve, the current 
rating falls in conformance to the maximum power 
rating of the transistor. There are 2nd and 3rd 
break points (charge of gradient) on the curve at 
6A and 0.2A. In these areas the transistor is no 
longer limited by total power rating, but by 
second breakdown. 



Fig. 1 - BUX48/BUV48 forward bias safe operating 
area 

3-479 7/2 




V CE (V) 



The outer set of curves represent the pulse current 
capability, as opposed to the DC capability of the 
transistor. The rating applies for a single pulse, 
so that the duty cycle effect and resulting tem- 
perature increase is discounted. All of these curves 
are terminated at the V CEO rating (400V - 700V) 
of the transistor. A small additional area, marked 



275 



'I' has been added, and represents the permissible 
area of operation for 'turn-on' from a voltage in 
excess of Vq^q- 

Figure 2. Illustrates the overload SOA for the 
BUX48 transistor. The SOA applies for a maxi- 
mum case temperature of 125°C and for a single 
pulse of 20ms duration. The lower, hatched area of 
the curve is the normal FBSOA. Repetitive pulses 
are permitted in the hatched area, provided that 
the thermal limitations of the transistor are com- 
plied with. 



Fig. 2 - BUX48 overload safe operating area 



CSM_ 














[ 










1 


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(A) 








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200 300 400 V CE (V) 



from which the curve has been derived are: Case 
temperature 125°C and base emitter reverse bias 
of 5V. The tests were performed with an inductive 
load, and with the collector emitter voltage ap- 
propriately clamped. The reverse bias SOA is, by 
it's nature, always a transient test condition. For 
this reason, time is not a control variable. The 
'switch off time of the transistor is determined 
by the test conditions. 



SAFE AREA TEST CIRCUITS 

The circuits shown in figures 4a and 4b illustrate a 
relatively simple way of measuring the FBSOA for 
the BUX48 and BUX98 transistor families respect- 
ively. Resistor R1 value is chosen to provide suf- 
ficient base current to saturate the transistor at 
the peak collector current which is, in turn, set by 
resistor R2. The resistor values shown are suitable 
for testing the transistor at rated DC collector 
current (15A and 30A respectively). The first 
step in the test cycle is to charge the high voltage 
capacitor, C to the appropriate voltage (Vceo 
rating of the D.U.T.) with the base drive switch 
'open'. The second step is to 'open' the capacitor 
charging switch, so disconnecting the high voltage 
supply from the test circuit, and to close the 
switch providing the forward base current. Closure 
of the switch turns on the T.U.T. which sub- 
sequently discharges the capacitor C through 
resistor R2. 



Fig. 4 - Forward bias safe area test circuits 



Fig. 3 - BUX48/BUV48 clamped reverse bias 
safe operating area 

































Cj- 5 2 


j 




If 





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BUX48 




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100 200 300 400 500 600 700 v CE(clamp)( »> 



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+L 



REVERSE BIAS SAFE OPERATING AREA 

The clamped reverse bias safe operating area for 
the SGS BUX48/SGS BUV48 family of transistors 
is illustrated in figure 3. This curve should not 
be confused with the overload forward safe area 
previously mentioned. The conditions under which 
the tests were made in order to achieve the results 



The operating point for the transistor follows the 
locus illustrated in figures 5 and 6. As the test is 
a 'one shot' measurement, temperature rise in the 
T.U.T. is negligible and the case temperature 
remains at 25°C. 



276 



Fig. 5 - Theoretical operating locus in FBSOA test 



Amps 




returning the inductive energy stored in L to the 
supply, Vg. Resistor R3 connected in series with 
the rectifier D1 shapes the load line and so deter- 
mines the locus of the operating point of the 
T.U.T. during 'turn off. The peak voltage across 
the T.U.T. will be: 



'CEpk 



Vr + I 



Cpk 



R3 + V F D1 



This simple equation neglects the effects of circuit 
wiring inductance and the forward recovery time 
of the rectifier, D1 . Some adjustment in Vgor R3 
value may be required to compensate for these 
effects. Figures 8 and 9 illustrate the locus of the 
operating point of the T.U.T. during 'turn off. 



Fig. 6 - Oscilloscope display of operating locus in Fig. 7 - Reverse bias safe area test circuit 
FBSOA test 



•c 

12A 



1 I | , I I 

— h — i — AH — i — ' — ^ — i- 
; ■ \ '■ _:__: \ 



-: I. 7 k 






T' 



: V CE600V | 




Fig. 8 - Theoretical operating loci in RBSOA 
tests 



gh Cu-er* RBSOA Test 




i.gh Voltage RBSOA 
Test 



The reverse bias SOA test is performed in 2 stages. 
This is to achieve a 'best fit' to the SOA curve. 
The first part of the test exercises the high current 
RBSOA extending up to the V CEO for the tran- 
sistor. The second part exercises the low current, 
high voltage area extending to V ce r. Figure 7. 
Illustrates the test circuit. Switch 1 closes to turn 
the T.U.T. 'on'. The condition time is controlled 
to limit the peak collector current. 

As switch 1 opens, switch 2 closes reverse biasing 
the base emitter junction of the T.U.T. Following 
the storage time delay, during which time the 
excess charge in the collector base junction is 
extracted, the collector emitter voltage rises instan- 
taneously to Vg when the rectifier, D1 conducts 



Fig. 9 - Oscilloscope display of operating loci 
in RBSOA test 




a) BUX48A High Current RBSOA 



277 



Fig. 9 (continued) 



ic 

2A 




b) BUX1.8A High Voltage RBSOA 




c) BUX98A High Current RBSOA 




dl BUX98A High Voltage RBSOA 



It is important when making measurement of 
RBSOA using an oscillospope with X-Y display 
that the time delay in both X and Y amplifiers are 



reasonably well matched. Otherwise, significant 
distortion of the operating locus display may 
occur. 



POWER MOS TRANSISTORS 

These are majority carrier devices which inherently 
do not exhibit the second breakdown phenomena 
that have plagued their bipolar counterparts. A 
glance at the FBSOA curve for a POWER MOS 
transistor will show that the device has a 'square 
loop' SOA capability, limited only by the power 
dissipation and maximum junction temperature of 
the semiconductor dice. The FBSOA extends all 
the way up to the BV DSS , the drain source break- 
down voltage rating. The inherent current sharing 
ability and the independence of it's transconduc- 
tance from l D , the drain current, allow the POWER 
MOS transistor an increased surge current rating 
when compared with a bipolar transistor of 
equivalent DC current rating. There are no sep- 
arate RBSOA curves for the power MOS device, 
the FBSOA can be used as the forward and reverse 
bias conditions are similar. 



POWER MOS IN AVALANCHE BREAK- 
DOWN 

SGS along with the majority of semiconductor 
manufacturers producing POWER MOS transistors, 
do not publish data, or recommend the use of 
the drain source avalanche capability of the device. 
There are several reasons for adopting this policy: 

Avalanche energy capability is : 

— not a function of dice size alone. 

— drain current dependent. 

— temp, dependent. 

— dv/dt dependent. 

A consensus of opinion on the failure mechanisms 
involved has not been seen. 

Long term effects of operating in avalanche break- 
down mode have not been evaluated. 

In time, improvements in the understanding of 
the capabilities of POWER MOS transistors will 
emerge and the manufacturers will doubtless 
publish more definitive information. 



278 



TECHNOLOGY RELIABILITY AND APPLICATIONS 
OF SGS HIGH VOLTAGE NPN TRANSISTORS 



Introduction 

The basic technology chosen for high voltage 
(V CEO > 400V - V CBO > 600V) transistors is 
fundamental to their in-circuit performance as well 
as their "built-in" reliability. 

Also the technology effects the wafer size which 
may be used in production, as well as the yields. 
In some cases also packaging options may be 
restricted. These are important factors influencing 
the price and availability for any semiconductor 
device. 



Subject 

This note discusses the SGS Multiepitaxial Mesa 
process used for a wide variety of industry standard 
products as well as some innovative types. 

This technology is illustrated in simplified form in 
figure 1, figure 2 shows an actual cross section of 
the edge of a die made up of several scanning 
electron microscope pictures. 



Fig. 1a - Multiepitaxial Mesa wafer simplified cross section 




279 



Fig. 1b - Mult/epitaxial Mesa die in plan view 




Fig. 2 - Actual section of Mesa edge termination 




Features of the technology 

Starting with an N + wafer, the N and N" collectors 
layers are grown in specially developed epitaxial 
reactors, to produce the layered structure of the 
collector for the H.V, transistors. 

The thicknesses required are much higher than 
used in integrated circuit technologies. 

The intermediate N layer was interposed for the 
main purpose of achieving a very high E s / B and 



RBSOA capability. 



An additional P" layer is then grown, to increase 
the voltage breakdown. For this first critical phase 
SGS is fully equipped to grow epitaxial layers 
entirely "in house" while other power transistor 
manufacturers are mostly dependent on outside 
suppliers. 

The P + base is produced by diffusion of boron into 
the final P- layer and the N+ emitter is diffused 
into the base. It is important to note that during 
this processing a relatively thick wafer is being 



280 



handled allowing SGS to use 4" and 5" wafers 
with ease. 

Following diffusion is the etching of the mesa 
which is filled with a very pure glass by an SGS 
patented selective deposition process which avoids 
any contaminants such as photoresist which may 
not be entirely evaporated during the fusion of 
the glass. The aluminium top metal is now deposited 
and the pattern defined. The entire top of the 
wafer is now protected by a thick deposited oxide 
in which windows are opened for bonding the base 
and emitter connecting wires. 

Finally the wafer is reduced to the correct thickness, 
removing the excess N+ silicon by grinding the 
back of the wafer, after which the back is metallized. 

Packaging 

As the die must be separated from the wafer before 



mounting in the package the fact that SGS cuts 
the silicon outside the mesa and its glass filling, 
eliminates the risk of mechanical damage to the 
passivation. 

As the sawing creates a short circuit at the edge of 
the die from the collector to the field plate no 
"flashover" can occur in the package between 
the header which is at collector potential and the 
top of the die, which in alternative half mesa tech- 
nologies will be at base potential. The surface is 
covered with a thick oxide as previously mentioned 
so no arcing occurs along the surface. 

This process of passivation also ensures high 
reliability in plastic packages. 

This technology also allows wafers to be 100% 
probe tested to high voltage specifications, an 
important point for users of high voltage transistors 
in chip form for hybrid assemblies. 



Fig. 3 - Section of Mesa with simulated equipotential lines 

THERMAL OXIDE P + 



BOFtON IMPLATED P 



GLASS AL EQUIPOTENTIAL RING 




Reliability 

In the reliability of a high voltage transistor the 
voltage stress on the surface of the silicon in the 
region of the collector/base interface is very 
important. This region must be protected from 
contamination. By terminating the collector-base 
junction on the edge of the mesa, and using glass 
the sealing against potential contaminants is as- 
sured. The use of the aluminium field plate ensures 
the glass is kept at a constant charge. The surface 
of the P layer is treated with an ion implantation 
to ensure a very well controlled surface doping 
thus aiding close control of the electric field 
strength distribution and leakage currents. SGS has 
developed computer simulation programs which 
can predict the field strength enabling the design to 
be optimised for reliability. Figure 3 shows the 
equipotential lines superimposed on the actual 
device cross section demonstrating the low stress 
on the surface. 

SGS continually monitors the reliability of the 
process by sampling production on a weekly basis. 
The high temperature reverse bias test (HTRB) is 
used to evaluate the stability and quality of the 
passivation. 

Devices are subjected to T amb = 125°C with the 



base-emitter shorted, and 600V d.c. is applied to 
the collector. Figure 4 shows typical results of 
leakage currents measured at V ces = 900V, a 
point on the line at 45 degrees indicates no drift in 



Fig. 4 ■ 



Leakage current stability in HTRB life 
tests 



1000 h) ' 


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281 



leakage. It is important to note that the currents Fig. 6- 
involved are much lower than the specified maxi- 
mum allowed by the data sheet. The devices with 
significant drift are those with initial leakage below 
1mA and they remain below 80mA following 1000 
hours of extreme stress. 

Application hints 

The basic rules of application for fast switching 
high voltage devices apply equally to SGS devices as 
well as other manufactures who use different tech- 
nologies however some points deserve particular 
mention. 

The multiple epitaxial structure with its "energy 
layer" provides an exceptional RBSOA, figure 5 
shows the RBSOA of the BUX48/BUV48 which 
can sustain up' to 2A at 700V or 15A at 400V 
during the device turn-off with an inductive load. 

Figure 6 shows the accidental overload safe op- 
erating area. The safe limit, up to 80A at any volt- 
age up to 400V, is independent of the transistor 
base current, the lines with different base current 
indicate the maximum current which can be Fig. 7- 
expected when the load is short circuited for any 
supply voltage. The overload must be sensed within 
20 microseconds and the base drive removed at 
which time the accidental overload reverse bias safe 
operating area, shown in figure 7, will apply. 

This data shows that for occasional non-repetitive 
overloads the multiepitaxial structure is excep- 
tionally robust. As an indication devices have 
been stressed to 80A/400V for 40 microseconds 
during the on phase and then turned off at a P.R.F. 
of 100Hz for 4 hours without degradation - nearly 
1.5 millon pulses! 

Attention should be paid to correct turn-on base 
drive. The BUX48/BUV48 data shows the dynamic 
V CE (sat) characteristics (figure 8) which are signifi- 
cantly improved by ensuring an overshoot of l B j 
illustrated in figure 9. 



Accidental 
BUV48 



overload SOA of BUX48/ 







































S237 


1 


CSM 






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(A) 






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|T case = 125-C 








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Accidental overload RBSOA of BUX48/ 
BUV48 

G-5489 



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100 200 300 400 500 600 700 V, 



'CE(clamp)' 



Fig. 5- RBSOA of SGS BUX48/BUX48A (TO-3), 
BUV48/BUV48A (SOT-93) 

G- 5230 



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II 



Fig. 8- Dynamic V CE ( sat ) of BUX48/BUV48 

^ G- 5227<l 

v CE(sal) 



100 200 300 400 500 600 700 »CE(clamp)< v > 







\ 




i 










V 




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I C =10A ,I B = 2A 
WITHOUT SPEED UP 




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c WITH C=50nF 






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WITH SPEED 
UP CAPACITOR 
T C a 5e = "-C 






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3 




'or 


Z^s) 



282 



Fig. 9- Igf waveform for improved dynamic saturation 



Vce (sat) dynamic test circuit 

+ V BB = 14 V 



SGS P421 f 




SGS P421 k 820A 4.7 Jl 



Equivalent input schematic circuit at turn-on 



X-i: 



if C *>C; AV- = AV; 



Remarks to V CE ( Sat: ) dyn. test circuit 




The speed-up capacitor decreases the V c r£ (sat) dyn- as shown in the 
diagram and modifies the shape of the base current with an overshoot. 



283 



A slow rise time of l B i can result in extremely high 
turn-on losses, as shown in figure 10 the multi- 
epitaxial device will have a V CE of around 40V for 
some microseconds. This results in higher junction 
temperatures and in turn longer turn-off switching 
times, sometimes these longer turn-off times are 
misinterpreted as being a "cause" rather than an 
"effect". This can be cured by similar solutions as 
used to improve dynamic V C f£ (sat)- 

Conclusion 

The Multiepitaxial Mesa process has been demon- 
strated to be a high volume, cost effective process 
yielding products with high intrinsic reliability and 
exceptional ruggedness to enhance field reliability. 

The process is very flexible being readily "pilotable" 
to produce higher voltage or higher current "sub 
families" with good yield, thus avoiding the risks 
for both the user and the suppliers of selections 
from lower performance types. 



Fig. 10 -High turn-on loss caused by too slow Ig-j 
rise time 



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284 



SECOND BREAKDOWN 
IN POWER TRANSISTORS 



One of the basic failure machanisms in power tran- 
sistors is second breakdown. 

Under this term, various physical phenomena 
which are completely different are included. They 
depend on the different use of transistors in the 
circuits and have in common the electrical and 
thermal instability inherent in transistors them- 
selves. 

The conduction behaviour of an emitter base junc- 
tion and the current gain of a transistor depend 
significantly on the temperature and increase as a 
function of the temperature. Electrical and thermal 
instabilities may simultaneously act within the 
device, thereby giving rise to destructive second 
breakdown mechanism. 

An understanding of this mechanism is of great 
importance for a safer and optimum application of 
a power transistor. 

A distinction should be made between direct 
second breakdown < i s/t> or more commonly SOA), 
which is distinguished by a normal direction of 
base current Ib (entering in an NPN transistor) and 
inverse second breakdown (E s /t>), when I b is in the 
opposite direction (extracted from an NPN tran- 
sistor). The limits to which a transistor may be 
used without entering into E s /b are defined by the 
reverse bias safe operating area (RBSOA). 



DIRECT SECOND BREAKDOWN (l s /b) 

An important information for the power circuit 
designer is the locus of lc - Vce points defining 
the boundary between stable and unstable operation 
of forward biased transistors. This locus defines the 
SOA (safe operating area) that is the area of the 



logic - logVcE plane which may be used without 
any risk in DC current conditions or with different 
width pulses at a known temperature. A typical 
SOA is shown in Fig. 1. 

The limits of this area are the following: 

1) The A-B section represents the upper limit of 
the collector current that may normally be used, 
generally limited by wire bonds. Operation at 
higher currents may cause damage to the 
wires of their bonding. 

2) The B-C section is the -1 slope curve section 
(i.e. the section with constant dissipation) 
defined by: 

. . . D (Tjmax - T ) 

VcE x lc = Pmax = - 



Rth 



Fig. 1 - Safe operating areas 



(A) 



,MAX PULS. - rrmni-Ti 4 — P h+4i- 




CE (V) 



285 



4) 



This section therefore indicates the maximum 
dissipable power of the device, Tjmax is the 
maximum temperature which the collector-base 
junction may reach, over which the device 
reliability may be compromised. In power tran- 
sistors, Tjmax varies between 125 and 200 de- 
grees C and generally depends on the metallurgy 
and the type of package. 

Rth is the thermal resistance between the 
collector-base junction and the case, including 
all the silicon and package system. It may be 
observed that the increase of the maximum dis- 
sipable power when the pulse width decreases 
(Fig. 1 ) corresponds to the decrease of Zth with 
respect to Rth. 

The section C-D corresponds to the second 
breakdown phenomenon (or l s /t>) and limits 
the maximum power that the transistor can 
dissipate. This may occur even at relatively low 
Vce voltages. 

The section D-F is the limit due to the transistor's 
BV CE o. 



sideration, it may be seen that a pulse of power 
P = Vce x lc generates: 

a) an increase of the junction temperature, giv- 
ing rise to an increase of l B and h FE , there 
fore to an increase of lc, with a following in- 
crease of P and, therefore, a further temperature 
increase. 

b) a dissipation to the external environment, con- 
trolled by the thermal resistance R^ n = dT/dP 
which tends to stabilize the device. 

The situation evolves towards stability when: 
AlC2 3lc 



Alex 3T 



x Vce x Rth is smaller than 1 , or in- 



stability if > 1. 

In this way, a, stability factor may be defined 
that will be a function of Vce and lc: 

9I C 



S = Rth x V C e x 



3T 



Second breakdown is generated by the electrical 
and thermal instability of the transistor. The main 
causes of this instability are; 

1) The Vbe °f a directly biased base-emitter 
junction, at constant current, decreases linearly 
with temperature, with a = 2 to 2.5mV/°C 
slope. The base current of the transistor may 
therefore be expressed by: 

, , (Vbe-*T) 
lB = loxe q — 

IS. I 

and, when Vbe is kept constant, it increases 
with temperature. 

2) The hFE at the relevent voltage values increases 
as a function of temperature according to the 
law: 

hFE = hFEox e (AEg/KT) 

where AEg is an activation energy which is a 
feature of the transistor. 

3) The thermal conductivity of silicon decreases 
when temperature is increased, therefore worsen- 
ing the thermal resistance of the transistor. 

When these three phenomena are taken into con- 



When S > 1 so called "thermal runway" occurs and 
the junction temperature increases without any 
limit, therefore degrading and possibly damaging 
the transistor. The failure generally occurs when 
the surface temperature becomes greater than the 
eutectic temperature between silicon and the 
contact metal (front aluminium) with a consequent 
melting of the alloy. 

Also, it may happen that a localized temperature 
increase damages the crystal, or that the inner 
temperature of the device reaches values high 
enough to melt the silicon. 

For the understanding of U/b phenomena giving 
rise to a reduction of the maximum power that 
the transistor can dissipate as Vce increases (zone 
D - E) it is necessary to take into account that 
device operation isn't homogeneous on all the dice 
area. There are disuniformities in the emitter base 
current density, that may be due to junction 
disuniformities, crystal defects and, most of all. 
to the emitter edge concentration phenomenon. 

The voltage drop due to the base current flowing 
through the cross resistance rbb' gives rise to a 
disuniformity of Vbe at the junction, therefore 
to the disuniformity of the current density Jg 
(see Fig. 2). 



Fig. 2 




286 



A side drop of 26m V reduces by a 1/e factor the 
injected emitter current. 

A concentration is therefore generated of the cur- 
rent at the emitter periphery, therefore the active 
silicon area is reduced and hot spots occur, leading 
to an effective increase of the thermal resistance. 
As a result, the maximum dissipable power is 
decreased. 

When Vce is increased the effect of the base - 
collector electric field is to increase the base cur- 
rent concentration. 

Different techniques may be adopted to limit 
the l s /b phenomenon. Fundamentally, they consist 
of minimising the mechanisms that trigger electrical 
and thermal instabilities in the transistor. The basic 
techniques are: 

1) Minimization of crystal damages, metal im- 
purities and of doping disuniformities. 

2) Optimization of package and die attach tech- 
niques, to minimize the thermal resistance on 
which the stability factor S depends. Disu- 
niformities of silicon die bondings to the case 
may give rise to adverse variations of Rth as a 
macroscopic parameter for the dice as a whole, 
but also to significant variations between differ- 
ent points, giving rise to premature second break- 
down. 

3) Increase of the base thickness to reduce the 
high current densities (due to emitter crowding) 
flowing through the collector base junction 
(where the electric field is localized), so that 
the density of the dissipated power is decreased. 
High base thicknesses, however, will result in 
lower cut off frequencies and slower switching 
times. 

4) Optimization of the horizontal geometry. 

5) Introduction of distributed ballast resistances 
connected in series with the base, the emitter 
or both, which tend to give a' negative feedback 
to thermal runaway, therefore stabilizing the 
device. Fig. 3 shows the Je/Vbe characteristic 
curves for two points in the junction, at dif- 
ferent temperatures (T2 > T1). 



Fig. 3 




It may be seen that the introduction of a ballast 
resistance in series with the base or the emitter 
may reduce from J3 to J2 the current density in 
the hot spot. 

The emitter ballast resistance is generally obtained 
by opening emitter contacts thinner than the 
emitter strip (Fig. 4). 

In this way it is possible to limit the current density 
at the boundaries of the emitter. These resistances 
show the drawback of increasing the saturation 
voltage of the transistor by the amount VcEsat 
= R EX Icsat- 

On the other hand, the base ballast resistance is 
obtained through a "l\l + pocket" (in the case of 
NPN), around the emitter area (see Fig. 5). This 
N + diffusion, being unbiased, can't be traversed 
by the base current, that is therefore forced to 
flow below the N + through a small section and, in 
the case of a diffused base, encounters a higher 
resistance on the way to the edge of the emitter. 
In this way, it is possible to significantly improve 
ls/b. 

It should be noted that the SOA limits are tem- 
perature dependant and suitable derating must 
be applied. 



Fig. 4 



m//////////////mj/w////////////m 




BASE 



COLLECTOR 



287 



Fig. 5 



JZ ^- 






-^77^ 



Rb 



5,-^0; 



- B M a - 



COLLECTOR N 



TdET 



Rb , 
-AAA/^i-WvM 



REVERSE SECOND BREAKDOWN 

The reverse breakdown phenomenon (E s /t>) is also 
due to thermal and electrical instability of the 
transistor. As already mentioned, it is distinguished 
from ls/b by the presence of a reverse Ib (i.e. 
with a direction opposite to the normal direction 
of a transistor operating in the active zone) and by 
high Vce values of the transistor. The device may 
be in these working conditions during turn off 
with an inductive load. 

In the following figure (Fig. 6) the common emitter 
characteristic curves for a transistor are shown. 



Fig. 6 



Fig. 8 




Fig. 7 




JT 





It may be easy to understand the behaviour of 
these curves when the common emitter gain ex- 
pression is considered: 

hFE = ap/1 - 3F (1) 

for high Vce values, aF is replaced with M x aF. 



288 



For low Vce values, M is an insignificant factor, 
being very close to 1. M increases when Vce is 
increased according to the following expression: 



M = 



1 



1 



1 -<VcE/BV CB o> n 



(2) 



From expression (1) and (2) it is evident that 
hpE depends on Vce, becoming infinite when 
M x a F = 1 (BVceo). 

The negative slope section, which is a feature of 
the curves with Ib < is due to the fact that aF 
decreases at low values of the emitter current. 

During turn off with an inductive load, the tran- 
sistor has to operate with negative base current and 
a high value of lc. It has often to reach a working 
area above Vceo, remaining there all the time 
required for the inductance to be discharged (see 
Fig. 7). Fig. 8 shows the behaviours of lc, Vce, 
Ib and the power dissipated by the transistor 
during turn off. 

The area of the dissipated power corresponds to 
the energy stored by the inductance 1/2 x L x I 2 , 
which is discharged into the transistor and this is 
called second breakdown energy (Es/b). 

Similarly to \ s/b , the voltage drop due to the 
reverse Ib flowing through the side resistance rbb' 
makes the centre of the emitter strip more biased 
than its periphery (Fig. 9). In this way, a current 
concentration occurs at the emitter centre. 



constant of silicon. When the collector current is 
limited to low values, expression (3) becomes (q 
being the electron charge): 



3E 
3X 



qNo 



(4) 



and the electric field behaviour is similar to that 
shown in figure 10 for Jc = J'l. 



Fig. 10 



CRITICAL FIELD 




SUBSTRATE 



Fig. 9 




Let's analyse the case of an NPN transistor with 
diffused base and epitaxial collector, i.e. with 
constant concentration ND of donors doping 
particles. 

Poisson's equation is recalled below: 



3E 
3X 



3 2 V _ 

'ax 2 " 



p(x) 



(3) 



The X axis is normal to the silicon dice surface, p (x) 
is the charge per unit volume, e is the dielectric 



The voltage Vcb (= Vce) is that given by the area 
of the E-X graph and is smaller than primary 
breakdown voltage, due to the reaching of critical 
field E C r. In the presence of significant values of 
current density Jc, the expression (4) is modified 
due to the n concentration of electrons flowing at 
the speed V through the depletion layer. 



3E 
~3X~ 



q(ND -n) 



where n : 



qV 



(5) 



At constant Vcb, the area limited by E has to 
remain constant. When Jc increases, the E-X slope 
varies (J'2) until its sign is changed (J'3) and Ecr 
is reached (J'cr). At this point avalanche multi- 
plication occurs locally of electron - hole pairs 
with an uncontrolled current increase and so 
a strip is formed with a very high temperature that 
gives rise to either crystal damage or silicon melting. 
Possible crystal defects, metal ions, junction 
disuniformities just further exagerate this phenom- 
enon. The avalanche multiplication is a very fast 
and very localized process, therefore the device 
remains externally cold. The E s /b behaviour isn't 
practically influenced by the die bonding quality. 
High Es/b values can be obtained with a proper 
design of geometry, to limit the current crowding 
and, most of all, by inserting a second epitaxial 
layer N of intermediate doping between the col- 
lector and the substrate. 

The intermediate layer creates the condition shown 
in Fig. 11. When the current density increases 
(J'2) the electric field at the interface l\T/l\l is in- 



289 



Fig. 11 




BASE 



COLLECTOR 



SUBSTRATE 



creased. Anyway, before the critical field Ecr is 
reached at this interface, the contribution of 
layer N becomes significant in sustaining the volt- 
age. A further density increase (J'3) reduces the 
electric field at the interface N/N and the break- 
down isn't triggered until the critical field is 
reached at interface N/N + . 

For a good power transistor with Vceo(sus) = 
450V the current density J' r c corresponding to 
E C r is in the order of 20A/mm 2 , greater by a factor 
10 when compared to the average current density, 
given by the ratio between maximum saturation 
current and emitter area. 

The E s /b behaviour is also influenced by the con- 
ditions outside the transistor, Rbe, Vbe, L. 

The base conditions are especially important, as 
they regulate the crowding phenomenon. 



Fig. 12 




(a) 



The most commonly used system by power design- 
ers to reduce the Es/b effect during turn off with 
inductive load is a clamping or 'snubber' circuit, 
that limits the voltage peak between collector and 
emitter. 

The presence of the clamping circuit (in Fig. 12 
for sake of simplicity it is schematized with a zener 
diode) allows only a minimal amount of the energy 
stored in the inductance to be absorbed by the 
transistor, and E s /b becomes independent of the 
value of L and practical RBSOA limits may be 
defined. 

It must be noted anyway that the presence of high 
Vce and negative Ib current may give rise at high 
current to the previously described E s /b phenom- 
enon, even in the presence of the clamping circuit. 

The multiepitaxial transistors show a better be- 
haviour even in the presence of a clamp. 

The reverse bias safe operating area (Fig. 13) 
establishes the maximum switchable current with 
inductive load versus clamping voltage in very 
harsh base conditions that simulate the real base 
driving conditions in the circuits. 

Note that the temperature is not a major factor in 
the Es/b and so the RBSOA rating can be considered 
to be independant of temperature. 

Fig. 13 





































G- 


5230 




'r. 








































(A) 










































































































' 


i 






































! ' 












H 


























SGS 




































BUV46 






































BUX48 


































' 






































































I 












8 


























r SGS 

BUV48 
BUX48 


A 

A 
















I 
































| 
































j 
































T case= 125-t 






























VrF 


= -5V 
























2 


























^l 




j 




























■,.[. 


















| 












! j 


iezl: 



100 200 300 400 500 600 700 v CE(clamp)< v > 



'c; v ce t 




CONCLUSION 

Second breakdown performance is a function of 
transistor technology and cannot always be im- 
proved without some trade-off in other parameters. 
The application conditions have a considerable 
effect on both l s /b and E s /b capability. 



290 



SGS HIGH VOLTAGE FAST RECOVERY DIODES 
AND THEIR SWITCHING PERFORMANCE 



INTRODUCTION 

SGS decided to introduce its line of power 
switching modules in the TO-240 TRANSPACK 
package. 

To solve the problem of providing fast recovery 
rectifiers capable of matching the high voltage/ 
high current of the transistor chips in the TO-240 
package, SGS was able to exploit its technological 
leadership in power semiconductors. The rectifiers 
were fabricated by epitaxial growth with high 
voltage termination structures. 

SGS was the first in the industry to introduce 
epitaxial growth for all its power transistors. 
Its epitaxy capability, fully in house, makes use 
of the fastest epitaxy reactors in the industry. 

This note describes the switching behaviour of the 
fast recovery rectifiers used in SGS TRANSPACK 
power transistor modules and the SGS35R120 
series of diodes. 

The turn-off and turn-on behaviour is described 
and the characterization is oriented to the con- 
ditions of practical use. 



The TRANSPACK product range and 
the internal diodes 



This report deals with the first three diode chips 
developed, table 1 gives their main characteristics. 



TABLE 1 



Type 


l F (A) 


VRRM (v) 


SGS35R80 

SGS35R120 

SGS60R40 


35 
35 
60 


800 

1200 

400 



The second table below shows the TRANSPACK 
product range and the relevant fast recovery 
rectifier used in each device. 



TABLE 2 



Type 

C/E diode = D 


Quart 
/Half 


Trans 

/Dart 


v CEO 

(V) 


V CEX 

(V) 


'Clsat) 
(A) 


v c 

sat 


at 
lb 


t ff (MS) 
typ. induct. 


Diode 
type 


SGS80DA020D 


Q 


D 


200 


300 


80 


2.0 


1 


1.9 


SGS60R40 


SGS40TA045 


Q 


T 


450 


850 


40 


2.0 


8 


2.2 


none 


SGS40TA045D 


Q 


T 


450 


850 


40 


2.0 


8 


2.2 


SGS35R120 


SGS50DA045D 


Q 


D 


450 


850 


50 


2.5 


2 


2.0 


SGS35R120 


SGS25DB070D 


H 


D 


700 


1000 


25 


3.0 


2.5 


2.4 


SGS35R120 


SGS25DB080D 


H 


D 


800 


1200 


25 


3.0 


2.5 


2.4 


SGS45R80 


SGS30DB040D 


H 


D 


400 


500 


30 


3.0 


2 


2.0 


SGS45R80 


SGS30DB045D 


H 


D 


450 


600 


30 


3.0 


2 


2.0 


SGS45R80 


SGS30DA060D 


Q 


D 


600 


1000 


30 


2.5 


1.5 


3.0 


SGS35R120 


SGS30DA070D 


Q 


D 


700 


1200 


30 


2.5 


1.5 


3.0 


SGS35R120 


SGS50DB040D 


H 


D 


400 


500 


50 


3.5 


5.0 


3.0 


SGS45R80 


SGS50DB045D 


H 


D 


450 


600 


50 


3.0 


5.0 


3.0 


SGS45R80 


SGS15DB070D 


H 


D 


700 


1000 


15 


3.0 


1.5 


2.5 


SGS35R120 


SGS15DB080D 


H 


D 


800 


1200 


15 


3.0 


1.5 


2.5 


SGS35R120 



291 



Turn-off 

— the recovery of a diode; 

— t rr definition; 

— t rr characterization; 

— Q r characterization; 



minority carriers (holes for the n-substrate diodes) 
that are present in the high resistivity side of the 
junction (the cathode in a n-substrate diode). 

The off-state occurs when the minority carriers 
disappear: 

— when they recombine with majority carriers 
(a function of their lifetime); 



The reverse recovery Of a diode ~ they are extracted by a reverse current. 



When the voltage across a conducting diode is 
reversed, it takes a certain time for the diode 
to recover its reverse state. During this recovery 
phase current flows in the diode as follows: 

— over a certain time, called reverse recovery 
time - t rr ; 

— with a negative current that reaches a peak 
maximum current - I R)V | ; 

— until the electric charge stored in the semi- 
conductor junction, Q r , is evacuated. 

The physical mechanism involved is related to the 



When a diode is used in fast switching circuits the 
removal of these carriers by a reverse current is 
of prime importance. After this instant no more 
minority carriers are created by the direct current. 
The lifetime of minority carriers in fast diodes is 
also minimised by design. 

Fig. 1 shows the relationship between voltage and 
current in a diode during the recovery phase. The 
elements of interest for its characterization are: 

— di/dt, the rate of decrease of the forward 
current; 

— Q r , the stored charge (shaded area of Fig. 1). 



Fig. 1- Voltage and current across diode during recovery phase 




Fig. 2 represents a typical fast recovery rectifier 
application. Inductor current flows (free wheels) 
through the diode when the transistor is off, 
(back e.m.f). When the transistor is on, the full 
supply voltage is applied to the inductor, so that 
the energy is transferred from the power supply 
to the load. 

For each cycle when the transistor is turned on. 



the diode recovers its reverse state. During the 
change the diode acts as a short circuit between 
the transistor and the supply. The longer it takes 
for the diode to recover, the higher the stress on 
the transistor (l cp is associated with a simultaneous 
high voltage condition) . 

This application is typical for fast recovery rec- 
tifiers. 



Fig. 2 - Voltage and current across transistor at turn-on 





V CE / 


lcp 




\ i 






H ' rr 


t 



292 



T rr definition 

Figures 3 shows two possible definitions for the 
recovery time, t A and tg. In practice t rr is defined 
as t B in the figure. 

Fig, 3 - t rr measurement methods 



In cases like that shown in Fig. 2, it is important 
to consider that only t A is representative of the 
duration of the power pulse that the recovery 
of the diode induces in the transistor. 



t«=N. 





*B 






V F \ 


f * . 














>RM 






"25% 


Vrm 












J 


■ 



T rr characterization 

Photographs 1 and 2 show how different test 
conditions (l F and di/dt) imply markedly different 
results for t rr , for the same diode. 

The blocking voltage V RM can be disregarded as 
its influence on t rr is not direct, di/dt is the sig- 
nificant factor and Vrm is of importance only to 
the extent where it modifies di/dt. 

Photographs 3 to 5 show the behaviour of the SGS 
fast recovery rectifier diodes in conditions re- 
presenting the real environment in which the 
devices are expected to work. For instance, t A for 
SGS45R80 at 40A is 150ns. In a circuit like the 
one in figure 4, with 40A current in the inductor, 
the power pulse that the transistor must sustain 
(l c peak x V CE ) will last for 150ns. 

The capacity that SGS transistors have to safely 
absorb this energy is guaranteed in their FBSOA 
diagram. 



Photo 1 - Recovery times vs. di/dt at 1A for 
SGS35R 120 



■■■■■■■■■I 
■■■■■■■■I 



Photo 2 ■ 



Recovery times vs. 
SGS35R 120 



di/dt at 40 A for 




l R = 1 A; A : di/dt = 100A/ms; 

B : di/dt = 50A/ms; C : di/dt = 25A/ms; 

V R = 30V; t = 20ns/div; y = 1A/div 




l F = 40A; A : di/dt 
B : di/dt = 100A/ms; 
t = 200ns/div; y = 1 



Photo 3 - t rr for SGS45R80 



= 250A/ms; 
V R = 30V; 
OA/div 




MHHMH1 
■IMMMM 

■mar - 




l F = 40A; di/dt = 100 M s; V R = 30V; 
t = 200ns/div; y = 20A/div 



293 



Photo 4 - t rr for SGS35R 120 



Photo 5 - t rr for SGS60R40 





l F = 25A; di/dt = 100A/ms; V R = 30V; 
t = 200ns/div; y = 10A/div 



l F = 80A; di/dt = 10A/ms; V r = 30V 
t = 200ns/div; y = 20A/div 



Fig. 4 - Typical stress on transistor at turn-on 





VCE / 


Icp 






/ 






- 


I50ns 


t 



Turn -on 

— the turn-on phase of a diode; 

— V F p and tpR definitions; 

— t FR characterization; 

— tpp characterization; 

— Q r characterization. 

The turn-on phase of a diode 

In the circuit shown in Fig. 5 a fast diode is nor- 
mally used, In general it is well understood that a 
fast diode is needed to avoid overstressing both 
the diode and the transistor during the diode 
recovery phase. 

However the diode could also cause the transistor 
to be overstressed during its turn-on phase. Both 
circuits a) and b), if the transistor and its driving 
stage are fast, cause a very high di/dt on the diode 
when the transistor switches off. 

In practice the forward voltage drop on the diode 



will exhibit an overshoot before settling to its 
steady state value. This phenomenon is a con- 
sequence of the delay time needed by the mi- 
nority carriers before flooding the epitaxial region 
(high resistivity). 

At first only the majority carriers are present, 
traversing the epitaxial layer, that exhibit its 
intrinsic resistivity. As soon as the minority carriers 
invade the epitaxial layer, its resistivity collapses 
(due to conductivity modulation) and the steady 
state is reached. Returning to Fig. 5, we can see 
that the stress on the transistor at its turn-on 
reaches an extreme point when: 

— the collector current is still fully present; 

— the collector voltage exhibits a transient peak 
up to V s (the so called 'clamping voltage') 
plus V F . 

Other parasitic elements in the circuit may increase 
the overvoltage due to the diode. 

Attention must be paid to the physical lay-out, 
and especially to the interconnections between 
the collector of the transistor and the diode. 



294 



Fig. 5 - Typical configurations for transistors switching 

♦ V 



J 



o* v s 



< 



< ± 



i ■ >-<TRSW> 



Vpp and tpR definition 

The turn-on phase of a diode in a practical situa- 
tion is shown in Fig. 6. 

V FP is defined as the peak transient voltage. 

For the same current, the turn-on overvoltage is 
higher for diodes that can withstand a higher 
reverse voltage. This can be seen in Fig. 7. 

This is mainly related to the thicker epitaxial 
layer needed to implement a higher reverse voltage 
rating. 

At the turn-on of a diode, a thicker epitaxial 
layer causes a higher resistance, before the con- 
ductivity modulation by the minority carriers 
takes place. 



Fig. 6 - Turn-on transient of the diode 



Fig. 7 - Direct overvoltage vs. di/dt 

v FP (V)r 



































































T c = 1?5*C 






SGS35R520 








■ f : If(av) 




> 


















I 


















SG^5R80 






1/ 


/\ 














/ 


' 










3- 


>6£>R 


-0 




^ 


^ 


' 

















di/tfflA^s) 



V (V) 
In IV) 







> 




If 






VFP1 










| 




4- 




-- 


-■ 






dl /df.C 


Ajjs 


























Vf 



































(/JS) 



Tfr Characterization 

In Fig. 8, the turn-on times, t fr , for the SGS 
fast recovery rectifiers SGS45R80, SGS35R120 
and SGS60R40 are shown as a function of di/dt. 

t fr is defined as the time from the instant Vp 
becomes positive till the time V FP decreases to 
+ 2V. 



Vpp Characterization 

Figs. 9 to 1 1 characterize Vpp in all possible 
di/dt conditions of practical use for the diodes 



295 



Fig. 8 - Turn-on time vs. di/dt 




Fig. 10 - Direct overvoltage vs. di/dt 

GU-10U 



FP IV) 






















to 










SGS35R120 


























30 






T C = 125-C 






s 








l F = 25A 


















































10 

































































'/dt <a//js; 



100 2C0 300 



di/dt (A/^js) 



Fig. 9 - Direct overvoltage vs. di/dt 

Vpp(V) 
rr 20 











I 
















SGS60R^0 






























Tc-125 


c 




















lF = 80A. 


















!p=lOA^ 












/ 


S' 




!F = 25A_ 










/ 


y 


















( 


s 


















h 



















100 



200 300 

di/d((A/ps) 




t = 0.lMs/div; V = 2V/div; I = 5A/div 




V = 5V/div; l F = 25A; di/dt = 200A/ms; 
t = 100ns/div 



under consideration. The values shown are typical. 
Maximum values are never more than 1.3 times 
the typical ones. 

They are valid for a case temperature up to 125°C; 
Vpp will be moderately lower at a lower tem- 
perature. 

Using an example it can be seen how V FP may, 
in some cases, be the origin of some unxpected 
inconvenience. 

In Fig. 12, case (a) refers to an application where 
Vpp is of no concern (di/dt is very low). 

In the case figure 12b, in contrast to figure 12a, 
di/dt may be high enough to create a significant 
Vpp overshoot. 

Figure 12c emphasized Vpp for the diode D 2 , at 
the moment when the switches Q.± and Q 3 are 
turned off. 

Immediately after turn-off when all the switches 
are off, the load current still flowing due to the 
inductive nature of the load, can only flow through 
D 2 and D3. Vp p across D 2 than acts as a negative 
bias on the collector (w.r.t. the emitter) of Q 2 . 



296 



Fig. 1 1 - Direct overvoltage vs. di/dt 



Fig. 12b -Bridge configuration for motor driving 



(.0 



20 







! 














SGS45R80 






\ 




! 








i . T C = 12 5*C 












! lF=<.0A 


























; i 














! ^ 














\y^\ 














/\ i 















100 200 300 

di/(jt(AAjs) 





















( 






4 



V = 5V/div; l F = 25A; di/dt = 200A/ms 
t = 100ns/div 



Fig. 12a - Final stage of power amplifier 



Fig. 12c - Voltage and current waveforms with 
reference to Fig. 12b 

V ' Q1 



Vi 



Q 2 



V D 2 



'CI 



ft 



t, 



Vi(t) 



^r 




If Q 2 is a darlington, this negative voltage may be 
enough to reverse bias (through the integrated 
resistances of the darlington) the final transistor 
and make it conduct a reverse current l x . 

The current l x may be a significant proportion of 
the current that is expected to flow only through 
D 2 , and it can store a significant charge Q r in the 
final darlington transistor. 

The final darlington transistor base collector 
junction acts as a slow recovery diode. 

As a result, when Q 2 is again turned on, it senses 
the behaviour of an 'equivalent D 2 ' with a much 
longer reverse recovery time. The peak current is 
higher than expected, creating reliability hazards or 
possibly the destruction of Q x . 

SGS produces safe operating area diagrams 
(FBSOA) which specify the maximum V c /I c 
boundary for each device in the range so the 



297 



designer can select the most suitable device Fig. 13c 
and ensure no repetitive overstress occurs. Q . 

Q r Characterization 

An electric charge Q r , is stored in the diode during » 

the direct conduction phase. 

The amount of charge that is evacuated during , 

the recovery phase is approximately: 

Q r = 1/2 l rm x l r 

Figures 13a, b and c plot Q r as a function of di/dt, « 

at room and at elevated case temperature (125°C), , 

and with the currents of practical use for SGS45R80, 
SGS35R120 and SGS60R40. 



Fig. 13a-b-c -Recovery charge vs. di/dt 



Q R/, 



(/jC) 













I 








1 








































































































































































































»F- 


OA 










, 




















IF = 25A 

! 






















— 


C -125 - C 


S\ III 














I 
I 

II 








' 






■'I 
If 

1 


_ 


5 


1 
A 






















































































/ 






i 






















/ 




/ 
































/ 


/ / 
































I 


/ / 


/ 






I 


























' 


// 


/ 






























P 












SGS< 


5R8 





















l- 

i 





















































! 












1 1 


























I ! ! 






j 














1! 






1 1 


H 






I i 


T C - 2S-C 

T c - 125" C 






1 




- '"' 


IF - 80A j 








^. 


1 








1 










x_. _^ '' ' 


































« 25A 








































| 








-4 ^ 1- 


























-r 


















i 


S* 


S 


kP 


1 




j 








! 1 ' 




/ 




i 












! 




A y< 






! 




i 








A(\ 










SGS60R40 






i 


— 


i 1 






j 











li/dtlA/pj) 



in : * t I B : * l e 

di/ di (A/^l 



F/ff. 13b 

°«/ImcI 































U 


-10*1 








































































































































T 


































| 






TC - 25' C 






























T c -12S- C 














• 


•* 


















I 


*F- 


SA 








1 


•* 


























' 


, 


. 


i 
























































































































; 


! / 
































J' / 








- 


























H/ 


















[ 














/ 






\ 












1 














j 






\ 
I 




SGS3 


SR1 































i 















dl/^IA/^sl 



CONCLUSION 

The devices described in this note can be classed 
in the high-speed range as far as turn-off is con- 
cerned, and in the medium-high range for turn-on. 

In addition it can be noted that the reverse re- 
covery of these devices is of the so called "soft" 
type, which makes them particularly suitable for 
applications where reduced radiated noise, ringing 
waveforms, etc. are of concern. 

While nowadays it is relatively easy to find in the 
market high voltage/high current transistors for 
fast switching applications, the same is not true for 
the diodes needed in the same applications. 

The fast recovery rectifier diodes SGS45R80, 
SGS35R120, and SGS60R40 represent part of a 
successful development that complement the 
SGS product range of power transistors in the high 
power area. 



298 



HANDLING AND MOUNTING ICs 
IN PLASTIC POWER PACKAGES 

Integrated circuits mounted in plastic power packages can be damaged, or reliability compro- 
mised, by inappropriate handling and mounting techniques. Avoiding these problems is 
simple if you follow the suggestions in this section. 



Advances in power package design have made it 
possible to replace metal packages with more econ- 
omical plastic packages in many high power appli- 
cations. Most of SGS' power driver circuits, for 
example, are mounted in the innovative MULTI- 
WATT® package, developed originally for high 
power audio amplifiers. Though the intrinsic re- 
liability of these packages is now excellent the use 
of inappropriate techniques or unsuitable tools 
during mechanical handling can affect the long 
term reliability of the device, or even damage it. 
With a few simple precautions, careful designers 
and production engineers can eliminate these risks, 
saving both time and money. 



BENDING AND CUTTING LEADS 

The first danger area is bending and cutting the 

Fig. 1 - Clamp the leads between the package and bend/cut point. 



leads. In these processes it is important to avoid 
straining the package and particularly the area 
where the leads enter the encapsulating resin. If the 
package/lead interface is strained the resistance to 
humidity and thermal stress are compromised, 
affecting reliability. 



There are five basic rules to bear in mind: 

• Clamp the leads firmly between the package 
and the bend/cut point (figure 1). 

• Bend the leads at least 3 mm from the package 
(figure 2a). 

• Never bend the leads more than 90° and never 
bend more than once (figure 2b). 

• Never bend the leads laterally (figure 2c). 

• Make sure that the bending/cutting tool does 
not damage the leads. 




Plastic 
Package 



Lead forming or cutting 
mechanism 



SpacecK W 
.oo33 Clamp mechanism 



Fig. 2 - Bend the leads at least 3 mm. from the package, never bend leads more than 90° and never 
attempt to splay the leads out. 

- — - 3.0miri 



o 




■ 


' 


"^- 



299 



INSERTION 

When mounting the IC on a printed circuit board 
the golden rule is, again, to avoid stress. In parti- 
cular: 

• Adhere to the specified pin spacing of the de- 
vice; don't try to bend the leads to fit non- 
standard hole spacing. 

• Leave a suitable space between the IC and the 
board. If necessary use a spacer, 

• Take care to avoid straining the device after 
soldering. If a heatsink is used and it is moun- 
ted on the PC board it should be attached to 
the IC before soldering. 

SOLDERING 

The greater danger during soldering is overheating. 
If an IC is exposed to high temperature for an ex- 
cessive period it may be damaged or reliability 
reduced. 

Recommended soldering conditions are 260°C 
for ten seconds or 350°C for three seconds. Figure 
3 shows the excess junction temperature of a 
PENTAWATT package for both methods. 

It is also important to use suitable fluxes for the 
soldering baths to avoid deterioration of the leads 
or package resin. Residual flux between the leads or 
in contact with the resin must be removed to gua- 
rantee long term reliability. The solvent used to 
remove excess flux should be chosen with care. 
In particular, trichloroethylene (CHCI : CCI2) — 
based solvents should be avoided because the 
residue can corrode the encapsulant resin. 

Fig. 3 - The excess junction temperature of a 
PENTAWATT package in the suggested soldering 
conditions. 











5 - 5363 


*C) 


350'C solder 


mg bath i 


— Exposed to air 




150 ■ 










100 - 
50 


Solder' - 


350'C [ ! 

















s 


- S3 6S 


T l 


Z60*C soldering bath 












(*C) 










Exposed 




150 - 














100 - 


/ S 












50 - 


/ i-260"C 


.. 1 

""T 


.5r 













HEATSINK MOUNTING 

To exploit the full capability of a power device a 
suitable heatsink must be used. The most impor- 
tant aspect from the point of view of reliability is 
that the heatsink is dimensioned to keep the junc- 
tion temperature as low as possible. From a mech- 
anical point of view, however, the heatsink must be 
designed so that it does not damage the IC. Care 
should also be taken in attaching the IC to the 
heatsink. 

The contact thermal resistance between the device 
and the heatsink can be improved by adding a thin 
layer of silicon grease with sufficient fluidity to 
ensure uniform distribution. Figure 4 shows how 
the thermal resistance of a MULTIWATT package 
is improved by silicone grease. 

An excessively thick layer or an excessively viscous 
silicon grease may have the opposite effect and 
could cause deformation of the tab. 



Fig. 4 ■ 



The thermal resistance of a MULTIWATT 
package is improved by silicon grease. 
Here thermal resistance is plotted against 
grease thickness. 



R th 


1 






CC/W) 












MULTIWATT 










PACKAGE 








' 1 




| 


j 




! / 










■*^s~ 




Without sill 


one gre 

1 


ase 




J^ 
















Ja^2 — 


1 


^C^ ' 


^^Jp-^" 








■^^ 1 


Silicone grease applied 





40 60 80 100 



SGS plastic power packages — MULTIWATT, 
PENTAWATT and VERSAWATT - are attached 
to the heatsink with a single screw. A spring clip 
may also be used as shown in figure 5. The screw 
should be properly tightened to ensure that the 
package makes good contact with the heatsink. It 
should not be too tight or the tab may be de- 
formed, breaking the die or separating the resin 
from the tab. 

The appropriate tightening torque can be found by 
plotting thermal resistance against torque as shown 
in figure 6. 

Suggested tightening torques for 3MA screws are 
8 Kg/cm for VERSAWATT, PENTAWATT and 
MULTIWATT packages. If different screws, or 
sping clips, are used the force exerted by the tab 
must be equivalent to the force produced with 
these recommended torques. 

Even if the screw is not overtightened the tab can 
be deformed, with disastrous results. If the surface 
of the heatsink is not sufficiently flat. The plan- 
arity of the contact surface between device and 



300 



Fig. 5 - MULTIWATT, PENTAWATTand VERSA- heatsink must be better than 50,um for PENTAWATT 
WATT packages are attached to the heat- and VERSAWATT packages and less than 40,um 
sink with a single screw or a spring clip, for MULTIWATT packages. 



Fig. 7 - The heatsink tab may be deformed if a 
washer or a wide-headed screw is not 
used. 



:7^ 




Fig. 6 - Contact thermal resistance depends on 
tightening torque. 





j MULTIWATT 










^it^t si co e g ease 


T" I 






Silicone grease applied 




! ! 1 ' 






- _ _ : 


J 




Similar problems may arise if the screwhead is too 
narrow compared to the hole in the heatsink 
(figure 7). 

The solution here is to use a washer to distribute 
the pressure over a wider area. An alternative is to 
use screws of the type shown in figure 8 which 
have a wide flat head. When self-tapping screws 
are used it is also important to provide an outlet 
for the material deformed as the thread is formed. 
Poor contact will result if this is not done. Another 
possible hazard arises when the hole in the heatsink 
is formed with a punch: a circular depression may 
be formed around the hole, leading to deformation 
of the tab. This may be cured by using a washer 
or by modifying the punch. 



Fig. 8 - The recommended screw type looks like 
this. 



rrf-n, 



6 Torque (Kg/< 



Serious reliability problems can be encountered if 
the heatsink and plrinted circuit board are not 
rigidly connected. Either the heatsink must be 
rigidly attached to the printed circuit board or 
both must be securely attached to the chassis. If 
this is not done the stresses and strains induced by 
vibration will be applied to the device and in parti- 
cular to the lead/resin interface. This problem is 
more likely to arise when large boards and large 
heatsinks are used or whenever the equipment is 
subjected to heavy vibrations. 



301 



DEVELOPMENTS IN SURFACE MOUNTING PACKAGES 
FOR POWER INTEGRATED CIRCUITS 



Thermal dissipation is recognized as a major problem in Surface Mount Technology. New 
packages are needed, having good thermal characteristics and meeting the SMT requirements: 
reduced size, automatic placement, compatibility with the SMT soldering systems. 

In this paper, thermal data and measurement methods for the most popular SO and PLCC 
packages are reviewed; some new solutions for surface mountable medium power (up to 2W) 
and high power (more than 2Wj devices are presented. 



INTRODUCTION 

A number of problems have been met in intro- 
ducing the high density, high reliability mass 
production of SM systems. This can explain the 
experimental work and the complex characteriza- 
tion activity of both ICs suppliers and users. 

As discussed elsewhere /1/, the four main areas of 
such activity are: standardization, quality, re- 
liability after soldering on PC boards and power 
dissipation. 

Fast progress has been made and more confidence 
in the SM technology has been achieved in the 
first three areas. For example, it was demonstrated 
that the most common conditions used in double 
wave soldering and vapour phase reflow soldering 
do not affect the final reliability of SO packaged 
devices (Fig. 1 ). 

On the contrary, referring to heat dissipation, 
progress is less fast, even if this point can strongly 
limit PERFORMANCE and COST of the system, 
thus losing the two main advantages of the SM 
technology, to a certain amount. 



needed, to cover the 



A development activity is 
following points : 

1) study of the relationship between thermal 
resistance of the package and board charac- 
teristics (density, lay-out, dissipated power). 
As it will be discussed later, this point cannot 
be ignored, even at dissipation levels (0.5W 
or less), typical of the "signal" packages like SO 
and PLCC packages; 

2) study of the thermal properties in pulsed 
conditions, in order to avoid redundancy and 
cost increase; 

3) development of new power packages with re- 
duced thermal resistance and heat transfer 
features. 

Moreover, a lack of standardized methodology 
exists when the thermal parameters have to be 
measured and compared. 

In the present paper the above mentioned points 
are considered. The characterization activity 
running in SGS is presented, together with ex- 
perimental data and details on development of 
new power packages. 



303 



Fig. 1 - SGS SO packages: reliability on FR4 board 





UNMOUNTED 


SOLDERED ON PCB 


% of rejects 

OPAMP family 

jan-june '86 


Vapour 

phase 

215°C/20s 


Doc 
wa 
225°C/8s 


ble 
ve 

250°C/8s 


SO-8, 14, 16 


SO-14 


SO-8 


SO-14 


SO-14 


Pressure pot 

98h 
196h 


0.05 
0.22 


0/32 


0/52 


0/52 


0/52 


Operating life test 
1000h 


0.66 




0/77 


0/77 


0/32 


THB 85/85 
T = 85°C 
RH = 85% 

1000h 
2000h 


0.5 


0/32 
0/32 




1/105 (*) 


0/32 
0/32 


THB 130/85 
T = 130°C 
RH= 85% 

200h 




0/60 




0/20 




Thermal cycles 
-65/+150 C 

500 cycles 


0.0 




0/77 


0/154 





(*) Parametric failure between 500 and 1000h 

(**) Acceleration factor to 85/85 can be assumed between 25 and 30 - Test is still running ■ 



EXPERIMENTAL TECHNIQUE FOR 
THE THERMAL CHARACTERIZA- 
TION IN DC AND PULSED CONDI- 
TIONS 

THERMAL EVALUATION TEST PATTERN 
P432 

The expecially designed test pattern P432 is used 
for thermal characterization (Fig. 2). 

It is formed by two power NPN transistors, able to 
dissipate 10W each. Their total area is about 1000 
sq. mils. The junction temperature Tj of a sensing 
diode, placed between the two transistors, is 
recorded through the measurement of the diode 
voltage V f when forward biased at a current of 
100/iA, The relationship between V f and Tj is 
linear, as shown by the calibration curve of Fig. 3. 



Fig. 2 - Thermal evaluation test Pattern P432 




S-9465 



304 



Fig. 3 - Calibration curve for P432 sensing diode 




The test pattern design ensures that the diode is 
positioned on the temperature plateau generated 
when the two transistors are biased in parallel; it 



is than possible to know the transistor Tj, through 
the junction temperature of the diode. 

The evaluation die can be cut in different sizes, 
in order to quantify the effect of the die area on 
the thermal resistance. 



MEASUREMENT TECHNIQUE 

The measurement technique is simple 111 and does 
not need to switch the power element from the 
dissipation condition to the sensing condition, 
thus offering a better accuracy if short pulses 
are considered. Indeed, the same resolution cannot 
be achieved with other test patterns, in which the 
sensing diode is missing (as single power transistors 
or diode, ICs substrate diode, etc.). 

The measurement circuit is shown in fig. 4. A DC 
power supply or a pulse generator biases the 
transistors in parallel; a fast voltmeter or a storage 
oscilloscope records the diode V f . Resolution 
better than 50ns is obtained with this circuit. 



Fig. 4 - Measurement circuit with P432 





D. C. 
SUPPLY 








D. C. 
SUPPLY 






f 




1 
















T 


FAST 
DVM 






~1 
1 


\v^> 


/ — 






SUPPLY 


7 | 






L 


STORAGE 
SCOPE 










H "~ 










1 f^ u 


1 


- 






1 

|P432 




PULSE 
■ GEN. 












5-9466 



UNMOUNTED (FLOATING) SAMPLES 

In order to simulate the thermal behaviour of the 
package in the worst condition (as in a high density, 
double sided card), samples are connected to 8 
thin wires, needed for biasing the two transistors 
and the sensing diode. Measurement is performed 
on such devices, suspended horizonthally in a 
one cubic foot plastic box, to prevent draft. 



SAMPLES SOLDERED ON TEST SUB- 
STRATES 

In order to characterize the thermal properties of 
parts mounted on a substrate, samples are reflow 
soldered on ceramic and epoxy glass substrates. 

For the evaluation of SO packages, the size of the 
plastic FR4 test board is fixed while the copper 
pattern lay-out can be changed. Seven different 



test boards are obtained from the basic configura- 
tion of Fig. 5, as summarized in Tab. 1 . 

Table 1 - CHARACTERISTICS OF THE TEST 
BOARDS FOR SO PACKAGE EVALUATION 



Type 


Trace area 
(x 1000 sq. mils) 


Heatsink 


SM PCB 1 SGS 


136 


yes 


1B 


136 


no 


1A 


21 


no 


1C 


50 


no 


1D 


71 


no 


1E 


93 


no 


1F 


102 


no 



substrate: FR4 

size: 00.9"xO.S"x0.056' , 



305 



Fig. 5 - Basic layout of thermal evaluation test board 




ajs 




S- 9«67 



Test board SM PCB1 SGS has a 0.2 sq. inch integral 
heatsink in the lower side obtained by a standard 
two layer PCB technology; in test board 1A the 



traces are reduced to the solder pads, only. 

For 68 leads PLCC package only one PCB lay-out 

has been considered at present. 



THERMAL RESISTANCE OF SO 
PACKAGES (STILL AIR) 

Thermal properties of these packages are influenced 
by following factors: 

1 ) thermal conductivity of the frame; 

2) thermal conductivity of the molding compound; 

3) frame design; 

4) device area; 

5) die pad area; 

6) device power dissipation; 

7) substrate type; 

8) substrate area; 

9) area of the connecting traces on the substrate. 

Due to the significant number of parameters, 
some of them have been mantained constant, as 
package design, which meets the standard Jedec 
outline, the test board size and the thermal pro- 
perties of the package materials, listed in Tab. 2: 



Table2- PACKAGE THERMAL CONDUC- 
TIVITIES 



The effect of the board is shown in Fig. 7: thermal 
resistance ranges now between 180 and 280° C/W, 
in the same conditions of die size and power dis- 
sipation. 

Fig. 8 is related to copper frame SO-14 package, 
with different substrates: thermal performance 
of the heatsinked SM PCB1 SGS plastic board is 
noticeable, as it only slightly differs from a ceramic 
substrate. 

For the same package, the relationship with the 
total area of the copper traces connected to the 
leads is shown in Fig. 9: actually, the traces behave 
as dissipating fins and this cannot be ignored when 
considering high density boards. 

At last, Fig. 10 reports the dependance on die 
area: the different behaviour of copper and Alloy 
42 can be explained taking into account that 
silicon thermal conductivity (1.3W/cmC) is higher 
than the alloy thermal conductivity by a factor 
of ten; silicon area is the dominating factor in 
this case. 

Fig. 6 - R th of "FLOATING" SO-8, 14, 16 (Alloy 
42 frame) 



Molding Compound 


2.67x10~ 3 W/cmC 


Frame Alloy 42 


0.105 W/cmC 


Frame Copper 


2.61 W/cmC 



THERMAL RESISTANCE OF S08, 14, 16 
PACKAGES 

Alloy 42 frame SO package have an intrinsic junc- 
tion to ambient thermal resistance ranging between 
250 and 430°C/W, depending on the power level: 
results for "floating" samples (die size: 4500sm) 
are summarized in Fig. 6. 



tf 




"T" 


'"T"" 


| 






I 








°^ 














' 




\^^ 






















f^c 


SO -8 












s 


























I 




! 












s 




! 


^~~~~j — -^T~^— • 


















j 










1 S0-I 


. 








i 










-| £0-1 








i 

t 








*,„ 


1 


: 



,10 8. IS B. 20 0.2S 8.38 B 
DISSIPATED POJEB 



as b.48 b.is e.se 



306 



Fig. 7 - Alloy 42 SO-8, 14, 16 R tn on board 



E 




-— r— , ^ 






V 


^ i | 


""j 


i s 


— i— - 


i "^ 


"~^ — -« so -a 


i I 


f 


^ 




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i 


! 








. 1 3 




^L "^^ 






SQ-14 


j 

q 


1 " 

£ s 


u 


nountUd on SM 


PC91 SG 


b~.d 




— ^ SD-16 - 




. . i 



J. 30 0.30 0.40 8.50 B.£0 3. 72 3.S£ 

DISSIPATED POUER ( Untt 1 



^/p. 70 - flf/j of on board SO-14 packages vs. 
die area 




- Pd 


tod on SH PCB1 

a. 6 U 


B SGS board 




1 
1 


f 


I | 






I 


_r 




] 




■ 


1 COPPER (W-E 


j 



DIE AREA ( x 1D00 sq. 



THERMAL RESISTANCE OF 68 LEADS 
PLCC PACKAGE 

Data concerning DC and pulsed conditions are 
_. „ , „,. „ . . . .... obtained for this package 131, which has Jedec 

Fig 8 - R th of copper SO-14 with different out | ine and copper crame. 
substrates 

Fig. 11 - R th of "FLOATING" 68 lead PLCC 




3.20 0.30 0.40 8.50 8.60 0.70 El. 83 3.50 1 .t 
DISS1PP.TD PDLEB ( Ltatt ) 

















I \ ■ ■ ■ ; \ | ; ; ■ 




! \ ' ' ' ' ■ ' ! ■}■!■! | j ' 


Bvxr* 


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1 


i ■ i ■ : ! . : ■ ! i ! j i ' i 














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rri-HNq— -^zt^: tr ^\--^Tr^^^--\]:r 












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II j ■ j i ! ■ ! ' ~h— -^ : 


r-H-?— "4 


4^—j-i-i-H I— j— . | ; | -,-4-ffi-j-U..-.. . j , 






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t-^— t-4— 


1 . 1 ■ 1 11-4 -J-, i 1— 1J.+ i i - 1 : . . 

-n+w-t-i-J-i— f-i-H—^ , ,-» , ■ , ,1 iTi : . i ; . .-1 



0.20 0.40 0.69 e.ga 1.00 ■; . 20 l 
OISSIPP.TID P0LER 1 Ltott : 



Fig. 12 - R tn of 68 lead PLCC mounted on board 
Fig. 9 - R tn of copper SO-14 vs. board trace area (Die pad area A = 300x300 sq. mils; B = 425x 

425 sq. mils I 



I 

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-"-""I 


I 


1 ' ' | ' ^ 


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) 


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40 
TRACE 


EB 8 
OREO ( 


I 100B 




<E 'G3 


130 


^ee 






DISSIPRTED- POLER ( Untt 



307 



DC CONDITION 

Fig. 11 and 12 show the thermal resistance for 
"floating" are assembled parts, respectively. Curves 
A and B refer to the minimum (300x300 sq. mils 
and maximum (425x425 sq. mils die pad size, 
in both cases. 

The package has a not negligeable thermal ca- 
pacitance, due to the thermal mass associated to 
the copper frame and to the molded body. From 
Fig. 13 a value of about 1-1.5J/s can be assumed 
for this parameter. 



Fig. 15 - Peak transient R tn of 68 lead PLCC (AC) 



Fig. 13 - Temperature rise of 68 lead PLCC (DC) 




PULSED CONDITIONS 

Very interesting values are found for single pulses: 
power up to 10W can be delivered for about 1 -2s 
(Fig. 14). 

When the pulse is repeated with a certain duty 
cycle DC, junction temperature is oscillating about 
a mean value Tj = T amb + R th P d DC. 

If the upper temperature values of the oscillation 
are considered, a peak transient thermal resistance 
can be defined, whose value is a function of pulse 
width and duty cycle. From the curves of Fig. 15 
the thermal properties are obtained for different 
pulse conditions. 



Fig. 14 
pulse) 



Transient R tn of 68 lead PLCC (Single 




— 






--= 


= 7 










■— 




It 


f- 




# J f 


n. 
















- 






[■■ 




[[ r 




























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^H-fj(ILSE" REPETITION PF 

jjiiL. .'niiL 


mui/ 


■ i 



TIME OR PULSE UIDTH C 



TIHE OR PULSE UIDTH ( ms ) 

DEVELOPMENT OF SMD POWER PACK- 
AGE 

The previous section has quantified the thermal 
performance limits for presently available SM 
standard packages. 

Interesting values have been measured for 68 lead 
PLCC package: high pin count PLCCs are suitable 
to dissipate up 1W in DC condition. No solution 
is standardized at present for higher power. 

Two main development areas for power SM pack- 
ages can be identified. The first is the medium 
power range (2W or less), where pin count up to 
44 will be needed; the second is high power (more 
than 2W), where up to about 20 leads will be 
required /4/. 

MEDIUM POWER SM PACKAGES 

They can be derived very conveniently from 
existing SO and PLCC, by modifying the lead 
frame connecting a number of pins to the die pad, 
for heat removal. 

A thermal conductive path is obtained from the 
junction to an external heatsink, having a defined 
thermal resistance R th (j_ sub ). Cost effective 
heatsink is easily formed with a suitable copper 
area on the PCB, which the "grounded" pins are 
soldered to. Powers of 1 -2W can be dissipated in 
this way. 

This approach is particularly attractive because the 
external dimensions of the package are identical 
to the existing signal packages, allowing the use of 
standard tools for testing, shipping and assembly. 

Example of modified SO20 package is given in 
Fig. 16. 

More interesting for future products is the ap- 
plication of modified leadframe techniques to 
PLCC. A PLCC 44 can be redesigned to obtain a 
A + B lead version (A + B = 44), which uses A 
signal pins and B leads connected to the die pad 
to reduce the junction to substrate R th . In Fig. 1 7, 
the frame of a new 33 + 1 1 power PLCC is shown, 
giving a junction to substrate thermal resistance 
better than 12°C/W. Such package is now entering 
in production is SGS. A typical application of this 
package for 2W dissipation is given in Fig. 18. 



308 



Fig. 16 - Medium power SO-20 frame 



Fig. 17 - Medium power 33+1 1 lead PLCC frame 





Mh j-amb 
^thj-sub 



Max die size 



nhj-sub 
/lax. die size 



S " 9 4 69 

55°C/W 

12°C/W 

195x195 mils 



Fig. 18 - Typical application (2W) of PLCC + 11 with external heatsink integrated are the printed board 




Additionally, the frame can be modified to in- 
corporate dissipating 'fins' within the plastic body 
for a further reduction of the junction-to-ambient 
thermal resistance. In PLCC these fins are obtained 
easily at the corner of the package by sacrificing 
signal pins. 

Due to availability of a high number of leads mils 
in PLCC, the reduction of useful pins is not a 
problem and junction to-ambient thermal re- 
sistances can be obtained in the range of 30- 



40°C/W, for the dissipation of 1 .5-2W without 
any need of external heatsinks. 

HIGH POWER SM PACKAGES 

For IC's dissipating more than about 2W a dif- 
ferent approach is needed. 

One obvious solution is simply to form the leads 
of standard power packages so that they can be 



309 



Fig. 19 - High power module with external heatsink 




surface mounted. SGS produces three terminal 
voltage regulators in a SM version of SOT-82 
package arranged in this way. 

In fact, development in this area is concentrated 
on a new generation of packages designed from the 
outset for surface mounting. 

Recent trends in premolding techniques give ad- 
ditional possibility in defining the structure of the 
package. 

A family of packages in now being studied with 
a junction-to-case thermal resistance of less than 
5°C/W from 3 to 17 pins and a lead spacing of 
50 mils. These packages will have a standard SO- 
width body and gull wing leads, allowing the use 
of SO packages handling equipments. 

The low thermal resistance is obtained by a copper 
heatspreader on the lower surface of the package, 
upon which the die is attached. When the package 



is soldered into place, the spreader is in contact 
with the substrate. Clearly the amount of power 
that can be dissipated depends on the conductivity 
of the substrate (Fig. 19). 

In view of this trend there is now considerable 
interest in high conductivity substrates and the 
various alternatives, such as plastic boards bonded 
to aluminium or copper sheets. Plated through 
holes in the PCB under the chip's heat spreader 
may be used to improve the thermal resistance 
between the device and the metal (Fig. 20). 

Another development area is the inclusion of a 
copper spreader on the under-side of pre-molded 
PLCC; the same substrate/heatsink possibilities 
apply to this package family too. This solution 
is obtained by moulding a plastic body having a 
cavity, into which the die is inserted later. It is 
more indicated for large area, high accuracy de- 
vices, for which some effects of the post epoxy 
molding process are very critical. 



Fig. 20 - High power module with external heatsink and plated through holes 



copper 



^lEca. 




REFERENCE: 



I'M C. Cognetti "Status of Active Surface Mounted 
Devices for Signal and Power Application" 
EIPC Conference Proc. p. 1 .1 .1 (Lugano, 1986) 

/2/T. Hopkins, R. Tiziani, C. Cognetti "Improved 
Thermal Impedance Measurements by means 
of a simple Integrated Structure"Jemitherm 
Conf. Proc. Phoenix (USA) - Dicembre 86. 



through-hojgIL 



/3/SGS Technical Report MMD-86101 

/4/ C. Cognetti, R. Tiziani "Status of Power 
Packages and Evolution Towards Power SMD" 
Electronica - Munich - November 86. 



310 



DATASHEETS 



311 



^^^^^^^^^® 



AM26LS31 



PRELIMINARY DATA 



QUAD HIGH SPEED DIFFERENTIAL LINE DRIVER 



• OUTPUT SKEW -2.0ns TYPICAL 

• INPUT TO OUTPUT DELAY -12ns 

• OPERATION FROM SINGLE +5V SUPPLY 

• OUTPUTS WONT LOAD LINE WHEN 
V cc = 

• OUTPUT SHORT-CIRCUIT PROTECTION 

• COMPLEMENTARY OUTPUTS 

• MEETS THE REQUIREMENTS OF EIA 
STANDARD RS-422 

• HIGH OUTPUT DRIVE CAPABILITY FOR 
100ft TERMINATED TRANSMISSION 
LINES 

The AM26LS31 is a quad differential line driver, 
designed for digital data transmission over bal- 
anced lines. The AM26LS31 meets all the re- 
quirements of EIA standard RS-422 and federal 
standard 1020. It is designed to provide unipolar 
differential drive to twisted-pair or parallel- 
wire transmission lines. 



The circuit provides an enable and disable func- 
tion common to all four drivers. The AM26LS31 
features 3-state outputs and logical OR-ed comp- 
lementary enable inputs. The inputs are all LS 
compatible and are all one unit load. 




W^ 



DIP-16 Plastic (0.25) 
and Ceramic 



SO-16J 



ABSOLUTE MAXIMUM RATINGS 



V s 


Supply voltage 


7 


V 


V] 


Input voltage 


7 


V 


Vo 


Output voltage 


5.5 


V 


Tstg 


Storage temperature range 


-65 to 150 


°C 



Fig. 1 -Typical Application 



ENABLE O 



data a 

1/4 AM26LS31 



TWO WIRE BALANCED SYSTEM RSA22 




/4AM26LS32 




313 



12/86 



AM26LS31 



CONNECTION DIAGRAM 

(Top view) 



INPUT ! 
GND 



] 1 


W 


16 1 


' 2 




15 ] 


3 




H ] 


4 




13 ] 


5 




12 ] 


6 




11 ] 


7 




10 1 


8 




9 [ 



+ 5V 
INPUT D 



ORDERING INFORMATION 



Package 
Type 


Temperature 
Range 


Order 
Number 


DIP-16 Ceramic 


-55 to 125°C 


AM26LS31MJ 


Oto 70° C 


AM26LS31CJ 


DIP-16 Plastic 


Oto 70° C 


AM26LS31CN 


SO-16J 


Oto 70° C 


AM26LS31D1 



LOGIC DIAGRAM 



ENABLE ENABLE INPUT 






INPUT 
C 



INPUT 
B 



INPUT 
A 



rv rvf rvf rv 



OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT 
D+ D- C* C- B+ B- A+ A- 



314 



AM26LS31 



THERMAL DATA 



DIP-16 
Ceramic 



DIP-16 
Plastic 



SO-16 



Thermal resistance junction-ambient 



150 C/W 



200 C/W 



165 C/W 



ELECTRICAL CHARACTERISTICS (The following conditions apply unless otherwise specified: 



'amb 


-55°Cto 125°C, V cc =5V 


± 10%; T amb =0to+70 


°C, V cc = 5V 


± 5%) 








Parameter 


Test Conditions 


Min. 


Typ. 

(Note!) 


Max. 


Unit 


VOH 


Output HIGH Voltage 


V cc = Min., 


l OH = -20mA 




2.5 


3.2 




V 


Vol 


Output LOW Voltage 


V C c = Min., 


l OL = 20mA 






0.32 


0.5 


V 


Vih 


Input HIGH Voltage 


v cc~ Min - 


2.0 






V 


V| L 


Input LOW Voltage 


V cc = Max. 






0.8 


V 


l|L 


Input LOW Current 


V cc = Max., 


V ]N = 0.4V 






-0.20 


-0.36 


mA 


l|H 


Input HIGH Current 


V cc = Max., 


V, N = 2.7V 






0.5 


20 


MA 


l| Input Reverse Current 


V cc = Max., 


V, N = 7.0V 






0.001 


0.1 


mA 


lo 


Off-State (High Impedance) 
Output Current 


Vcc = Max - 




V = 2.5V 




0.5 


20 


MA 


V o =0.5V 




0.5 


-20 


V| 


Input Clamp Voltage 


V cc = Min., 


l !N = 18mA 






-0.8 


-1.5 


V 


Isc 


Output Short Circuit Current 


V cc = Max. 


-30 


-60 


-150 


mA 


'cc 


Power Supply Current 


v cc = Max., 


all outputs disabled 




60 


80 


mA 


tpLH 


Input to Output 


V CC =5.0V, 


T amb = 25 ° c - 


Load = Note 2 




12 


20 


ns 


tpHL 


Input to Output 


V cc = 50V, 


T amb = 25 ° c . 


Load = Note 2 




12 


20 


ns 


SKEW 


Output to Output 


V cc = 5.0V, 


Tamb= 25°C, 


Load = Note 2 




2.0 


6.0 


ns 


tl_Z 


Enable to Output 


V cc = 5.0V, 


T amb =25°C, 


C L = 10pF 




23 


35 


ns 


'HZ 


Enable to Output 


V CC =5.0V, 


T amb = 25 ° c - 


C L = 10pF 




17 


30 


ns 


»ZL 


Enable to Output 


V CC = 5.0V, 


T amB = 25 ° C ' 


Load = Note 2 




35 


45 


ns 


tZH 


Enable to Output 


V CC =5.0V, 


T amb =25°C, 


Load = Note 2 




30 


40 


ns 



Notes : 1 . 

2. 



A typical values are V cc = 5.0V, T amb = 25°C 

C L = 30pF, V| N = 1.3V to V OUT = 1.3V, V PULSE = 0V to +3.0V, See Bek 



315 



AM26LS31 



Fig. 2 - Guaranteed V OH 
and V OL (T amb = -55 °C to 
+ 125°C) 































I 
















Wcc-"» 














5V 














i.5V 






































































V 0L «45V S V CC <5.5V 


" 








I I I 



Fig. 3 - V OUT vs. V cc 



*cc 




I 




1 | 


























•~ 


.„, 










-■ i— 






55 "C 








it'" 


^ 


' — - 25"C 



























































i 







12 I rtl n nH (m*) 



Fig. 4 - AC load test circuit 
for three-state outputs 



Fig. 5 - Propagation delay 
(Notes 1 and 3) 



TEST POINT 



C L INCLUDES 
PROBE AND JIG 
CAPACITANCE 



X 



11) 75J1 



"1 



-f=^ 



\ 



r 



Fig. 6 - Enable and disable times 
(Notes 2 and 3) 



OUTPUT 
NORMALLY 



ENABLE DISABLE 



■ ZL l LZ - 



0.5 V 

Mr 

/ v 0L 



OUTPUT 

NORMALLY S 1 0PEN/l.3V 



"Xp: 



Notes: 1. Diagram shown for Enable LOW. 

2. S1 and S2 of Load Circuit are closed except where shown. 

3. Pulse Generator for AH Pulses: Rate < 1.0MHz; Z = 50«;t r =S 15ns; t f < B.Ons. 



316 



^^^^^^^® 



AM26LS32 
AM26LS33 



PRELIMINARY DATA 



RS422 AND RS423 
LINE RECEIVERS 



QUAD DIFFERENTIAL 



• THE AM26LS32 MEETS ALL THE REQUI- 
REMENTS OF RS-422 AND RS-423 

• 6K MINIMUM INPUT IMPEDANCE 

• 30mV INPUT HYSTERESIS 

• OPERATION FROM SINGLE +5V SUPPLY 

• FAIL SAFE INPUT-OUTPUT RELATION- 
SHIP. OUTPUT ALWAYS HIGH WHEN 
INPUTS ARE OPEN 

• THREE-STATE DRIVE, WITH CHOICE OF 
COMPLEMENTARY OUTPUT ENABLES, 
FOR RECEIVING DIRECTLY ONTO A 
DATA BUS 

• PROPAGATION DELAY 17ns TYPICAL 

The AM26LS32 is quad line receiver designed to 
meet the requirements of RS-422 and RS-423, 
and Federal Standards 1020 and 1030 for bal- 
anced and unbalanced digital data transmission. 

The AM26LS32 features an input sensitivity 
of 200mV over the input voltage range of ± 7V. 



The AM26LS33 features an input sensitivity of 
500mV over the input voltage range of ± 15V. 

The AM26LS33 provide an enable and disable 
function common to all four receivers. Both 
parts feature 3-state outputs with 8mA sink 
capability and incorporate a fail safe input- 
output relationship which keeps the outputs 
high when the inputs are open. 



^ 




DIP-16 Plastic (0.25) 
and Ceramic 



SO-16J 



ABSOLUTE MAXIMUM RATINGS 



v s 


Supply voltage 


7 


V 


CMR 


Common mode range 


±25 


V 


Vi 


Differential input voltage 


±25 


V 


V E 


Enable voltage 


7 


V 


Ics 


Output sink current 


50 


mA 


Tstg 


Storage temperature range 


-65 to 150 


°C 



Fig. 1 - Typical Applications 
Two wire balanced system, RS-422 

ENABLE O- 



DATA 
H4 AM26LS31 



W4AM26LS32 




Single wire with common ground imbalanced system, RS-423 

DATA O 



1/4AM26LS32 



£~' 



DATA 
OUTPUT 



_0R0UND RETURN COMMON 
TO SEVERAISIGNALWIRES 



317 



12/86 



AM26LS32 
AM26LS33 



CONNECTION DIAGRAM 

(Top view) 





O 




INPUTS A 


1 
2 


16 

15 


INPUTS B 


OUTPUT* 


3 


U 


ll 


ENABLE 


' 


13 


J OUTPUT 8 


OUTPUT C 


5 


12 


] ENABLE 




6 


11 


OUTPUT D 


INPUTS C 


7 


10 


INPUTS D 


GND | 


8 


9 


'1 



ORDERING INFORMATION 



Package 
Type 


Temperature 
Range 


AM26LS32 AM26LS33 


Order Number 


Order Number 


Hermetic DIP 
Hermetic DIP 
Molded DIP 
SO-16J 


-55 to 125°C 
to 70° C 
Oto 70° C 
Oto 70° C 


AM26LS32MJ 
AM26LS32CJ 
AM26LS32CN 
AM26LS32D1 


AM26LS33MJ 
AM26LS33CJ 
AM26LS33CN 
AM26LS33D1 



LOGIC DIAGRAM 



ENABLE ENABLE IN D* IN D- INC+IN C- IN B+ IN B- IN A + IN A - 




6 6 

OUTPUT C OUTPUT B OUTPUT A 



THERMAL DATA 



DIP-16 
Ceramic 



DIP-16 
Plastic 



SO-16 



R thj-amb Thermal resistance junction-ambient 



150 C/W 200 C/W 





165 C/W 



318 



AM26LS32 
AM26LS33 



ELECTRICAL CHARACTERISTICS (The following conditions apply unless otherwise specified: T amb =-55°C 
to 125°C, V cc = 5V ± 10%; T amb = to 70°C, V cc = 5V ± 5%) 



Parameter 


Test Conditions 


Min. 


Typ. (1) 


Max. 


Unit 


V TH Differential Input Voltage 


V OUT" V OL or V OH 


AM26LS32, -7V < V CM « +7V 


-0.2 


±0.06 


+0.2 


V 


AM26LS33, -15V < V CM « +15V 


-0.5 


±0.12 


+ 0.5 


R|N Input Resistance 


-15V < V CM < +15V (One input AC ground) 


5.0 


9.8 




KSJ 


l| N Input Current (Under Testl 


V m - +15V, Other Input -15V < V (N < +15 V 






2.3 


mA 


l|N Input Current (Under Test) 


V| N = -15V, Other input -15V <; V m < +15V 






-2.S 


mA 


V OH Output HIGH Voltage 


Vcc = Min - fiV IN " +1-0V 


COM'L 


2.7 


3.4 




V 




= -440uA 


MIL 


2.5 


3.4 




^ENABLE 0.6V, Iqh 


V OL Output LOW Voltage 


V cc = Min., AV m = -1.0V 


'oL = 4 -°mA 






0.4 


V 


V ENABLE = °- 8v 


'oL = 8 - 0m A 






0.45 


V| L Enable LOW Voltage 








0.8 


V 


V| H Enable HIGH Voltage 




2.0 






V 


V| Enable Clamp Voltage 


V C c =" Mi"-. I|N = -18mA 






-1.5 


V 


Off-State (High Impedance) 
Iq Output Current 


V C c " Max - 


V = 2.4V 






20 


mA 


V o = 0.4V 






-20 


l|l_ Enable LOW Current 


V| N = 0.4V 




-0.2 


-0.36 


mA 


l|H Enable HIGH Current 


V (N = 2.7V 




0.5 


20 


,uA 


l| Enable Input High Current 


V| N = 5.5V 




1 


100 


MA 


l sc Output Short Circuit Curr. 


V o = 0V, V cc = Max., AV| N = +1.0V 


-15 


-50 


-85 


mA 


I cc Power Supply Current 


V cc = Max., All V| N = GND, Output Disabled 




52 


70 


mA 


v hyst Input Hysteresis 


Tamb = 25°C, V cc = 5.0V, V CM = 0V 




30 




mV 


tpLH Input to Output 


T amt) = 25°C r V cc = 5.0V, C L = 15pF, see test cond. below 




17 


25 


ns 


tpHL Input to Output 


T amb = 25° C, V cc = 5.0V, C L = 15pF, see test cond. below 




17 


25 


ns 


t|_z Enable to Output 


T amb = 25°C, V cc = 5.0V, C L = 5pF, see test cond. below 




20 


30 


ns 


t H z Enable to Output 


Tamb = 25°C, V cc = 5.0V, C(_ = 5pF. see test cond, below 




15 


22 


ns 


tzL Enabie to Output . 


T amb = 25 ° c . V CC = 5 - 0v - C L = 15 P F . see tes « c ° n d. below 




15 


22 


ns 


tzH Enable to Output 


T amb = 25°C, V cc = 5.0V, C L = 15pF, see test cond. below 




15 


22 


ns 



(1) All typical values are V cc = 5.0V, T al 



319 



AM26LS32 
AM26LS33 



Fig. 2 - Load test circuit for three-state outputs 



Fig. 3 - Propagation delay 
(notes 2 and 3) 





TEST POINT 

9 




1 280A 


v cc 

J 








v nu 


FROM OUTPUT rv _ 






/ \ 


i 1.3V 




/ 


UNDER TEST °~ 




= [ 


| R 1 


! 


[ 
[ 
; 


ALL DIODES 
lN916or 1N3064 


/ 




CONCLUDES 
PROBE AND JIG 
CAPACITANCE 


OPPOSITE 1 

PHASE \ 

INPUT 

TRANSITION 


~—\ *PLH 




'OL 

— 'phi 






















S 2 


1 


S-9180 







Fig. 4 - Enable and disable time (notes 2 and 3) 

ENABLE 



ENABLE 
INPUT 



OUTPUT 

NORMALLY 

LOW 



OUTPUT 

NORMALLY 

HIGH 



■jF^k 



'Zl 'LZ- 

-45V 



S.OPEN jf 1.3V 



3V 

1.3V 

OV 



U.bV 



~ 1.5V 

'OL 



^ 



'OH 
— 1.5V 



Notes: 1. Diagram shown for Enable LOW 

2. SI and S2 of Load Circuit are closed except where shown. 

3. Pulse Generator for All Pulses: Rate < 1.0MHz; Z = 50S~2; t r < 15ns; t f < 6.0ns 



320 



^^^^^^^^'S 



AM6012 
AM6012A 



PRELIMINARY DATA 



12-BIT HIGH SPEED MULTIPLYING D/A CONVERTERS 



The AM6012 is an industry standard monolithic 12-bit 
digital-to analog converter. Complementary current 
output and high speed multiplying capability make 
the AM6012 useful in a wide range of applications 
such as video displays, process control circuitry and 
fast A/D converters. The 6012 is the first D/A to 
achieve 12-bit differential linearity without the use of 
thin film resistors or active trimming. The 6012's uni- 
que circuit design insures monotonicity without the 
precision trimming associated with most other 12-bit 
DAC architectures. 

The AM6012 is packaged in a 20-pin plastic DIP and 
is SO-20L for surface mounting. Although tested and 
specified at ± 15V, the AM6012 works well over a 
wide range of power supply voltages. Performance 
is essentially independent of supply voltage over the 
range of +5 volts, -12 volts to ±18 volts. The 
AM6012 series guarantees full 12-bit monotonicity for 
all grades and differential nonlinearity as high as 
0.012% (13 bits) for the A grades and 0.025% (12 
bits) for the standard grades over the entire tempe- 
rature range. 

Guaranteed monotonicity and low cost make the 
AM6012 an ideal choice for high volume applications 
requiring fine local resolution. Typical applications in- 
clude printer graphics and video displays. These ap- 
plications need a minimum of 12 bits of resolution, 
although conformance to an ideal straight line from 
zero to full scale is less important. 



• ALL GRADES 12-BIT MONOTONIC OVER 
TEMPERATURE 

• DIFFERENTAL NONLINEARITY TO ±0.012% 
(13 BITS) MAX OVER TEMPERATURE 

(A GRADES) 

• 250ns TYPICAL SETTLING TIME 

• FULL SCALE CURRENT 4mA 

• HIGH SPEED MULTIPLYING CAPABILITY 

• TTL/CMOS/ECL/HTL COMPATIBLE 

• HIGH OUTPUT COMPLIANCE: -5VTO +10V 

• COMPLEMENTARY CURRENT OUTPUTS 

• LOW POWER CONSUMPTION: 230mW 




BLOCK DIAGRAM 



LSB 
B4 B5 B6 B7 BB B9 B10 Bll B12 




321 



11/86 



AM6012 
AM6012A 



ABSOLUTE MAXIMUM RATINGS 



Operating Temperature Range 


to 70 


°C 


Storage Temperature 


-65 to + 125 


°C 


Power Supply Voltage 


±18 


V 


Logic Inputs 


-5 to +18 


V 


Voltage at Current Outputs Pins 


-8 to +12 


V 


Reference Inputs 


+ Vs to -Vee ±18V 
max Differential 


V 


Reference Input Current 


1.25 


mA 



CONNECTION DIAGRAM AND ORDERING INFORMATION 



Type 


Differential 
linearity (%) 


Temperature 
Range (°CI 


Package 


AM6012PC 


0.025 


to 70 


DIP. 20 


AM6012APC 


0.012 


AM6012 D 


0.025 


to 70 


SO.20L 


AM6012 AD 


0.012 



(TOP VIEW) 



MSB-B1 


c 


i 


B2 


r 


2 


B3 


d 


3 


B4 


q 


4 


B5 


p 


5 


B6 


r J 


6 


B7 


p 


7 


B8 


c 


8 


B9 


p 


9 


B1C 


c 


10 



20 Z +Vs 

19 Zl lo 

IB Zl lo 

17 Zl -VEE 

16 p C0MP. 

15 P VREF (-) 

14 P VREF (+) 

13 p GND/VLC 

12 p B12-LSB 

11 P Bll 



THERMAL DATA 



"Uhj-amb 



Thermal resistance junction-ambient 



100 °C/W 



322 



AM6012 
AM6012A 



ELECTRICAL CHARACTERISTICS 

These specifications apply for Vs = + 1 5V, Vee = 
ge unless otherwise specified 



■ 15V, Iref = 1 .OmA, over the operating temperature ran- 



Param. 






Test Conditions 


AM6012A 


AM6012 


Units 


Description 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 




Resolution 




12 


12 


12 


12 


12 


12 


Bits 




Monotonicity 




12 


12 


12 


12 


12 


12 


Bits 


D.N.L. 


Differential 
Nonlinearity 


Deviation from ideal step size 


- 


- 


±.012 


- 


- 


±.025 


%FS 


13 


- 


- 


12 


- 


- 


Bits 


N.L. 


Nonlinearity 


Deviation from ideal straight line 


- 


- 


^.05 


- 


- 


±0.05 


%FS 


Ifs 


Full Scale Current 


V REF = 10.000V 
Rl4 = Rl5 = 10.000k!) 
T A = 25°C 


3.967 


3.999 


4.031 


3.935 


3.999 


4.063 


mA 


tci fs 


Full Scale Temp. Co. 




- 


±5 


±20 


- 


±10 


±40 


ppm°C 


- 


±.0005 


±.002 




±.001 


±.004 


%FS°C 


Voc 


Output Voltage 
Compliance 


D.N.L. Specification guaranteed 
over compliance range 
Rout>10 megohme typ. 


-5 


- 


+ 10 


-5 


- 


+ 10 


V 


! FSS 


Full Scale 
Symmetry 


'fs-'fs 


- 


±0.2 


±1.0 


- 


±0.4 


±2.0 


/iA 


'zs 


Zero Scale Current 




- 


- 


0.10 


- 


- 


0.10 


liA 


is 


Setting Time 


To ±1/2 LSB, all bits ON or 
OFF, T A = 25°C 


- 


250 


500 


- 


250 


500 


nSec 


tpLH 
tpHL 


Propagation 
Delay - all bits 


50% to 50% 


- 


25 


50 


- 


25 


50 


nSec 


C OUT 


Output Capacitance 




- 


20 


- 


- 


20 


- 


pF 


V|L 


Logic 
Input 
Levels 


Logic "0" 




- 


- 


0.8 


- 


- 


0.8 


V 


V|H 


Logic "1" 




2.0 


- 


- 


2.0 


- 


- 


!|N 


Logic Input Current 


V IN= -5 to -18V 


- 


- 


40 


- 


- 


40 


/iA 


Vis 


Logic Input Swing 


V EE = -15V 


-5 


- 


+ 18 


-5 


- 


+ 18 


V 


!ref 


Reference Current 
Range 




0.2 


1.0 


1.1 


0.2 


1.0 


1.1 


mA 


lis 


Reference Bias 
Current 







-0.5 


-2.0 





-0.5 


-2.0 


liA 



323 



AM6012 
AM6012A 



ELECTRICAL CHARACTERISTICS (Continued) 



Param. 


Description 


Test Conditions 


AM6012A 


AM6012 


Units 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


di/dt 


Reference Input 
Slew Rate 


R 14(eql = 800fi 
CC = OpF 


4.0 


8.0 


- 


4.0 


8.0 


- 


mA.'Vs 


PSSI FS + 


Power Supply 
Sensitivity 


V s = (^13.5Vto ^ 16.5V) 
V EE =-15V 


- 


± .00005 


±.001 


- 


* 0.0005 


±.001 


%FS/% 


PSSI FS 


V EE =- 13.5V to -16.5V 
V S =-15V 


- 


± .00025 


±.001 


- 


± .00025 


±.001 


v s 


Power Supply 
Range 


v ut = ov 


4,5 


- 


18 


4.5 


- 


18 


V 


Vee 


-18 


- 


-10.8 


-18 


- 


-10.8 


I-"- 


Power Supply 
Current 


V s =+5V, V EE =-15V 


- 


5.7 


8.5 


- 


5.7 


8.5 


mA 


I- 


- 


-13.7 


-18.0 




-13.7 


-18.0 


l + 


V S =^15V, V EE = -15V 




5.7 


8.5 


- 


5.7 


8.5 


- 


-13.7 


-18.0 


- 


-13.7 


-18.0 


I- 


P D 


Power 
Dissipation 


V s = +5V, V EE = -15V 


- 


234 


312 


- 


234 


312 


mW 


V s = J- 15V, V EE = -15V 


- 


291 


397 


291 397 



Fig. 1 - Relative Accuracy Error 



Fig. 2 - Example of Nonmonotonic Behavior 



FULL SCALE 




OUTPUT 
CURRENT 



DIGITAL INPUT CODE 




DIFFERENTIAL LINEARITY ERRORS SEVERE 
ENOUGH TO CAUSE NONHONOTONICY 



DIGITAL INPUT CODE 



A60i3-10: : D1S 



A6012-10: : LIS 



324 



APPLICATION INFORMATION 



AM6012 
AM6012A 



FUNCTIONAL DESCRIPTION 

The segmented design of the AM6012, shown in the 
block diagram, insures that there are no significant 
differential nonlinearities in the transfer characteri- 
stic. The eight major carries of the most significant 
bits are not subject to the gross differential nonlinea- 
rities that can occasionally occur in an R-2R type 
DAC. This advantage is due to the fundamentally dif- 
ferent way that the current is handled in an AM6012. 
In a conventional R-2R type DAC, when the input 
code is increemented past a major carry, a current 
representing the new code is substituted for the sum 
of all the less significant bit currents that were pre- 
viously on. To avoid any nonlinearities, the two to- 
tal currents must be extremely well matched. In the 
case of the MSB major carry in a 12-bit DAC, the 
match must be better than one part in 2048 to main- 
tain monotonicity. However, in the AM6012, a new 
current is never substituted for the sum of several 
smaller ones, but redirected through alternate chan- 
nels and incremented one step at a time. 
For example, consider the MSB carry in an AM6012. 
In the initial state of 01 1 1 1 1 1 1 1 1 1 1 as shown in the 
block diagram, the switches in the segment genera- 
tor are set in such a way that currents Irj, l| and I2 
are steered directly into the noninverting output 
lOUT- In addition, a portion of I3 is directed through 
the 9-bit DAC that is controlled by the 9 least signi- 
ficant bits into Iout. With the 9LSBs set to "I", all 
of the I3 current is directed to IrjlIT except for the 
1/512 that goes to ground through the right-most 
transistor in the 9-bit DAC. After the input word is 
changed to 100000000000, the segment decoder 
switch for I3 will be all the way to the right, the 
switch for I4 will be in the middle, and all the swit- 
ches in the 9-bit DAC will be to the left. Iout will 
be composed of In, M, I2 and I3. None of U will be 
directed into Iout until a higher code is reached. In 
other words, I3 is now steered directly to Iout in- 
stead of being divided by a factor of 51 1 /512 in the 
9-bit DAC. Since no major current substitution oc- 
curs, there is less chance of a large nonlinearity at 
this transition than in a comparable R-2R DAC. 

RELATIVE ACCURACY VS. DIFFERENTIAL NON 
LINEARITY 

SGS defines relative accuracy as the maximum de- 
viation of the actual, adjusted DAC output from the 
ideal analog output (a straight line drawn between 
the lowest code output voltage and the highest co- 
de output voltage) for any bit combination. Relative 



accuracy is often referred to as nonlinearity. The DAC 
transfer function shown in Figure 1 has a bow that 
results in a maximum relative accuracy error of 3LSB. 
This must be distinguished from a differential linea- 
rity error. Differential nonlinearity is the measure of 
the variation in analog value, normalized to full sca- 
le, associated with 'a ILSB change in digital input 
code. 

For example, for a 4mA full scale output, a change 
of ILSB in digital input code should result in a 0.98/tA 
change in the analog output current 
(ILSB = 4mA x 1/4096 = 0.98/*A). If in actual use, 
however, a ILSB change in the input code results 
ina change of only 0.24fiA (1/4LSB) in output cur- 
rent, the differential linearity error would be 0.74/iA 
or 3/4LSB. 

The AM6012 has very good differential linearity in 
spite of the porr relative accuracy. Conversely, the 
DAC of Figure 1 has very good relative accuracy 
but poor differential linearity. The anomaly in the 
middle of the transfer function is the result of a po- 
sitive differential linearity error followed by a ne- 
gative differential linearity error greater than 1 LSB. 
A negative output step for an increase in digital in- 
put code is referred to as nonmonotonic behavior. 
In general, if a DAC has a differential linearity er- 
ror specification greater than 1 LSB, it may be non- 
monotonic at one or more of the major carries. In 
most case the worst differential linearity error will 
occur at the MSB transition point. 
As noted in the functional description, the 6012's 
unique design minimizes differential linearity errors 
at the transition points of the 3MSBs. This results 
in a tight specification on maximum differential non- 
linearity over temperature. Differential linearity is 
verified on all AM6012s with 100% final testing. 
In many converter applications, uniform step size 
(or minimum differential linearity error) is more im- 
portant than conformance to an ideal straight line. 
Twelve-bit onverters are usually needed for high 
resolution rather than high linearity as evidenced 
by the fact that few transducers are more linear 
than 0.1%. This is also true in video graphics, whe- 
re the human eye has difficulty discerning nonli- 
nearity of less than 5%. The AM6012 is especially 
well suited for these applications since it has in- 
herently low differential linearity error. 



325 



AM6012 
AM6012A 



APPLICATION INFORMATION (Continued) 



ANALOG OUTPUT CURRENTS 

Both true and complemented output sink currents 
are provided where lrj + lo = lFR- Current appears at 
the "true" output when a "1" is applied to each lo- 
gic input. As the binary count increases, the sink cur- 
rent at pin 18 increases proportionally, in the fashion 
of a "positive logic" D/A converter. When a "0" is 
applied to any input bit, that current is turned off at 
pin 18 and turned on at pin 19. A decreasing logic 
count increase In as in a negative or inverter logic 
D/A converter. Both outputs may be used simulta- 
neously. If one of the outputs is not required it must 
still be connected to ground or to a point capable 
of sourcing Ifr; do not leave an unused output pin 
one. 

Both outputs have an extremely wide voltage com- 
pliance enabling fast direct current-to-voltage con- 
version through a resistor tied to ground or other 
voltage source. Positive compliance is 25V above V- 
and is independent of the positive supply. Negative 
compliance is + 10V above V- . 
The dual outputs enable double the usual peak-to- 
peak load swing when driving loads in quasi- 
differential fashion. This feature is especially useful 
in cable driving, CRT deflection and in other balan- 
ced applications such as driving center-tapped coils 
and transformers. 

POWER SUPPLIES 

The AM6012 operates over a wide range of power 
supply voltages from a total supply of 20V to 36V. 
When operating with V - supplies of - 1 0V or less, 
Iref s 1 mA is recommended. Low reference cur- 
rent operation decreases power consumption and 
increases negative compliance, reference ampli- 
fier negative common mode range, negative logic 
input range, and negative logic threshold range; 
consult the various figures fro guidance. For exam- 
ple, operation at -9V with Iref = 1mA is not re- 
commended because negative output compliance 
would be reduced to near zero. Operation from lo- 
wer supplies is possible, however at least 8V total 
must be applied to insure turn-on of the internal 
bias network. 

Symmetrical supplies are not required, as the 
AM6012 is quite insensitive to variations in supply 
voltage. Battery operation is feasible as no ground 
connection is required; however, an artificial ground 
may be used to insure logic swings, etc. remain 
between acceptable limits. 



TEMPERATURE PERFORMANCE 

The nonlinearity and mononicity specifications of the 
AM6012 are guaranteed to apply over the entire ra- 
ted operating temperature range. Full scale output 
current drift is flight, typically ± 1 0ppm/°C with ze- 
ro scale output current and drift essentially negli- 
gible compared to 1/2 LSB. 
The temperature coefficient of the reference resi- 
stor R14 should match and track that of the out- 
put resistor for minimum overall full scale drift. 

SETTLING TIME 

The AM6012 is capable of extremely fast settling ti- 
mes, typically 250ns at Iref = 1 .0mA. Judicious cir- 
cuit design and careful board layout must be 
employed to obtain full performance potential during 
testing and application. The logic switch design ena- 
bles propagation delays of only 25ns for each of the 
12 bits. Settling time to within 1 12 LSB of the LSB 
is therefore 25ns, with each progressively larger bit 
taking successively longer. The MSB settles in 250ns, 
thus determining the overall settling time of 250ns. 
Settling to 10-bit accuracy requires about 90 to 
130ms. The output capacitance of the AM6012 in- 
cluding the package is approximately 20pF; therefo- 
re, the output RC time constant dominates settling 
time if R|_ > 500fl. 

Settling time and propagation delay are relatively 
insensitive to logic input amplitude and rise and fall 
times, due to the high gain of the logic switches. 
Settling time also remains essentially constant for 
Iref values down to 0.5mA, with gradual increa- 
ses for lower Iref values lies in the ability to at- 
tain a given output level with lower load resistors, 
thus reducing the output RC time constant. 
Measurement of settling time requires the ability 
to accurately resolve ±2/xA, therefore a 2.5kO load 
is needed to provide adequate drive for most oscil- 
loscopes. At Iref values of less than 0.5mA, ex- 
cessive RC damping of the output is difficult to 
prevent while maintaining adequate sensitivity. Ho- 
wever, the major carry from 011111111111 to 
100000000000 provides an accurate indicator of 
settling time. This code change does not require 
the normal 6.2 time constants to settle to within 
±0.1% of the final value, and thus settling times 
may be observed at lower values of Iref- 
AM6012 switching transients or "glitches" are very 
low and may be further reduced by small capaciti- 
ve loads at the output at a minor sacrifice in set- 
tling time. 



326 



APPLICATION INFORMATION (Continued) 



AM6012 
AM6012A 



Fastest operation can be octained by using short 
leads, minimizing output capacitance and load resi- 
stor values, and by adequate bypassing at the sup- 
ply, reference, and Vlc terminals. Supplies do not 
require large electrolytic bypass capacitors as the sup- 
ply current drain is independent of input logic sta- 
tes; 0. VF capacitors at the supply pins provide full 
transient protection. 

REFERENCE AMPLIFIER SETUP 

The AM6012 is a multiplying D/A converter in which 
the output current is the product of a digital number 
and the input reference current. The reference cur- 
rent may be fixed or may vary from nearly zero to 
+ 1.0mA. The full range output current is a linear 
function of the reference current and is given by: 



|RF = 



4095 
4096 



x4x(Iref) = 3.999 Ir ef , 



where Iref = 1 14 

In positive reference applications, an external posi- 
tive reference voltage forces current through R14 into 
the Vref( + ) terminal (pin 14) of the reference am- 
plifier. Alternatively, a negative reference may be ap- 
plied to Vrefi - ) at pin 15. Reference current flows 
from ground through R14 into Vref( + ) as in the 
positive reference case. This negative reference 
connection has the advantage of a very high im- 
pedance presented at pin 15. The voltage at pin 
1 4 is equal to and tracks the voltage at pin 1 5 due 
to the high gain of the internal reference amplifier. 
R1 5 (nominally equal to R14) is used to cancel bias 
current errors. (Figure 3). 
Bipolar references may be accommodated by off- 
setting Vref or pin 15. The negative common- 
mode range of the reference amplifier is given by: 
Vcm- =V- plus (Iref x3kQ) plus 1.8V. The po- 
sitive common-mode range is V+ less 1.23V. 
When a DC reference is used, a reference bypass 
capacitor is recommended. A 5.0V TTL logic sup- 
ply is not recommended as a reference. If a regu- 
lated power supply is used as a reference, R14 
should be split into two resistors with the junction 
bypassed to ground with a 0.1/iF capacitor. 
For most applications the tight relationship between 
Iref and Ips will eliminate the need for trimming 
Iref- If required, full scale trimming may be ac- 
complished by adjusting the value of R14, or by 
using a potentiometer for R14. 



MULTIPLYING OPERATION 

The AM6012 provides excellent multiplying perfor- 
mance with an extremely linear relationship between 
Ifs and Iref over a range of 1mA to VA. Monoto- 
nic operation is maintained over a typical range of 
Iref from 100^A to 1.0mA. 

REFERENCE AMPLIFIER COMPENSATION FOR 
MULTIPLYING APPLICATIONS 

AC reference applications will require the reference 
amplifier to be compensated using a capacitor from 
pin 16 to V - . The value of this capacitor depends 
on the impedance presented to pin 14. For R1 4 va- 
lues of 1 .0, 2.5 and 5 OkQ; minimum values of Cc 
are 5, 12 and 25 pF. Larger values of R14 require 
proportionately increased values of Cc for proper 
phase margin (See Figure 4 and 5). 
For fastest response to a pulse, low values of R1 4 
enabling small Cc values should be used. If pin 14 
is driven be a high impedance such as a transistor 
current source, none of the above values will suf- 
fice and the amplifier must be heavily compensa- 
ted which will decrease overall compensated which 
will decrease overall bandwidth and slew rate. For 
R14= IkQ and Cc = 5pF, the reference amplifier 
slews at 4mA/ms enabling a transition from 
Iref = to Iref= 1mA in 250ns. 
Operation with pulse inputs to the reference am- 
plifier may be accommodated by an alternate com- 
pensation scheme. This technique provides lowest 
full scale transition times. An internal clamp allows 
quick recovery of the reference amplifier from a cu- 
toff (Iref = 0) condition. Full scale transition (0 to 
1 mA) occurs in 62.5ns when the equivalent impe- 
dance at pin 14 is 800Q and Cc = 0. This yields a 
reference slew rate of 8mA/^s which is relatively 
independent of Rin and Vin values. 



327 



AM6012 
AM6012A 



APPLICATION INFORMATION (Continued) 



LOGIC INPUTS 

The AM6012 design incorporates a unique logic in- 
put circuit which enables direct interface to all po- 
pular logic families and provides maximum noise 
immunity. This feature is made possible by the large 
input swing capability, 40/iA logic input current, and 
completely adjustable logic inputs may swing bet- 
ween -5 and + 10V. This enables direct interfa- 
ce with + 1 5V CMOS logic, even when the AM601 2 
is powered from a + 5V supply. Minimum input lo- 
gic swing and minimum logic threshold may be ad- 



justed over a wide range by placing an appropria- 
te voltage at the logic threshold control pin (pin 1 3, 
V|_c)- For TTL interface, simply ground pin 13. 
When interfacing ECL, an Iref £ 1mA is recom- 
mended. For interfacing other logic families, see 
block titled "Interfacing With Various Logic Fami- 
lies". For general setup of the logic control circuit, 
it should be noted that pin 13 will sink 1.1mA typi- 
cal, external circuitry should be designed to accom- 
modate this current (Figure 6). 



Fig. 3 - Reference amplifier biasing 




$B 



ice n. - 1 ^ i°-u. 

T ji f i i 



22 JJF TANT. 
(NOTE 5) 



V- V+ 



A601S-B: : LIB 



Reference Configuration 


R-14 


R 15 


R IN 


c c 


!ref 


Positive Reference 


Vr + 


ov 


N/C 


.OVF 


VR + /R14 


Negative Reference 


OV 


Vr- 


N/C 


,0VF 


-VR-/R.14 


Lo Impedance Bipolar 
Reference 


Vr + 


OV 


VlN 


(Note 1) 


Vr + /Ri 4 ) + (V|n/R|N) 
(Note 2) 


Hi Impedance Bipolar 
Reference 


Vr + 


VlN 


N/C 


(Note 1) 


(Vr + -Vin)/Ri4 
(Note 3) 


Pulsed Reference (Note 4) 


Vr + 


OV 


VlN 


No Cap 


(V R -r/Ri4) + (ViN/RlN) 



Notes: 

1. The compensation capacitor a function of the impedance seen at the + Vref input and must be at least 5pFx R 14(eq j 
in kfi. For R-|4< 80QQ no capacitor is necessary. 

2. For negative values of V|pvj, VrW'R-|4 must be greater than ~V|^ (V1ax/R[^ so that the amplifier is not turned off. 

3. For positive values of V|^, Vr^ must be greater than V|n Max so the amplifier is not turned off. 

4. For pulsed operation, Vr 4 provides a DC offset and may be set to zero in some cases. The impedance at pin 14 should 
be 800S2 or less. 

5. For optimum settling time, decouple V - with 20U and bypass with 22>F tantulum capacitor. 

6. Reference current and reference resistor - there is a 1 to 4 schale factor between the reference current (Irer) an d the 
full scale output current (l F g>. If V REF = +10V and l FS =4mA, the value of the R 14 is: 



4x10 Volt 

R 14 = = lOkfi 

4mA 



Ri4 = Ri 



328 



AM6012 
AM6012A 



Fig. 4 - Minimum size compensation capacitor 
(l FS = 4mA, l REF =1.0mA) 



Rl4(EQ)IK!>) 


C C (pF) 




10 


50 




5 


25 




2 
1 


10 
5 




5 








Note: A 0.01 /^F capacitor is recommended for fixed reference operation. 



Fig. 5 - Reference Amplifier Frequency response 





I I I 




SMALL SIGNAL I 

LARGE SIGNAL [ 




















-^ 


^ 










\ 


\ 
















\ 




R14=2K 

Cc=10pF 










\\ 




I 





3 


-3 
-6 

0.01 0.1 



1 10 

(MHz) 



Fig. 6 - Interfacing Circuits 



A6012-11: : OI 
Fig. 7 - Accomodating Bipolar Reference 




TO PIN 13 




RREF n IREF 



:RE= > PEAK NEGATIVE SWING OF Iin 



ECL 




TO PIN 13 



AM6012 
15' ' 19 



HIGH INPUT 
IMPEDANCE 

VREF {+) MUS T BE ABOVE PEAK POSITIVE SWING OF VIN 



329 



AM6012 
AM6012A 



Fig. 8 - AM6012 Logic Inputs 




R14 



HOFF 



10 KOhm 



VBEF (+) N *" 

AM6012 IO > 

VHEF (-1 TcX— 

bi2 y + 



1 . OmA OPTIONAL 

(SEE CODE TABLE! 

VREF 

2.0mA 




LSB 



1 I 



ABOia-7: : LIB 









Output 


MSB 




















LSB 


lo 


lo 




Code Format 


Connec. 


Scale 


B1 


B2 


B3 


B4 


B5 


B6 


B7 


B8 


B9 


B10 B11 


B12 






"out 




Straight bynary 


a-c 


Positive full scale 


1 


1 


1 


1 


1 


1 


1 


1 


1 


f 


1 


1 


3,999 


.000 


9.9978 




one polarity 


b-g 


Positive full scale-LSB 


1 


1 


1 


1 


1 


1 


t 


1 


1 


1 




u 


3 998 


.001 


9.9951 




with true input 


R 1 = R2 = 2.5K 


Zero scale 






































.000 


3.999 


.0000 




code, true zero 




































Unipolar 


output 




































Complementary 


a-g 


Positive lull scale 






































000 


3.999 


9.9976 




binary one 


b-c 


Positive full scale-LSB 





































001 


3 998 


9.9951 




polarity with 


R1 = R2 = 2.5K 


Zero scale 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




3.999 


000 


.0000 




complementary 






































input code, true 






































zero output 






































Straight offset 


a-c 


Positive full scale 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




3 999 


.000 


9.9976 




binary: offset 


b-d 


Positive full scale-LSB 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




3.998 




001 


9.9927 




half scale, sym- 


1-0 


( + | Zero scale 


1 


































2.000 


1 


999 


.0024 




metrical about 


R1=R3 = 2.5K 


(-) Zero scale 





1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




1.999 


2 


000 


-.0024 




zero, no true 


R2 = 1 25K 


Negative lull scale-LSB 





































.001 


3 


998 


-9.9927 


Symmetrical 
Offset 


zero output. 




Negative tull scale 


























(J 










.000 


3 


999 


-9.9976 


1 's complement 


a-c 


Positive full scale 





1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




3.999 




000 


9.9976 




offset half scale 


b-d 


Positive lull scale-LSB 





1 


1 


1 


1 


1 


1 


1 


1 


1 


1 





3.998 




001 


9.9927 




symmetrical 


f-g 


( + ) Zero scale 






































2.000 


1 


999 


.0024 




about zero, no 


R1 = R3 = 2.5K 


(-) Zero scale 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




1.999 


2 000 


-.0024 




true zero output 


R2-1.25K 


Negative full scale-LSB 


1 


































001 


3 998 


-9.9927 




MSB comple- 




Negative full scale 


1 














u 





u 


I) 





u 


u 


000 


3 999 


-9.9976 




mented (need 






































inverter at B1| 






































Offset binary 


e-a-c 


Positive full scale 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




3.999 


.000 


9.9951 




offset half 


b-g 


Positive full scale-LSB 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 





3 998 




001 


9.9902 




scale, true zero 


R1 = R2 = 5K 


+ LSB 


1 


































2.001 


1 


998 


0049 




output. 




Zero Scale 
-LSB 


1 






1 




1 




1 




1 




1 







1 



1 



1 




1 





2 
1 


000 
999 


1 
2 


999 
000 


.000 
-.0049 








Negative full scale + LSB 







































001 


3 


998 


-9.9951 


Offset with 






Negative full scale 








































000 


3 


999 


-10.000 












































2's complement 


e-a-c 


Positive tull scale 





1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




3 


999 




00b 


9.9951 




offset half scale 


0-g 


Positive full scale-LSB 





1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




3 


998 




001 


9.9902 




true zero output 


R1 = R2 = 5K 


+ 1 LSB 





































2 


001 


1 


998 


.0049 




MSB comple- 




Zero scale 




















u 





It 










2 


000 


1 


999 


000 




mented (need 




-1 LSB 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 




1 


999 


2 


000 


-0.049 




inverter at B1) 




Negative full scale-t- LSB 


1 




































001 


3 998 


-9.9951 








Negative lull scale 


1 





































000 


3.999 


-10.000 



ADDITIONAL CODE MODIFICATIONS 

1. Any of the offset binary codes may be complemented by reversing the output terminal pair. 



330 



AM6012 
AM6012A 



Fig. 9 - Basic Negative Reference Operation 

=)REF 
VHEF (-) O 1 ■ 



Fig. 10 - Recommended Full-scale Adjustment Circuit 



14- 



VREF 



AM60 12 



F 15 



15- 



4 . 5K 



A M 6 1 2 



10K <- 



19 



Fig. 11 - CRT Display Driver 



+ 120V DC 



60V COMMON 
MODE LEVEL 



"X" INPUT 



it 



CRT 




10 



AM60 1 2 



^T_K 



-15V 



"Y" INPUT 



>*2^ 



Io 



Io 



Fig. 12 - 12-BIT High-Speed A/D Converter 



-i5v < AM60 1 2 



Io 



A6012-5: : LI 



n r 



SERIAL D*T» OUT 



E S CC DO 

2504 SAR 

Oil 



CP 



+ 10V 
REF 



1 




5 OOOK I MSB 



lO.OOOKOhl 



_ ANALOG IN 

VHEF (O-lOV) 



AM6012 



m 



hi— n- 

KJnF luF 1UF 

HI- HUH 



V (-) V (+) 



A6012-3: : LIB 



331 



AM6012 
AM6012A 



Fig. 13 - Interface with 8-bit Microprocessor Bus 



BUS 





J 


. 










MSB 

AM 
6012 

LSB 




OE 
LS373 








Q 




D 




H 










cL 


















U 




















L cl 
























D3A (5SA 

D2A Q2A 

D1A Q1A 
DOA QOA 

1/2LS100 




D3B 03B 
- DEB Q2B 

DIB Q1B 
DOB QOB 

1/2LS100 




L 1 




























EA 

























A6012-4: : LIB 



332 



^^^^^^® 



DAC0808 
DAC0807 
DAC0806 



PRELIMINARY DATA 



8-BIT D/A CONVERTERS 



• RELATIVE ACCURACY: ±0.19% ERROR MAXI- 
MUM (DAC0808) 

• FULL SCALE CURRENT MATCH: ±1 LSB TYP 

• 7 AND 6-BIT ACCURACY AVAILABLEIDAC0807, 
DAC0806) 

• FAST SETTING TIME: 150 ns TYP 

• NONINVERTING DIGITAL INPUTS ARE TTL 
AND CMOS COMPATIBLE 

• HIGH SPEED MULTIPLYING INPUT SLEW RA- 
TE: 8 mA/^s 

• POWER SUPPLY VOLTAGE RANGE: ±4.5Vto 
±18V 

• LOW POWER CONSUMPTION: 33 mW @±5V 



The DAC0808 series is an 8-bit monolithic digital-to- 
analog converter (DAC) featuring a full scale output 
current settling time of 150 ns while dissipating only 
33 mW with ±5V supplies. No reference current 
(Iref) trimming is required for most applications sin- 
ce the full scale output current is typically ± 1 LSB 
of 255 Iref/256. Relative accuracies of better than 

BLOCK DIAGRAM 



±0.19% assure 8-bit monotonicity and linearity while 
zero level output current of less than 4 /xA provides 
8-bit zero accuracy for Iref£2 mA. The power sup- 
ply currents of the DAC0808 series are independent 
of bit codes, and exhibits essentially constant devi- 
ce characteristics over the entire supply voltage 
range. 

The DAC0808 will interface directly with popular TTL, 
or CMOS logic levels, and is a direct replacement for 
the MC1508/MC1408. 




*y^ 



DIP-16 Plastic (0.25) 
and Ceramic 



SO-16 



+ VS Al A2 A3 A4 A5 A6 A7 A8 

Q OOOOQQQQ 



+ o- 

VREF 
-O- 



13 



BIAS 



5 6 7 8 9 10 11 12 



oTirrrrrin 




-o 

vo 



COMPO -VEEO 



DAC0808- 



333 



11/86 



DAC0808 
DAC0807 
DAC0806 



ABSOLUTE MAXIMUM RATINGS 



Supply Voltage 

Vs 

Vee 
Digital Input Voltage V5--V12 
Reference Current, I14 
Reference Amplifier Inputs, V14, V15 

Operating Temperature Range 
DAC0808L 
DAC0808LC/D 

Storage Temperature Range 



+ 18 


V 


-18 


V 


-10 V to +18 


V 


5 


mA 


VCC 


Vee 


55°C<Ta< +125 


°C 


0<Ta< +75 


°C 


-65°C to +150 


°C 



CONNECTION DIAGRAM AND ORDERING INFORMATION 




Accuracy 


Temperature 
range 


Plastic 
DIP-16 


Ceramic 
DIP16 


SO-16 


8 bit 


to 75°C 


DAC0808LCN 


DAC0808LCJ 


DAC0808D 


7 bit 


to 75°C 


DAC0807LCN 


DAC0807LCJ 


DAC0807D 


6 bit 


to 75° C 


DAC0806LCN 


DAC0806LCJ 


DAC0806D 


8 bit 


-55 to 125°C 


- 


DAC0808U 


- 



DAC0B0B-13 



THERMAL DATA 



Ceramic 
DIP-16 



SO-16 



Plastic 
DIP16 



Rthj-amb Thermal resistance junction-ambient max 



150°C/W 



120°C/W 



100°C/W 



334 



DAC0808 
DAC0807 
DAC0806 



ELECTRICAL CHARACTERISTICS 

(Vs = 5V, Vee= -15V, Vref/R14 = 2 mA, Ta = Tmin to Tmax and all digital inputs at high logic level 
unless otherwise noted.) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


E r 


Relative Accuracy (Error Relative 

to Full Scale Iq) 
DAC0808L 

DAC0807LC/D1 (Note 1) 
DAC0806LC/D1 (Note 1) 


(Figure 10) 






±0.19 
±0.39 
±0.78 


% 

% 
% 
% 




Settling Time to Within 1/2 LSB 


T A = 25°C (Note 2) 




150 




ns 




(Includes tp LE |) 


(Figure 1 1) 










fpLH 
tPHL 


Propagation Delay Time 


T A = 25°C (Figure 11) 




30 


100 


ns 


TCI 


Output Full Scale Current Drift 






±20 




ppm/°C 


MSB 


Digital Input Logic Levels 


(Figure 9) 










VlH 


High Level, Logic "1" 




2 






v D c 


VlL 


Low Level, Logic "0" 








0.8 


Vdc 


MSB 


Digital Input Current 


(Figure 9) 












High Level 


V| H = 5V 







0.040 


mA 




Low Level 


V| L = 0.8V 




-0.003 


-0.8 


mA 


lis 


Reference Input Bias Current 
Output Current Range 


(Figure 3) 
(Figure 91 




-1 


-3 


/iA 






V EE = -5V 





2.0 


2.1 


mA 






V EE = -15V, T A = 25°C 





2.0 


4.2 


mA 


'o 


Output Current 


V REF = 2.000V. 
R14 = 1000SJ 














(Figure 9) 


1.9 


1.99 


2.1 


mA 




Output Current, All Bits Low 


(Figure 9) 







4 


p.A 




Output Voltage Compliance 


E r s0.19%, T A = 25°C 












V EE = - 5V 








-0.55, + 0.4 


V 




V EE Below -10V 








-5.0 ,+0.4 


V 


SRI RE p Reference Current Siew Rate 


(Figure 14) 


4 


8 




mA/fis 




Output Current Power Supply 


-5V<V EE s- 16.5V 




0.05 


2.7 


/iA/V 




Sensitivity 












Power 


Supply Current (All Bits Low) 


(Figure 9) 










is 

Iee 








2.3 
-4.3 


22 

-13 


mA 


Power 


Supply Voltage Range 


T A = 25°C (Figure 9) 










V.S 






4.5 


5.0 


5.5 




Vee 






-4.5 


-15 


-16.5 






Power Dissipation 














All Bits Low 


V S = 5V.V EE = -5V 




33 


170 


mW 






V S = 5V.V EE = -15V 




106 


305 


mW 




All Bits High 


V S = 15V.V EE = -5V 
V S = 15V.V EE = -15V 




90 
160 




mW 
mW 



Note 1: All current switches are tested to guarantee at least 50% of rated current. 

Note 2: All bits switched. 

Note 3: Range control is not required. 



335 



DAC0808 
DAC0807 
DAC0806 



Fig. 1 - Supply Current vs 
Temperature 



Ice 
(mA) 



Fig. 2 - Supply Current vs Supply Fig. 3 - Supply Current vs Supply 

Voltage (V EE ) Voltage (V s ) 



T f— r— rn — r~T— i — r^ 


] ALL BITS HIGH OR LOW [• 






i 


T -,-„ 












1 1 








































^E 

, J 






































— 
















































is 




















_L 










1 l 



-50 50 1 T . (• C) 



1 1 1 1 1 1 1 1 1 


-| ALL BITS HIGH OR LOW f- 
















Mill 

I EE (I 14 = 2 m A ) 


















Ice di4 -1mA) 

1 — 1— -1 — 1 — 1 — 


















I EE (I 14 =0 .2mA) 












































is 

1 





























\^i—LznjziLJZJZ3z^nz' 


(mA) 


-j ALL BITS HIGH OH LOW j- 
















1 1 


















" r~M 








' 1 






























1 


"1 


1 


























1 1 










































1 IT! 








n 






1 s 


1 x 14' 

1 1 J 


1 







12 V FF (V) 



1 2 Ve (V) 



Fig. 4 - Logic Input Current vs Fig. 5 - Bit Transfer Characteristics Fig. 6 • Output Voltage Compliance 

Input Voltage 



"L 
(uA) 

















































TH 


=!0U 


GH 






1 





































-B -4 " 4 B \^ (V) 



Io 
(mA) 

1 
0.8 
0.6 
0.4 
0.2 























J l 


4 <- 




















































































V = -5 





































Al 



-4 4 8 12 V L (V) 



Id 
(mA) 

2.4 

2 

1.6 

A2 1.2 

A3 °' B 
A4 0-4 
A5 











IALL BITS "ON" 1 
































v E 


E=- 


15V 


Ve£=" 


5V 




1 








1 


1 
Il4=2mA 












1 1 












fl 1 


4 1IHM 


1 








































Il4 




1 




i! 




" 1 



-14-10 -B -2 2 B 10 Vo (V) 



Fig. 7 - Output Voltage Compliance 
vs Temperature 



Vo 
(V) 
16 



Fig. 8 - Frequency response 











































//A/A 




■// 


/// 


'/' 


{S- 






''// 




''/, 


'/A 


% 






- 


! 


SHADED AREA 

INDICATES 

PERMISSIBLE OUTPUT 

VOLTAGE RANGE FOR 
V- E =-15V, I 14 =2mA 


'< 






* 








\ 










'<. 










V/ 


y/w/tw/s 


'//, 


7/ 








22 


'///// 


<Zt 


// 


vs 


'// 





































(dB) 

4 



-12 



-50 50 100 T.('C) 



-16 





































B 
























A 












C 



Unless otherwise specified: R14 = 
R15 = 1 kSJ, C = 15 pF, pin 16 to V EE ; 
R L -50n, pin 4 to ground. 

Curve A: Large Signal Bandwidth 
Method of Figure 7, V REF -2 Vp-p 
offset 1 V above ground 

Curve B: Small Signal Bandwidth 
Method of Figure 7, R L = 25052, 
V REF = 50 mVp-p offset 200 mV 
above ground. 

Curve C: Large and Small Signal 
Bandwidth Method of Figure 9 (no 
op amp. R L - 50!!), R s = 500, 
Vp; E p-2V, Vg = 100 mVp-p centered 
at 0V. 



0.1 0.2 0.5 1 2 (MHz) 



336 



DAC0808 
DAC0807 
DAC0806 



Test Circuits 



FIGURE 9. Notation Definitions 




DAC080B-3 



The resistor tied to pin 1 5 is to temperature compen- 
sate the bias current and may not be necessary for 
all applications. 

IO=K | ^l + ^ + M + M + M + A6 + Al + A& | 
2 4 8 16 32 64 128 256 



where K = 



VREF 
R14 



and An= "1" if An is at high level 
An = "0" if An is at low level 



FIGURE 10. Relative Accuracy 




-VEE O 



337 



DAC0808 
DAC0807 
DAC0806 



FIGURE 11. Transient Response and Settling Time 



£ Vm (Vj 




100 nF A = 15 pF 

| " l~ZZ DAC080B-5 



SETTLING 
• I ME 



ts^ 150ns TYP. 



THANSIEN" 

"ESPONSE 

IOC 



— ~1 ^ T^ ^^- 

DACOBOB -14 



FIGURE 12. Positive V RE f 



FIGURE 13. Negative V REF 



vhef J~L 




DAC0808-7 




~i_r 



IS 



DAC0B0B-8 



338 



DAC0808 
DAC0807 
DAC0806 



FIGURE 14. Reference Current Slew Rate Measurement 




APPLICATION INFORMATION 

CIRCUIT DESCRIPTION 

The DAC0808 consists of a reference current ampli- 
fier, an R-2R ladder, and eight high-speed current 
switches. For many applications, only a reference re- 
sistor and reference voltage need be added. 
The switches are noninverting in operation, there- 
fore a high state on the input turns on the specified 
output current component. The switch uses current 
steering for high speed, and a termination amplifier 
consisting of an active load gain stage with unity gain 
feedback. The termination amplifier holds the para- 
sitic capacitance of the ladder at a constant voltage 
during switching and provides a low impedance ter- 
mination of equal voltage for all legs of the ladder. 
The R-2R ladder divides the reference amplifier cur- 
rent into binarily-related components, which are fed 
to the switches. Nota that there is always a remain- 
der current which is equal to the last significant bit. 
This current is shunted to ground, and the maximum 
output current is 255/256 of the reference amplifier 
current, or 1 .992 mA for a 2.0 mA reference ampli- 
fier current if the NPN current source pair is perfec- 
tly matched. 



REFERENCE AMPLIFIER DRIVE AND COMPEN- 
SATION 

The reference amplifier provides a voltage at pin 14 
for converting the reference voltage to a current, and 
a turn-around circuit or current mirror for feeding the 
ladder. The reference amplifier input current, I14, 
must always flow into pin 14, regardless of the set- 
up method or reference voltage polarity. 

Connections for a positive voltage are shown in Fi- 
gure 12. The reference voltage source supplies the 
full current 1 14. For bipolar reference signals, as in 
the multiplying mode, R15 can be tied to a negative 
voltage corresponding to the minimum input level. 
It is possible to eliminate R15 with only a small sa- 
crifice in accuracy and temperature drift. 

The compensation capacitor value must be increa- 
sed with increases in R14 to maintain proper phase 
margin; for R14 values of 1, 2.5 and 5 kfi, minimum 
capacitor values are 15,37 and 75 pF. The capacitor 
may be tied to either Vee or ground, but using Vee 
increases negative supply rejection. 

A negative reference voltage may be used if R14 is 
grounded and the reference voltage is applied to R15 
as shown in Figure 13. A high input impedance is 
the main advantage of this method. Compensation 
involves a capacitor to Vee on pin 16, using the va- 
lues of the previous paragraph. The negative refe- 
rence voltage must be at least 3V above the Vee 
supply. Bipolar input signals may be handled by con- 
necting R14 to a positive reference voltage equal to 
the peak positive input level at pin 15. 

When a DC reference voltage is used, capacitive by 
pass to ground is recommended. The 5V logic sup- 
ply is not recommended as a reference voltage. If a 
well regulated 5V supply which drives logic is to be 
used as the reference, R14 should be decoupled by 
connecting it to 5V through another resistor and by- 
passing the junction of the 2 resistors with 0.1 ^F to 
ground. For reference voltages greater than 5V, a 
clamp diode is recommended between pin 14 and 
ground. 

If pin 14 is driven by a high impedance such as a tran- 
sistor current source, none of the above compensa- 
tion methods apply and the amplifier must be heavily 
compensated, decreasing the overall bandwidth. 



339 



DAC0808 
DAC0807 
DAC0806 



OUTPUT VOLTAGE RANGE 

The voltage on pin 4 is restricted to a range of - 0.6 
to 0.5V when Vee= -5V due to the current swit- 
ching methods employed in the DAC0808. 

The negative output voltage compliance of the 
DAC0808 is extended to -5V where the negative 
supply voltage is more negative than - 10V. Using 
a full-scale current of 1 .992 mA and load resistor of 
2.5 kfi between pin 4 and ground will yield a voltage 
output of 256 levels between and - 4.980V. Floa- 
ting pin 1 does not affect the converter speed or po- 
wer dissipation. However, the value of the load 
resistor determines the switching time due to increa- 
sed voltage swing. Values of R|_ up to 500Q do not 
significantly affect performance, but a 2.5 kf! load 
increases worst-case setting time to 1 .2 /is (when all 
bits are switched ON). Refer to the subsequent text 
section on Settling Time for more details output 
loading. 

OUTPUT CURRENT RANGE 

The output current maximum rating of 4.2 mA may 
be used only for negative supply voltages more ne- 
gative than - 7V, due to the increased voltage drop 
across the resistors in the reference current amplifier. 

ACCURACY 

Absolute accuracy is the measure of each output cur- 
rent level with respect to its intended value, and is 
dependent upon relative accuracy and full-scale cur- 
rent drift. Relative accuracy is the measure of each 
output current level as a fraction of the full-scale cur- 
rent. The relative accuracy of the DAC0808 is essen- 
tially constant with temperature due to the excellent 
temperature tracking of the monolithic resistor lad- 
der. The reference current may drift with tempera- 
ture, causing a change in the absolute accuracy of 
output current. However, the DAC0808 has a very 
low full-scale current drift with temperature. 

The DAC0808 series is guaranteed accurate to wi- 
thin ± 1 12 LSB at a full-scale output current of 1 .992 
mA. This corresponds to a reference amplifier out- 
put current drive to the ladder network of 2 mA, with 
the loss of 1 LSB (8 /iA) which is the ladder remain- 
der shunted to ground. The input current to pin 14 
has a guaranteed value of between 1 .9 and 2. 1 mA, 
allowing some mis-match in the NPN current sour- 
ce pair. The accuracy test circuit is shown in Figure 
10. The 12-bit converter is calibrated for a full-scale 
output current of 1 .992 mA. This is an optional step 
since the DAC0808 accuracy is essentially the same 



between 1 .5 and 2.5 mA. Then the DAC0808 circuits' 
full-scale current is trimmed to the same value with 
R14 so that a zero value appears at the error ampli- 
fier output. The counter is activated and the error 
band may be displayed on an oscilloscope, detected 
by comparators, or stored in a peak detector. 

Two 8-bit D-to-A converters may not be used to con- 
struct a 16-bit accuracy D-to-A converter. 16-bit ac- 
curacy implies a total error of ±1/2 of one part in 
65,536, or ±0.00076%, which is much more accu- 
rate than the ±0.019% specification provided by the 
DAC0808. 

MULTIPLYING ACCURACY 

The DAC0808 may be used in the multiplying mode 
with 8-bit accuracy when the reference current is va- 
ried over a range of 256:1. If the reference current 
in the multiplying mode ranges from 16 p.A to 4 mA, 
the additional error contributions are less than 1 .6 ^A. 
This is well within 8-bit accuracy when referred to 
full-scale. 

A monotonic converter is one which supplies an in- 
crease in current for each increment in the binary 
word. Typically, the DAC0808 is monotonic for all 
values of reference current above 0.5 mA. The re- 
commended range for operation with a DC referen- 
ce current is 0.5 to 4 mA. 

SETTLING TIME 

The "worst case" switching condition occurs when 
all bits are switched "on", which corresponds to a 
low-high transition for all bits. This time is typically 
150 ns for settling to within ±1/2 LSB for 8-bit ac- 
curacy and 100 ns to 1/2 LSB for 7 and 6-bit accu- 
racy. The turn off is typically under 100 ns. These 
timers apply when R|_ <500 ohms and Co ^25 pF. 

The test circuit of Figure 1 1 requires a smaller volta- 
ge swing for the current switches due to internal vol- 
tage clamping in the DAC0808 A 1.0-kilohm load 
resistor from pin 4 to ground gives a typical settling 
time of 200 ns. Thus, it is voltage swing and not the 
output RC time constant that determines setting ti- 
me for most applications. 

Extra care must be taken in board layout since this 
is usually the dominant factor in satisfactory test re- 
sults when measuring settling time. Short leads, 100 
p.F supply bypassing for low frequencies, and mini- 
mum scope lead length are all mondatory. 



340 



DAC0808 
DAC0807 
DAC0806 



PROGRAMMABLE GAIN AMPLIFIER OR DIGI- 
TAL ATTEPUATOR 

When used in the multiplying mode can be applied 
as a digital attenuator. See Figure 15. One advanta- 
ge of this technique is that if Rs = 50 ohms, no com- 
pensation capacitor is needed. The small and large 
signal band are now identical and are shown in Fi- 
gure 8C. 

The best frequency response is obtained by not al- 
lowing I14 to reach zero. However, the high impe- 
dance node, pin 16, is clamped to prevent saturation 
and insure fast recovery when the current through 
R14 goes to zero. Rs can be set for a ±1 .0 mA va- 
riation in relation to I14. I14 can never be negative. 
The output current is always unipolar. The quiescent 
dc output current level changes with the digital word 
which makes accoupling necessary. 

CURRENT TO VOLTAGE CONVERSION 

Voltage output of a larger magnitude are obtainable 
with the circuit of fig. 16 which uses an external ope- 
rational amplifier as a current to voltage converter. 
This configuration automatically keeps the output of 
the DAC0808 ground potential and the operational 
amplifier can generate a positive voltage limited on- 
ly by its positive supply voltage. Frequency respon- 
se and setting time are primarily determined by the 
characteristics of the operational amplifier. In addi- 
tion, the operational amplifier must be compensated 
for unity gain, and in some cases over compensa- 
tion may be desirable. 

Note that this configuration results in a positive out- 
put voltage only, the magnitude of which is depen- 
dent on the digital input. The LM301 can be used 
in a feedforwerd mode resulting in a full scale set- 
ting time on the order of 2.0 fis. 

COMBINED OUTPUT AMPLIFIER AND VOLTA- 
GE REFERENCE 

For many of its applications the DAC0808 requires 
a reference voltage and an operational amplifier. Nor- 
mally the operational amplifier is used as a current 
to voltage converter and its output need only go po- 
sitive. With the popular LM723 voltage regulator both 
of these functions are provided in a single package 
with the added bonus of up to 150 mA output cur- 



rent. See Figure 17. The reference voltage is deve- 
loped with respect to the negative voltage and ap- 
pears as a common-mode signal to the reference 
amplifier in the D-to-A converter. This allows use of 
its amplifier as a classic current-to-voltage conver- 
ter with the non-inverting input grounded. 
Since ±15V and +5.0V are normally available in a 
combination digital-to-analog system, only the -5.0 
V need be developed. A resistor divider is sufficien- 
tly accurate since the allowable range on pin 5 is from 
-2.0 to -8.0 volts. The 5.0 kilohm pulldown resi- 
stor on the amplifier output is necessary for fast ne- 
gative transitions. 

Full scale output may be increasing Rrj and raising 
the + 15V supply voltage to 35 V maximum. The re- 
sistor divider should be altered to comply with the 
maximum limit of 40 volts across the LM723 Co may 
be decreased to maintain the same R0C0 product 
if maximum speed is desired. 

PROGRAMMABLE POWER SUPPLY 

The circuit of figure 17 can be used as a digitally pro- 
grammed power supply by the addition of thumb- 
wheel switches and a BCD-to-binary converter. The 
output voltage can be scaled in several ways, inclu- 
ding to + 25.5 volts in 0.1 - volt increments, ±10 
mV. 

PANEL METER READOUT 

The DAC0808 can be used to read out the status of 
BCD or binary registers or counters a digital control 
system. The current output can be used to drive di- 
rectly an analog panel meter. External meter shunts 
may be necessary if a meter of less than 20 mA full 
scale is used. Full scale calibration can be done by 
adjusting R14 or V re f (see fig. 18). 

CHARACTER GENERATOR 

In a character generation system fig. 19 one DAC0808 
circuit uses a fixed reference voltage and its digital 
input defines the starting point for a stroke. The se- 
cond converter circuit has a ramp input for the refe- 
rence and its digital input defines the slope of the 
stroke. Note that this approach does not result in a 
16-bit D-to-A converter (see Accuracy Section). 



341 



DAC0808 
DAC0807 
DAC0806 



TWO-DIGIT BCD CONVERSION 

Two 8-bit, D-to-A converters can be used to build 
a two digit BCD D-to-A or A-to-D converter (fig. 21). 
If both outputs feed the virtual ground of an opera- 
tional amplifier, 10:1 current scaling can be achieved 
with a resistive current divider. If current output is 
desired, the units may be operated at full scale cur- 
rent levels of 4.0 mA and 0.4 mA with the outputs 
connected to sum the currents. The error of the D- 
to-A converter handling the least significant bits will 
be scaled down by a factor of ten and thus an 
DAC0806 may be used for the least significant word. 

FIGURE 16. 




FIGURE 15. Programmable Gain Amplifier or Di 
Attenuator Circuit 



gital 




When V s = 0. I 14 = 2.0mA 
A|R 



v s 



Vn ■- 10V 



A1 
2 



A2 
4 



256 



FIGURE 17. Combined output amplifier and voltage 
reference circuit 



FIGURE 18. Panel meter readout circuit 





*Kl DAC 



A5 9 



^_, oeoe 

A6 10 | 3.b K 

LSB --, r -^ 

J» 6 j.3 



10 nF 




DACOBOa-10 



(») DIGITAL WORD FROM COUNTER/REGISTER 



342 



DAC0808 
DAC0807 
DAC0806 



FIGURE 19. Digital summing and character generation 



O^r r^„ h^> 



tit 






OVREF.2 
R 14 



DAC 
0808 




>!-T 



DACOBOB-16 



v = doi + io2) Ro 



v - 


Vrefl : Aj+ V ref2: R , 
R14-, R14 2 


Ro 



FIGURE 20. Analog product of two digital words (High Speed Operation) 




-VEE O 



DAC0808-12 



v =-ioi R o = -^fiAi Ro 

R14-, 



v l_ !B! 



R14 2 R14 2 



R \-'^ | !A| 
1 R14i 



Since R = R14 2 and K = 



R14, 



FIGURE 21. Two-digit BCD conversion 



i 02 = K ;Aj ;BI K can be an analog variable 



VREF B14 14 




(*) MOST SIGNIFICANT BCD WORD 
(xx) LEAST SIGNIFICANT BCD WORD 



DAC080B-11 



343 



^^^^^^^F® 



L149 



4A LINEAR DRIVER 



• HIGH OUTPUT CURRENT (4A PEAK) 

• HIGH CURRENT GAIN (10.000 TYP.) 

• OPERATION UP TO ± 20V 

• THERMAL PROTECTION 

• SHORT CIRCUIT PROTECTION 

• OPERATION WITHIN SOA 

• HIGH SLEW-RATE (30V/ms) 

The L149 is a general purpose power booster in 
Pentawatt® package consisting of a quasi-comp- 



lementary darlington output stage with the as- 
sociated biasing system and inhibit facility. 

The device is particularly suited for use with an 
operational amplifier inside a closed loop con- 
figuration to increase output current. 



<<te 



Pentawatt® 



ORDERING NUMBER: L149V 



ABSOLUTE MAXIMUM RATINGS 



V s 


Supply voltage 


± 20 


V 


v. 


Input voltage 


V 5 




v 5 -v 4 


Upper power transistor V CE 


40 


V 


V4-V3 


Lower power transistor V CE 


40 


V 


lo 


DC output current 


3 


A 


lo 


Peak output current (internally limited) 


4 


A 


V|NH 


Input inhibit voltage 


-V s +5 


V 






-V s -1.5 


V 


Ptot 


Power dissipation at T case = 75°C 


25 


W 


Tstg , Tj 


Storage and junction temperature 


-40 to 150 


°C 



TEST CIRCUIT 




OOUT 



3- 

"To.l/uF "To.l. 



0-v s 



345 



3/85 



L149 



CONNECTION DIAGRAM (top view) 




(tab connected to pin 3) 



> INPUT 
INHIBIT 



SCHEMATIC DIAGRAM 



Xr< 



-O.v, 



SOA 
PROT. 



^ 



IHERMAL 
PROT 









*, , r 


'NHIBIT 


*-IO< 












I 


SOA 
PROT. 






-OOUT 



346 



L149 



THERMAL DATA 



R th j-case Thermal resistance junction-case 



°C/W 



ELECTRICAL CHARACTERISTICS (Tj = 25°C, V 5 



16V) 



Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit | 


V s - Supply voltage 








± 20 


V 


l d Quiescent drain current 


V s = ± 16V 




30 




mA 


| jn Input current 


V s = ± 16V Vi = OV 




200 


400 


MA 


h FE DC current gain 


V S = ±16V l = 3A 


6000 


10000 




- 


G v Voltage gain 


V 5 =±16V l =1.5A 




1 




— 


VcEsat Saturation voltage 
(for each transistor) 


l =3A 






3.5 


V 


V os Input offset voltage 


V s = + 16V 






0.3 


V 


V| NH Inhibit input voltage 
(pins 1-3) 


ON condition 






± 0.3 


V 


OFF condition 


± 1.8 






R| NH Inhibit input resistance 






2.0 




Kn 


SR Slew rate 






30 




V/ M s 


B Power bandwidth 


V = ± 10V, d = 1%, R L =8f2 




200 




KHz 



APPLICATION INFORMATION 

Fig. 1 - High slew-rate power operational amplifier (SR = 13V//tis) 



rO* v s 




347 



L149 



Fig. 2 - Maximum saturation 
voltage vs. output current 



Fig. 3 - Current limiting 
characteristics 





Fig. 4 - Supply voltage 
rejection vs. frequency 




Fig. 5 - Distortion vs. out- 
put power (f = 1 KHz) 




Fig. 6 - Distortion vs. out- 
put power (f= 10 KHz) 




Fig. 7 - Output power vs. 
supply voltage 




22 26 30 



Fig. 8 - Electronic potentiometer (short-circuit protected) 




(2Amax) 



348 



^^^^^^® 



L165 



3A POWER OPERATIONAL AMPLIFIER 



• OUTPUT CURRENT UP TO 3A 

• LARGE COMMON-MODE AND DIFFER- 
ENTIAL MODE RANGES 

• SOA PROTECTION 

• THERMAL PROTECTION 

• ± 18V SUPPLY 

The L165 is a monolithic integrated circuit in 
Pentawatt® package, intended for use as power 
operational amplifier in a wide range of applica- 
tions, including servo amplifiers and power sup- 



plies. The high gain and high output power ca- 
pability provide superior performance wherever 
an operational amplifier/power booster combina- 



Hon 


IS 


required. 








■^ 


Pentawatt® 






ORDERING NUMBER 


: L165V 



ABSOLUTE 


MAXIMUM RATINGS 






V s 


Supply voltage 


± 18 


V 


v 5 -v 4 


Upper power transistor V CE 


36 


V 


V4-V3 


Lower power transistor V CE 


36 


V 


Vi 


Input voltage 


v s 




V] 


Differential input voltage 


± 15 


V 


lo 


Peak output current (internally limited) 


3.5 


A 


Ptot 


Power dissipation at T case = 90°C 


20 


W 


T"stg> Tj 


Storage and junction temperature 


-40 to 150 


°C 



APPLICATION CIRCUITS 

Fig. 1 - Gain > 10 



Fig. 2 - Unity gain configuration 





349 



12/86 



L165 



CONNECTION DIAGRAM 

(top view) 




3> INVERTING INPUT 
> NON INVERTING INPUT 



tab connected to pin 3 



SCHEMATIC DIAGRAM 




THERMAL DATA 



Thermal resistance junction-case 



°C/W 



350 



L165 



ELECTRICAL CHARACTERISTICS (V, 



15V, Ti = 25°C unless otherwise specified) 



Parameter 


Test conditions 


Mm. 


Typ. 


Max. 


Unit 


v s 


Supply voltage 




± 6 




-.18 


V 


Id 


Quiescent drain current 


V s = ± 18V 




40 


60 


mA 


lb 


Input bias current 




0.2 


1 


M A 


Vos 


Input offset voltage 




± 2 


±10 


mV 


los 


Input offset current 




±20 


±200 


nA 


SR 


Slew-Rate 


G v = 10 




8 




V/ M s 


G v = 1 (<>) 




6 




v 


Output voltage swing 


f = 1 kHz l p = 0.3A 
lp = 3A 




27 
24 




V PP 


f=10kHz l p = 0.3A 
lp = 3A 




27 
23 




V PP 


Ri 


Input resistance (pin 1) 


f = 1 KHz 


100 


500 




Kfi 


Gv 


Voltage gain (open loop) 




80 




dB 


e N 


Input noise voltage 


B = 1 to 1 000 Hz 




2 




MV 


'N 


Input noise current 




100 




PA 


CMR 


Common mode rejection 


R g «:lOKn G v =30dB 




70 




dB 


SVR 


Supply voltage rejection 


R g = 22 kn 
Vripple=0.5 V rms 
f ripple= 10° Hz 


G v = 10 




60 




dB 


G v = 100 




40 




dB 


V 


Efficiency 


f = 1 kHz 
R L = 4a 


lp = 1.6A; P = 5W 




70 




% 


lp = 3A; P D = 18W 




60 




% 


Tsd 


Thermal shut-down case 
temperature 


P tot =12W 




110 




°C 


P tot = 6W 




130 





(°) Circuit of fig. 2 



351 



L165 



Fig. 3 -Open loop frequency Fig. 4 - Closed-loop fre- 

response quency response (circuit of 

fi 'g-2) 







T.~ 












5 V 
























PHASE 






































GAIN 









































































I 










V s _ • • 5 V 














/ 












/ _ 


















PHASE 
























ga:n 


\ 












* 














\ 



























Fig. 5 - Large signal fre- 
quency response 



(Vpp) 
























i | 












"»■ 


" 






































1 






i 




2i, 
20 






















■ R u =50J1 






















R 




a \ 

| 






J 












ill 












\ 


















III 










1 


\ 






II 


































1 














^ 






i 














I 








! 





Fig. 6 -- Maximum output 
current vs. voltage [V CE ] 
across each output transistor 





r 
















" 


" 




r T 








r- 


- 


i,' 




r_i i 




i 










- 






s 




^- 
















; 


1 


7 








^ 


s 






















- 


t 




1 
































CI 






















































































































































































































































r" 














































i-r 






































a? 












- 












-N*- 














/ 


















V 
































A 






































_L 








_ 




_i_ 











Fig. 7 - Safe operating area 
and collector characteristics 
of the protected power 
transistor 




Fig. 8 - Maximum allowable 
power dissipation vs. am- 
bient temperature 



4 j i , i_i_ _+ 


44 






4i — M-l — ~-i 




"^ \T^~~^T^ 




e — i- j \ J\- yJ rr \~\ r 


4:4:3 






































■• ii " " j t ■ '"'^s. '^v 1 v - 














~ +— I - !"! ' !~"~H"~ TMB 




■ft f-t— — F 1 1 i f- i — Tf^ 


-4- 



IDO '5CT amb CC) 



Fig. 9 - Bidirectional DC motor control with TTL/CMOS/mP compatible inputs 

4x1N/.00t I 



"*" i ? * 1 

J L -i L 




El, E2 = logic inputs 
Vgi = logic supply voltage 



352 



L165 



Fig. 10 - Motor current control circuit with external power transistors (i mo tor > 3.5A) 



36KH lOKil 

R'* R2* 



J.3Kfi.2*/. 3.3 KA 2% 




X |— ©uT X i'l 



0.22 j 0.22^i 

. kJr^ X 




36K.fi 10 KH 



R3* R4# 







1 



*R< 



looKnz'.', 



V F < 1.2V @ I =4A 
trr < 500 ns 



D1 to D4 : 

Note: The input voltage level is compatible with L291 (5-BIT D/A converter) . 



The transfer function is : M 
V; 



R4 



Rx R3 



Fig. 1 1 - High current tracking regulator 



ur l 



-#„ 



^Jj 



1,. 



T 



Fig. 12 - Bidirectional speed control of 
DC motor (Compensation networks 
not shown) 




A: for ± 18 < V; < ± 32 

Note — V z must be chosen in order to verify 
2 Vj - V z < 36V 

B: for V ; < i 18V 



D1 D2- ! V F«12V@ l = 2A 

I trr < 500 ns 



353 



L165 



Fig. 13 - Split power supply 



hoo ' 

r 



= i.7uF 




i,7^jF 



.7K/1 0.22^jF 



T " : Ko- t4 to ±18 



Fig. 14 - Power squarewave oscillator with independent adjustments for frequency and duty-cycle. 




P1 : duty-cycle adjust 

o v oui _fl_J|_ p 2 ■ frequency adjust (f = 700 Hz with 
C1= 10 nF, P2= 100 Kn, f=25 Hz 
with C1= 10 nF, P2=0) 



354 



^^^^^^^^r® 



L200 



ADJUSTABLE VOLTAGE AND CURRENT REGULATOR 



ADJUSTABLE OUTPUT CURRENT UP TO 
2A (GUARANTEED UP TO T, = 150°C) 

ADJUSTABLE OUTPUT VOLTAGE DOWN 
TO 2.85V 

INPUT OVERVOLTAGE PROTECTION (UP 
TO 60V, 10ms) 

SHORT CIRCUIT PROTECTION 

OUTPUT TRANSISTOR S.O.A. PROTEC- 
TION 

THERMAL OVERLOAD PROTECTION 

LOW BIAS CURRENT ON REGULATION 
PIN 

LOW STANDBY CURRENT DRAIN 



The L200 is a monolithic integrated circuit for 
voltage and current programmable regulation. It 
is available in Pentawatt® package or 4-lead 
TO-3 metal case. Current limiting, power limiting, 
thermal shutdown and input overvoltage protec- 
tion (up to 60V) make the L200 virtually blow- 
out proof. The L200 can be used to replace fixed 
voltage regulators when high output voltage pre- 
cision is required and eliminates the need to stock 
a range of fixed voltage regulators. 




Pentawatt® 



: ^W 



TO-3 (4 lead) 



ABSOLUTE MAXIMUM RATINGS 



v i 


DC input voltage 


40 V 


Vi 


Peak input voltage (10 ms) 


60 V 


AVi_ 


Dropout voltage 


32 V 


'o 


Output current 


internally limited 


Mot 


Power dissipation 


internally limited 


T s tg 


Storage temperature 


-55 to 150 °C 


' op 


Operating junction temperature for L200C 


-25 to 150 °C 




for L200 


-55 to 150 °C 



APPLICATION CIRCUITS 

Fig. 1 - Programmable voltage regulator with 
current limiting 




Fig. 2 - Programmable current regulator 




355 



3/85 



L200 



CONNECTION DIAGRAMS AND ORDERING NUMBERS 

(top views) 



OUTPUT 

> REFERENCE 
GND 

> LIMITING 
INPUT 




Type 


Pentawatt® 


TO-3 


L200 




L200T 


L200C 


L200CH 
L 200 CV 


L 200 CT 



BLOCK DIAGRAM 



o — 

INPUT 



PASS 
ELEMENT 



S.O.A. 

PR0TECTON 



-0 5 



^CURRENT 
/LIMITING 



CURRENT 
SOURCE 



ERROR 
AMPLIFIER 



COMPARATOR 



-0« 



REFERENCE 



THERMAL 
PROTECTION 



03 GROUND 



356 



SCHEMATIC DIAGRAM 



L200 



R8 'R9 



07^ 



01* 
D2* 



f Q15 



Z2» 


-r 


z 7 




R21 1 1 


I 


Q2l' x 1 -i 

r 





I |R26 R28 ■ R23 

i. D3t 

|026 v l- • ^02? 



--K.'qu 



, T Z1 S '" ' t I.Q23: • 

^ _ X t FQ29 030 t • 

! Rf R ! ! R R R | 

' 18. J 19 - 20 22 23 C3 

► „ •+'Q16 Q19>t t1|« • "• t If -t 



- T 
3 fj ' F 



-sH ,. _ 



Ql>4t;Q3 ^'05 



- • J Q!2 Q13 i - ; 

— - ■ + Q17 

v 

I— I' Q1! R13 ' ! , R „! 
A .- ! 'X 



"020 Q24*" 



031";! : . , . 

* R P. Q32 X 4 -M:'033 

27' J r* *■ ' 

4 "1 I L ♦. 1 i X <2: 

-» - ■ - *- ■£! 



• — KQ10 R12 



•-— . t.'Q18 



Rl ! R2 |R4. . R6 R7| 



-J'Q25 



THERMAL DATA 




TO-3 


Pentawatt ® 


R th ,. case Thermal resistance junction-case 
R th j-amb Thermal resistance junction-ambient 


max 
max 


4°C/W 
35 °C/W 


3°C/W 
50°C/W 



ELECTRICAL CHARACTERISTICS (T amb = 25°C, unless otherwise specified) 



Parameter 


Test conditions 


Min. 


Typ. Max. 


Unit 



VOLTAGE REGULATION LOOP 



l d Quiescent drain current (pin 3) 


V, = 20V 




4.2 


9.2 


mA 


e^ Output noise voltage 


V -V re( l o -10mA 
B - 1 MHz 




80 




>,V 


V Output voltage range 


l„ - 10 mA 


2.85 




36 


V 


AV o Voltage load regulation 
V (note 1) 


,-A - 2 A 
L\ = 1.5A 




0.15 
0.1 


1 
0.9 


% 


AV i Line regulation 

m7~ 


Vo- 5V 

V ( - 8 to 18V 


48 


60 




dB 


SVR Supply voltage rejection 


V - 5V I Q = 500 mA 

AV r 10 V pp 

f - 100 Hz (note 2) 


48 


60 




dB 



357 



L200 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


AVi_ 


Droupout voltage between 
pins 1 and 5 


l = 1.5A &V ^ 2 % 




2 


2.5 


V 


Vref 


Reference voltage (pin 4) 


V; = 20V l o =10mA 


2.64 


2.77 


2.86 


V 


AV ref 


Average temperature 
coefficient of reference voltage 


Vi = 20V l o =10mA 

forTj=-25 to 125"C 
forTj= 125 to 150°C 




-0.25 
-1.5 




mV/°C 
mV/°C 


14 


Bias current at pin 4 






3 


10 


M A 


Al 4 


Average temperature 
coefficient (pin 4) 






-0.5 




%rc 


AT.| 4 


Zo 


Output impedance 


V, = 10V v =v ref 
l = 0.5A f = 100 Hz 




1.5 




mS2 



CURRENT 


REGULATION LOOP 












v S c 


Current limit sense voltage 
between pins 5 and 2 


Vi=10V v = v ref 
l 5 = 100 mA 


0.38 


0.45 


0.52 


V 


AV SC 


Average temperature 
coefficient of V sc 






0.03 




%/°C 


AT-V SC 


Al 


Current load regulation 


Vj = 10V AV = 3V 
l D = 0.5A 
l =1A 
l = 1.5A 




1.4 

1 

0.9 




% 
% 
% 


lo 


Isc 


Peak short circuit current 


V, - V = 14V 

(pins 2 and 5 short circuited) 






3.6 


A 



Note 1): A load step of 2A can be applied provided that input-output differential voltage is lower than 20V (see 
fig. 3). 

Note 2): The same performance can be maintained at higher output levels if a bypassing capacitor is provided bet- 
ween pins 2 and 4. 



358 



L200 



Fig. 3 - Typical safe oper- 
ating area protection 




Fig. 4 - Quiescent current 
vs. supply voltage 




Fig. 5 - Quiescent current 
vs. junction temperature 




-2.0 «3 80 120 Tj (*C) 



Fig. 6 - Quiescent current 
vs. output current 



Fig. 7 - Output noise voltage 
vs. output voltage 



Qi. 08 12 




Fig. 8 - Output noise voltage 
vs. frequency 



- ■ '^ V RMS" 



IMS'- ' 




10 10 10 1 IHi) 



Fig. 9 - Reference voltage 
vs. junction temperature 



v rH 






^ — ■ - 


. 








— - - v o =v ref 

[ Q =10mA 










-— • - 










2760 


- 






^ ! 




\ i 














\ 










^ 4 4^1 
















; . . , i 1 : 



Fig. 10 - Voltage load regu- 
lation vs. junction tempera- 
ture 



Fig. 11 - Supply voltage re- 
jection vs. frequency 



-40 *0 80 120 T, CO) 




359 



L200 



Fig. 12 - Dropout voltage 
vs. junction temperature 




Fig. 13 - Output impedance 
vs. frequency 
■• ■ !:::'3 : ]■•■■<% --n ■ ';■■!» > -'■'■-■ 

: : ;! ;!:J :':-' ' , ■ .1 ^ 



-W 40 8C 120 T: CC) K. « ; 




Fig. 14 - Output impedance 
vs. output current 




Fig. 15 - Voltage transient 
response 



v ° r~ 


, ^_, 


— ~- 


— — 


■ ■-r-i— 


r - r- - n 


















20 U 
20 h 
























t— 


\ 


, | : 
















\ 








/ " " 












/ : ' ■ " 


-40 \ ■ 
-60 - ; 


* fc o =0. 




■ y 


\ 


/::-■:' 


t - 


1 






1 






































\: 








:: 


: '- ; - : 1 


1 






1 


1 





Fig. 16 - Load transient response 



I I" 

AV n = 200mV 




^s l^s '^s 5 23; 



12 3 4 5 6 



Fig. 17 - Load transient response 




Fig. 18 - Current limit sense 
voltage vs. junction tem- 
perature 




-40 40 



360 



L200 



APPLICATION CIRCUITS 

Fig. 19 - Programmable voltage regulator Fig. 20 - P.C. board and components layout of fig. 19. 

(1:1 scale) 




n¥ ft 

I I © <§> ® q> 



Fig. 21 - High current voltage regulator with 
short circuit protection 




jo.i^ I 

•T: 



Fig. 22 - Digitally selected regulator with 
inhibit 



Fig. 23- Programmable voltage and current regulator 



I oi n 

PI R 2 V =V f to26V 

I 47011 

^ ! n = 35rrAtol5A 




1 

*P1:CURRENT REGULATION J_ s _ t , 

P2 : VOLTAGE REGULATION 

Note: Connecting point A to a negative voltage (for example -3V/10 mA) it is possible to extend the output voltage 
range down to 0V and to obtain the current limiting down to this level (output short-circuit condition). 



361 



L200 



APPLICATION CIRCUITS 



Fig. 24 - High current regulator with NPN 
pass transistor 



Fig. 25- High current tracking regulator 




^; 



r- : " 



--L'\ 



A: for ±18 < V;<±32 

Note — V z must be chosen in order to verify 
2 V, -V z « 36V 

B: for V, <± 18V 



Fig. 26 - High input and output voltage 



Fig. 27 - Constant current battery charger 




*n 



The resistors H t and R 2 determine the final 
charging voltage and R sc the initial charging 
current. D[ prevents discharge of the battery 
throught the regulator. 

The resistor R L limits the reverse currents 
through the regulator (which should be 100 
mA max) when the battery is accidentally 
reverse connected. If R L is in series with a 
bulb of 12V/50 mA rating this will indicate 
incorrect connection. 



362 



L200 



APPLICATION CIRCUITS (continued) 
Fig. 28 - 30W Motor speed control 




(M ) V M SS0.22/JF 

- JJ T 



R, Rm 



v m = v r , 



(1 + 



Ri 



Fig. 29 - Low turn on 




^£E-- 



Fig. 30- Light controller 




363 



SS 



L272 
L272M 



PRELIMINARY DATA 



DUAL POWER OPERATIONAL AMPLIFIERS 



• OUTPUT CURRENT TO 1A 

• OPERATES AT LOW VOLTAGES 

• SINGLE OR SPLIT SUPPLY 

• LARGE COMMON-MODE AND DIFFER- 
ENTIAL MODE RANGE 

• GROUND COMPATIBLE INPUTS 

• LOW SATURATION VOLTAGE 

• THERMAL SHUTDOWN 

The L272 and L272M are monolithic integrated 
circuits in powerdip and minidip packages in- 
tended for use as power operational amplifiers in 
a wide range of applications including servo ampli- 
fiers and power supplies, compact disc, VCR, etc. 



The high gain and high output power capability 
provide superior performance whatever an opera- 
tional amplifier/power booster combination is 

required. 




V 



Powerdip 8+8 Minidip Plastic 

ORDERING NUMBERS: 

L272 L272M 



ABSOLUTE MAXIMUM RATINGS 



v s 


Supply voltage 




28 


V 


v, 


Input voltage 




v s 




v, 


Differential input voltage 




±V S 




lo 


DC output current 




1 


A 


Ip 


Peak output current (non repetitive) 




1.5 


A 


ftot 


Power dissipation at T amb = 80°C (L272), T amb 


= 50°C (L272M) 


1 


W 




Tease =75°C(L272) 




5 


W 


T stg. T i 


Storage and junction temperature 




-40 to 150 


°C 



BLOCK DIAGRAM 



8 O- 

' o- 



6 O- 
5 O- 



t> 



t> 
t> 



x 



L272 



L272M 



365 



12/86 



L272 
L272M 



CONNECTION DIAGRAM 








(Top view) 
















\J 








OUTPUT 1 | 


' 




t6 


|gnd 


OUTPUT 1 


Vs 1 


2 




15 


|gnd 


SUPPLY V( 


OUTPUT 2 | 


3 




H 


Jgnd 


OUTPUT 2 


GNO 


U 




13 


|gnd 


GND 


INPUT-2 


5 




12 


|gnd 




INPUT- 2 


6 




•' 


Jgnd 




1NPUT.1 


7 




10 


Jgnd 




INPUT -1 i 


8 




9 


Jgnd 










S-S905 







L272 



SCHEMATIC DIAGRAM (one only) 



I 8 j INPUT - 

e[ 2 7 ]lNPUT*1 




jlNPUT.2 
] INPUT-2 



L272M 




THERMAL DATA 




Powerdip 


Minidip 


^thj-case Thermal resistance junction-pins 
Rthj-amb Thermal resistance junction-ambient 


max 
max 


15°C/W 
70°C/W 


*70°C/W 
100°C/W 


* Thermal resistance junction-pin 4 



366 



L272 
L272M 



ELECTRICAL CHARACTERISTICS (V s = 24V, T amb = 25°C unless otherwise specified) 





Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V s 


Supply voltage 




4 




28 


V 


Is 


Quiescent drain current 


v s 


V s = 24V 




8 


12 


mA 


V s = 12V 




7.5 


11 


mA 


lb 


Input bias current 






0.3 


2.5 


HA 


Vos 


Input offset voltage 






15 


60 


mV 


los 


Input offset current 






50 


250 


mA 


SR 


Slew rate 






1 




V/ms 


B 


Gain-bandwidth product 






350 




KHz 


R| 


Input resistance 




500 


| 


Kfi 


Gv 


O.L. voltage gain 


f = 100Hz 




60 


70 


dB 


f = 1KHz 




50 


dB 


e N 


Input noise voltage 


B = 20KHz 




10 


MV 


In 


Input noise current 


B = 20KHz 




200 


PA 


CRR 


Common Mode rejection 


f = 1KHz 


60 


75 


dB 


SVR 


Supply voltage rejection 


f = 100Hz 
R G = 10KO 
V R - 0.5V 


V s = 24V 
V s = ±12V 
V s = ± 6V 


54 


70 
62 
56 




dB 
dB 
dB 


Vo 


Outout voltage swing 


lp = 0.1A 
lp = 0.5A 


21 


23 
22.5 




V 
V 


Cs 


Channel separation 


f=1KHz; R L =10H; G v =30dB 
V 5 = 24V 
V s = ± 6V 




60 
60 




dB 
dB 


d 


Distortion 


f = 1KHz 
V s = 24V 


G v = 30dB 
R L = <x 




0.5 




% 


T sd 


Thermal shutdown 
junction temperature 


■ - ■ ■ ■ — 




145 




°C 



367 



L272 
L272M 



Fig. 1 - Quiescent current 
vs. supply voltage 





' 





































-- 























- 


• - 
















I i . I 







Fig. 2 -- Quiescent drain 
current vs. temperature 





- 




1" ' 

■--I-- ' ■ 




1 i I ! 1 ! 


■■ v *- zw l ! . 










— 








^ ■ i ■ 








"v^ ■ . 








' N \ i i 
























T 








! 






1 , i 





Fig. 3 - Open loop voltage 
gain 



12 16 20 24 V S (V: 




Fig. 4 - Output voltage 
swing vs. load current 















— - 


-- 












V 5 = 112V 

































































































































Fig. 5 - Output voltage 
swing vs. load current 



— ' 1 1 — i < — 1-.- 



Fig. 6 - Supply voltage 
rejection vs. frequency 



— 


— 


V s = 1 1 2 V 










- 




REFINPUT ( 
- i 


3, -1011! 










^~T\ 






- 


- • 






1 




" 



200 400 600 



200 400 000 i L OAD (m 



Fig. 7 - Channel separation 
vs. frequency 



Fig. 8 - Common mode 
rejection vs. frequency 




368 



L272 
L272M 



APPLICATION SUGGESTION 

NOTE 

In order to avoid possible instability occurring 
into final stage the usual suggestions for the 
linear power stages are useful, as for instance: 
— layout accuracy; 



— A 100nF capacitor corrected between supply 
pins and ground; 

— boucherot cell (0.1 to 0.2flF +1S2 series) bet- 
ween outputs and ground or across the load. 



Fig. 9 - Bidirectional DC motor control with |UP compatible inputs 




V S1 = logic supply voltage 
Must be V S2 > V S1 
E1, E2 = logic inputs 



Fig. 10 - Servocontrol for compact-disc 



REFLECTED k 

BEAM ) 




Fig. 11 - Compact-disc motor driver (1/2 section 




369 



L272 
L272M 



Fig. 12 - Capstan motor control in video recorders 




1° 



Fig. 13 - Motor current control circuit 




36KD 2.5KQ 10KO 2V. 

Note: The input voltage level is compatibie with L291 (5-BIT D/A converter) 



Fig. 14 - Bidirectional speed control of DC motors. 

O DO CM 

For circuit stability ensure that R x > = where R M = internal resistance of motor. The voltage 

V 2R°R1 

available at the terminals of the motor is V M = 2 ( V, 4 — ) + I Ff 1. I M where |R ! = g and 

2 nj( 

l M is the motor current. 




370 



^^^^^Wb 



L290 



TACHOMETER CONVERTER 



The L290, a monolithic LSI circuit a 16-lead 
dual in-line plastic package, is intended for use 
with the L291 and L292 which together from a 
complete 3-chip DC motor positioning system 

for applications such as carriage/daisy-wheel 
position control in typewriters. 

The L290/1/2 system can be directly controlled 
by a microprocessor. The L290 integrates the 
following functions : 

— tacho voltage generator (F/V converter) 
-- reference voltage generator 

— position pulse generator 




<2| DIP-16 Plastic 

(0.4) 



ORDERING NUMBER: L290B 



ABSOLUTE MAXIMUM RATINGS 



V s Suoply voltage 

V, (FTA, FTB, FTF) Input signals 

P tot Total power dissipation T amb = 70°C 

T stg , Tj Storage and junction temperature 



±15 V 

±7 V 

1 W 

-40 to + 150 °C 



SYSTEM BLOCK DIAGRAM 



MICROPROCESSOR 



— -------' f --M-'-'-t. 

A A: U 



TACHO 
CONV. 






i 


292 




*l 


r<H 



^^ L291 



OPTO. 
ENC. 



-(J 



371 



1 2/86 



]l, FTA 
J15 VAA 
]l'. STA 
]l3 STB 



Sir gk 



.--': 





v s ! GNO 






v =] 






: f i 


r — 1 

" ] x p 
~Ts7l.J , 






TACHO 


,_..__„;■.... 


<f 




FTF 


l- j ; 


;l.^i :SB 




~_L 


STF 


^ i 








<L 








^H ~* 


RE F. 
GEN. 




Vref 























TEST CIRCUIT 




L290 



THERMAL DATA 



R th j- 



Thermal resistance junction-ambient 



max 80 °C/W 



ELECTRICAL CHARACTERISTICS (Refer to the test circuit, S in(A),V s =±12V,T amb = 25°C 
unless otherwise specified) 



Parameters 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


V s Supply voltage 




±10 




±15 


V 


l^ Quiescent drain current 


V s = ± 15V 




13 


20 


mA 


INPUT AMPLIFIERS (AiandA;,) 


FTA, FTB Input signal from encoder 
(pin 1, 16) 


f max = 20 KHz 


z0.4 




±0.6 


V P 


V os Output offset voltage 
(pin 2, 15) 


FTA = FTB =0V 






t 55 


mV 


lb Input bias current (pin 1, 16) 






0.15 




MA 


G v Voltage gain 


f=10KHz FTA=FTB=i0.6V p 


22 


23 


24 


dB 


V Output voltage swing 
(pin 2, 15) 


FTA= FTB= ± 1 V p 


±9.5 






V 



373 



L290 



ELECTRICAL CHARACTERISTICS (continued) 



Parameters 


Test conditions 


Min. 


Typ. 


Max. 


Unit 



COMPARATORS WITH HYSTERESIS (Ci,C 2 andC 3 



V T HP<°> 


Positive Threshold voltage 
(pin 2, 12, 15) 


Ci and C 2 


550 




850 


mV 


c 3 


700 




300 


mV 


V THN<°° 


Negative Threshold voltage 
(pin 2, 12, 15) 


Cj and C 2 


55 




175 


mV 


c 3 


570 




830 


mV 


AFTF 


Threshold Hysteresis 


c 3 


72 




120 


mV 


v L 


Output voltage (low level) 
(pin 10, 13, 14) 


l = 2 mA 
FTA= FTB= 


FTF=0V 




0.2 


0.4 


V 


'leak 


(pins 10, 13, 14) 


FTA= FTB= 
V CE =5V 


0.5V 

FTF= 1V 






1 


MA 



REFERENCE GENERATOR 



V re f DC reference voltage 
(pin 3) 


FTA=- FTB = ± 0.5V p (*) 
l ref - 1 mA 


4.5 


5 


5.5 


V 


! ref Output current (pin 3) 








1.4 


mA 



"TACHO" AMPLIFIER (A 3 



V os Output offset voltage (pin 4) 


FTA= + 15 mV FTB= 0.5V 






= 80 


mV 


V DC output voltage (pin 4) 


FTA= FTB= >0.5Vp 
V M A=V MB = + 1.25V p 


("*) 
Vol 


5.4 


6 


6.6 


V 


V 2 


-5.4 


-6 


-6.6 


AV Q 


V a + v o2 


-150 




+ 150 


mV 


V Q Output voltage swing (pin 4) 


S in (B) 


FTA= FTB= 0.5V 


9 






V 


FTA= FTB= -0.5V 


-9 






Vma Multiplier input voltage 
V MB (pin 7, 8) 






:• 1.25 


± 1.7 


Vp 


V b j as Bias voltage (pin 6) 


FTA and FTB floatino 


-6.5 




-8 


V 



(°) : FTA= FTB = FTF = J ('- 

Note : Phase relationship between the signals: 
* FTA : 0° FTB : 90° 



** FTA : 0° 
*** FTA : 0° 



FTB : -90° 
FTB : 90° 



FTA = FTB = FTF = 



= 90° V MR =0° 



Vk... 

V MA =90= V MB =180° 



374 



WAVEFORMS (Neglecting threshold voltage level of the comparators) 



L290 




ANTICLOCKWISE 
DIRECTION 




SYSTEM DESCRIPTION : refer to the L292 data sheet 



375 



L290 



Fig. 1 - Complete application circuit 








q 




I '" 5 


.i 


LW\ 




C.'IN 


DA 


'OJT 


— ? 


S . C \ 






- 


■■ IsS^ER™ 


—' 


SC2 
SC2 




'rjACC 


'i- 


"^,, 


- 5 


SC 5 








^ 


6 


..'R-info 


SIGN 


-. 


,*. 




Sirobe 












D1 to D4 : 



trr =S 200 ns 



376 



^^^^^^s 



5 BIT - D/A CONVERTER AND POSITION AMPLIFIER 



The L291, a monolithic LSI circuit in a 16-leacl 
dual in-line plastic package, is intended for use 
with the L290 and L292 to form a complete 
3 chip DC motor positioning system for applica 
tions such as carriage/daisy-wheel position 
control in typewriters. 

The L290/291/292 system can be directly con- 
trolled by a microprocessor. 

The L291 integrates the following functions: 

— 5 bit D/A converter (% LSB max linearity 
error); 

— error amplifier; 

— position amplifier. 




DIP-16 Plastic 

(0.4) 



ORDERING NUMBER: L291B 



ABSOLUTE MAXIMUM RATINGS 



V s Supply voltage 

P tot Total power dissipation T amb = 70°C 

Tstg, Tj Storage and junction temperature 



1 
-40 to 150 



V 
W 
°C 



SYSTEM BLOCK DIAGRAM 




! 


129 2 






r<3- ; 


I 







377 



12/86 



L291 



CONNECTION DIAGRAM 

(top view) 







W 


ERRV 


'I 




sc, 


>[ 




sc 2 


3[ 




sc J 


l 




sc^ 


= [ 




sc 5 


*l 


} 


SIGN. 


'[ 


] 


Strobe 


°l 


1 



16 P05/0U7 
^ POS/IN 
»V S 
GND 
12 DAC/OUT 
N.C. 
10 -v s 



BLOCK DIAGRAM 




ERRV POS/IN 



378 



TEST CIRCUIT 



L291 







v s 


^5 

9 


SIGN 


JAC/IN 
(A 


sc-.c/^ 


2 


•: 


''" 


7 


9 


5CZO "- 


3 










5C3C) 


L 




L 291 




SC4Q 


5 










5C5C MSB- 


6 




12 1 


15 


13 
16 


trobeO 






C 5ca 


J 








a 


> b 


a / o fc - 




S---5 • 






- A.,00. 


v ""*" 


i 2 . i V 



X 



THERMAL. DATA 



f«i j-amb Thermal resistance junction-ambient 



max 80 °C/W 



ELECTRICAL CHARACTERISTICS (Refer to the circuit, S1 and S2 in (a), V s = ± 12V, 
T amb = 25°C, unless otherwise specified) 



Parameters 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


V s Supply voltage 




± 10 




± 15 


V 


l d Quiescent drain current 






6.5 


10 


mA 



POSITION AMPLIFIER 



^strobe Enaole voltage level 


V L (S in (a)) * 







0.8 


V 


V H (S in (b)) * 


2.4 




+v s 


V 


V os Output offset voltage (pin 16) 


V strobe= V L ; G v =20dB 






± 50 


mV 


l b Input bias current {pin 15) 


V strobe = V L 






0.3 


MA 


V Output voltage swing (pin 16) 


v strobe=V L ;S2in(b);V s =±10.8V 


+ 9 






V 


V R Resdual output voltage (pin 16) 


V strobe = V H 






± 20 


mV 



See block diagram and the note for Position Amplifier. 0-70 



L291 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test conditions Min, 


Typ. 


Max. 


Unit 



D/A CONVERTER 



Iref 


Current reference input range 
(pin 9) 




0.3 




1.2 


mA 


V s 


Current reference offset voltage 
(pin 9) 


l ref = 0.3 to 1.2 rr 
Alt inputs high 


A 






J 20 


mV 


lo 


Output current range (pin 1 2) 








1.4 


mA 


'o 


Output current (pin 12) 


l ref = 0.722 mA 
SC1 to SC5 = L 


SIGN= L (I o1 ) 


-1.358 I 


-1.4 


-1.442 


mA 


SIGN = H (l o2 ) 


+ 1.358 


+ 1.4 


+ 1.442 


AI D 


Linearity error 


lol + 'o2 


-21 




+21 


UA 


l ref = 0.722 mA 






1.61 


%FS 


I OS 


Pin 12 output offset current 
(including Error Amplifier bias 
current} 


All inputs high 






• 0.4 


,uA 


V L 


Low voltage level (digital inputs) 


SC1 = LSB 

SC5 = MSB 







0.8 


V 


Vh 


High voltage level (digital inputs) 


2.4 




+V S . 


V 


II 


Digital inputs current (low state) 


V L = 0.4V 






-50 


juA 


Ih 


Digital inputs current (high state) 


v H =+v s 






1 


MA 



ERROR AMPLIFIER 



V os Output offset voltage (pin 1 ) 


l ref = 0.5 mA; All inputs high 
G v = 40 dB 






t 200 


mV 


l G Output current (pin 1 ) 








± 5 


mA 


V Output voltage swing (pin 1 ) 


All inputs high 

S1 in (b); R L = 10 KP- 


± 7.4 




± 8.4 


Vp 



380 



L291 



D/A Converter 

The L297 contains a 5-bit D/A converter accepting a binary code and generating a bipolar output 
current, the polarity of which depends on the SIGN input. The amplitude of the output current is a 
multiple of a reference current l ref . 
The maximum output current is 



31 
16 



U, 



The following table shows the value of l for different input codes. Note that the input bits are active 
low. 



DIGITAL INPUT WORD 


Output Current 
'o 


SIGN 


SC5 
MSB 


SC4 


SC3 


SC2 


SC1 
LSB 


L 
L 
X 
H 
H 


L 
H 
H 
H 
L 


L 
H 
H 
H 
L 


L 
H 
H 
H 
L 


L 
H 
H 
H 
L 


L 
L 
H 
L 
L 


31 

1 | 
16 



+ — — lref 
16 re 

+ 31 1 



X = indifferent 
L = low 
H = high 



This D/A converter has a maximum linearity error equal to ± 1/2 LSB (or ± 1 .61% Full Scale); that gua- 
rantees its monotonicity. 

Error Amplifier 

In order to have a good stability, the Error Amplifier must work with a closed loop gain greater or equal 
than 20 dB. 

Position Amplifier 

It is inserted by means of the strobe signal, TTL and microprocessor compatible. Its output is connected 
to pin 16 when V strobe = Low; pin 16 is grounded for V strobe = High. 

SYSTEM DESCRIPTION: refer to the L292 data sheet. 



381 



L291 



Fig. 1 - Complete application circuit 




D1IOD4- i V F <1.2V® I-2A 
^ trr < 200 ns 



382 



^^^^^^s 



L292 



SWITCH-MODE DRIVER FOR DC MOTORS 



The L292 is a monolithic LSI circuit in 15-lead 
Multiwatt® package. It is intended for use, 
together with L290 and L291, as a complete 
3-chip motor positioning system for applications 
such as carriage/daisy-wheel position control in 
typewrites. 

The L290/1/2 system can be directly controlled 
by a microprocessor. The outstanding charac- 
teristics of the L292 are : 

— Driving capability: 2A, 36V, 30KHz 

— 2 Logic chip enable 

— External loop gain adjustment 



Single power supply (18 to 36V) 
Input signal symmetric to ground 
Thermal protection 




#■ 



Multiwatt 15 



ORDERING NUMBER: L292 



ABSOLUTE 


MAXIMUM RATINGS 






V s 


Power supply 


36 


V 


v i 


Input voltage 


-15 to +V S 


V 


^Inhibit 


Inhibit voltage 


to V 5 


V 


lo 


Output current 


2.5 


A 


Ptot 


Total power dissipation (T^^ = 75'C) 


25 


W 


T s tg 


Storage and junction temperature 


-40 to +150 


u c 



BLOCK DIAGRAM AND TEST CIRCUIT 




D1 ■ D2 • D3 • D4 = High speed diodes 



383 



12/86 



L292 



THERMAL DATA 



R«i j- 



Thermal resistance junction-case 



°C/W 



ELECTRICAL CHARACTERISTICS (V s = 36V, T amD = 25°C, f osc = 20KHz unless otherwise 
specified) 



Parameter 


Test conditions 


Mini. 


Typ. 


Max. 


Unit 


v s 


Supply voltage 




18 




36 


V 


Id 


Quiescent drain current 


V S = 20V (offset null) 




30 


50 


mA 


Vos 


Input offset voltage (pin 6) 


l o = 






±350 


mV 


Vinh. 


Inhibit low level (pin 12, 13) 








2 


V 


Inhibit high level (pin 12, 13) 




3.2 






V 


'inh. 


Low voltage condition 


V inh . (L)=0.4V 






-100 


M A 


High voltage conditions 


V inh . (H)=3.2V 






10 


MA 


I, Input current (pin (6) 


V, = -8.8V 
V, = +8.8V 






-1.8 
0.5 


mA 
mA 


v, 


Input voltage (pin 6) 


R sl = R s2 =0.2f2 


l =2A 




9.1 




V 


l = -2 A 




-9.1 




V 


lo 


Output current 


V| = ±9.8V R sl = R s2= 0.2n 


± 2 






A 


Vd- 


Total drop out voltage 


(inluding 

sensing 

resistors) 


l =2A 






5 


V 


l =1A 






3,5 


V 


Vr S 


Sensing resistor voltage drop 


Tj = 150°C l =2A 






0.44 


V 


lo 


Transconductance 


R sl = R s2 = 0.2S2 


205 


220 


235 


mA/V 


R sl = R s2 = 0.4f2 




120 




mA/V 


'osc 


Frequency range (pin 10) 




1 




30 


KHz 



TRUTH TABLE 



v inhibit 
Pin 12 Pin 13 



L 
H 
L 
H 



Output stage 
condition 



Disabled 

Normal operation 
Disabled 
Disabled 



CONNECTION DIAGRAM (top view) 



Tab connected 




MOTOR 
INHIBtTfCEU 

inhibit^) 

OSCILL.(R) 

OSC ILL. (C) 

OUTPUTtERR.AMPU 

GND 

INPUT(ERR.AMPL) 

INPUT 

OUTPUT C.S.A. 

C0MP INPUT 

•Vs 

Rs' 



384 



L292 



SYSTEM DESCRIPTION 

The L290, L291 and L292 are intended to be used as a 3-chip microprocessor controlled positioning 
system. These devices may be used separately - particularly the L292 motor driver - but since they will 
usually be used together, a description of a typical L290/1/2 system follows. 



Fig. 1 - System block diagram 







OP TO. 
ENC. 



-<£" 



The system operates in two modes to achieve high-speed, high-accuracy positioning. 

Speed commands for the system originate in the microprocessor. It is continuously updated on the 

motor position by means of pulses from the L290 tachometer chip, which in turn gets its information 

from the optical encoder. From this basic input, the microprocessor computes a 5-bit control word 

that sets the system speed dependent on the distance to travel. 

When the motor is stopped and the microprocessor orders it to a new position, the system operates 

initially in an open-loop configuration as there is no feedback from the tachometer generator. Therefore 

maximum current is fed to the motor. As maximum speed is reached, the tachometer chip output backs 

off the processor signal thus reducing accelerating torque. 

The motor continues to run at top speed but under closed-loop control. 

As the target position is approached, the microprocessor lowers the value of the speed-demand word; 

this reduces the voltage at the main summing point, in effect braking the motor. The braking is applied 

progressively until the motor is running at minimum speed. 

At that time, the microprocessor orders a switch to the position mode, (strobe signal at pin 8 of L291) 

and within 3 to 4 ms the L292 drives the motor to a null position, where it is held by electronic 

"detenting". 



385 



L292 



SYSTEM DESCRIPTION (continued) 

The mechanical/electrical interface consists of an optical encoder which generates two sinusoidal signals 

90° out of phase (leading or lagging according to the motor direction) and proportional in frequency to 

the speed of rotation. The optical encoder also provides an output at one position on the disk which is 

used to set the initial position. 

The opto encoder signals, FTA and FTB are filtered by the networks R 2 C ? and R 3 C 3 (referring to 

Fig. 4) and are supplied to the FTA/FTB inputs on the L290. 

The main function of the L290 is to implement the following expression: 

dV AB FTA dV AA FTB 

Output signal (TACHO) = —£L- • -^ -^- • ^p 

Thus the mean value of TACHO is proportional to the rotation speed and its polarity indicates the 

direction of rotation. 

The above function is performed by amplifying the input signals in A 2 and A 2 to obtain V AA and 

V AB (typ. 7 V p ). From V AA and V AB the external differentiator RC networks R 5 C 5 and R 4 C 4 give 

the signals V MA and V MB which are fed to the multipliers. 

The second input to each multiplier consists of the sign of the first input of the other multiplier before 

differentiation, these are obtained using the comparators C sl and C S2 . The multiplier outputs, C SA and 

C SB , are summed by A 3 to give the final output signal TACHO. The peak-to-peak ripple signal of the 

TACHO can be found from the following expression: 

V r 
The max value of TACHO is: 



Using the comparators Ci and C 2 another two signals from V AA and V AB are derived - the logic signals 

ST A and STB. 

These signals are used by the microprocessor to determine the position by counting the pulses. 

The L29Q internal reference voltage is also derived from V AA and V AB : 

v ref = I v AA | + I V AB | 

This reference is used by the D/A converter in the L291 to compensate for variations in input levels, 
temperature changes and ageing. 

The "one pulse per rotation" opto encoder output is connected to pin 12 of the L290 (FTF) where it is 
squared to give the STF logic output for the microprocessor. 

The TACHO signal and V ref are sent to the L291 via filter networks R 8 C 8 R 9 and R 6 C 7 R 7 respectively. 
Pin 12 of this chip is the main summing point of the system where TACHO and the D/A converter out- 
put are compared. 

The input to the D/A converter consists of 5 bit word plus a sign bit supplied by the microprocessor. 
The sign bit represents the direction of motor rotation. The (analogue) output of the D/A converter - 
DAC/OUT - is compared with the TACHO signal and the resulting error signal is amplified by the error 
amplifier, and subsequently appears on pin 1 . 

386 



ipple p-p a W ^ ' ' 


' v thaco DC 


Vtacho max=-~-\A2~' 


Vthaco DC 



L292 



SYSTEM DESCRIPTION (continued) 

The ERRV signal (from pin 1, L291) is fed to pin 6 of the final chip, the L292 H-bridge motor-driver. 
This input signal is bidirectional so it must be converted to a positive signal because the L292 uses a 
single supply voltage. This is accomplished by the first stage - the level shifter, which uses an internally 
generated 8V reference. 

This same reference voltage supplies the triangle wave oscillator whose frequency is fixed by the external 
RC network (R 20 , C 17 - pins 1 1 and 10) where: 

f °sc=W (with R> 8.2 Kn) 

The oscillator determines the switching frequency of the output stage and should be in the range 1 to30 

KHz. 

Motor current is regulated by an internal loop in the L292 which is performed by the resistors R 18 , R 19 

and the differential current sense amplifier, the output of which is filtered by an external RC network 

and fed back to the error amplifier. 

The choice of the external components in these RC network (pins 5, 7, 9) is determined by the motor 

type and the bandwidth requirements. The values shown in the diagram are for a 5n, 5 mH motor. 

(See L292 Transfer Function Calculation in Application Information). 

The error signal obtained by the addition of the input and the current feedback signals (pin 7) is used 

to pulse width modulate the oscillator signal by means of the comparator. The pulse width modulated 

signal controls the duty cycle of the H-bridge to give an output current corresponding to the L292 

input signal. 

The interval between one side of the bridge switching off and the other switching on, r , is programmed 

by C 17 in conjunction with an internal resistor R T . 

This can be found from: 

T — R T • C pin 10 . (C 17 in the diagram) 

Since R T is approximately 1.5 Kn and the recommended T to avoid simultaneous conduction is 2.5 ms 
C Bin 10 should be around 1 .5 nF. 

The current sense resistors R 18 and R 19 should be high precision types (maximum tolerance ± 2%) and 
the recommended value is given by: 



It is possible to synchronize two L292's, if desired, using the network shown in fig. 2. 

Fig- 2 , L292 4 I l 4 L292 | 

io n 1 | I 10 11 I 



100KQ iini/uF 

FLOAT i— C^ i ||OlA^ — , 

0" 4 



iO.IajF 

R 

c 



Finally, two enable inputs are provided on the L292 (pins 12 and 13-active low and high respectively). 



387 



L292 



SYSTEM DESCRIPTION (continued) 

Thus the output stage may be inhibited by taking pin 12 high or by taking pin 13 low. The output will 
also be inhibited if the supply voltage falls below 18V. 

The enable inputs were implemented in this way because they are intended to be driven directly by a 
microprocessor. Currently available microprocessors may generates spikes as high as 1 .5V during power- 
up. These inputs may be used for a variety of applications such as motor inhibit during reset of the 
logical system and power-on reset (see fig. 3). 



Fig. 3 



L292_ 

CE2 CEl 
12 !3 



1 I- 



d— o • 



Fig, 4 - Application circuit 



FROM ENCODER 
(0) 

r\», A»l {,'3 

gmn 0'«^ U ,lul 

>F !O0pF 100PF 

HI- HM HH 

c, 1 I tj 

- .,, , L290 



«jPROCESSOR '— ' 



1 ! i t>^ ,A 

ftSiilll. U^ 



Ue2on 



Hi— 'II • 

0.1/JF j 0.22, U F , 

«7 r ;?--. ._I'S»„ 



L291 



*■ pRR>^ ERR\ 

'^~ _ POS/IN 

L -t^POS/OUT 



>„ P, 



JsK. 



— i^v-ii 

O.ljjF . O.I^F 



L292 




D1 toD4: < V F< 1 - 2Ve ' =2A 
1 trr «; 200 ns 



388 



L292 



APPLICATION INFORMATION 

This section has been added in order to help the designer for the best choise of the values of external 

components. 

Fig. 5 - L292 block diagram 




The schematic diagram used for the Laplace analysis of the system is shown in fig. 6. 
Fig. 6 



1 LEVEL SHIFTER , ERROR AMPLIFIER 





i pwr> 


A and Moto 


1 tsHC 

sR F C 


i V TH : 


Omo 


1 





SR F C F 



CURRENT 
SENSING 
AMPLIFIER 



R sl = R S2 = R s (sensing resistors) 

— ! — = 2.5 • 10~ 3 £2 (current sensing amplifier transconductance) 
Ra 



R M = Motor resistance 
l M = Motor current 

G mn = _J^ — | n (DC transfer function from the input of the comparator (V TH )to the motor cur- 
rent (l M )). 



'TH 



389 



L292 



APPLICATION INFORMATION (continued) 

Neglecting the V CEsat of the bridge transistors and the V BE of the diodes: 

G mn = -J r^ — where: V s = supply voltage 



Rm V c 



V R = 8V (reference voltage) 



DC transfer function 

In order to be sure that the current loop is stable the following condition is imposed 



1 + sRC = 1 + s 



from which RC : 



(pole cancellation) (2) 

Note that in practice R must be greater than 5.6 Kn) 



The transfer function is then, 



1 + sRpC F 



_[m_ (s) = R 2 ^4 g 

V, RiR 3 m ° G mo R s + sR 4 C+s2 R F C F R.,.C 



In DC condition, this is reduced to 



R2 R4 

Ri R 3 



0.044 A 

RT ^~V~ 



(3) 



(4) 



Open-loop gain and stability criterion 

For RC = L M /R M , the open loop gain is: 

1 „ R, 



Aj3 



Rf 



1 



sR F C 



R 4 1 + sR F C F 



R 4 C s (1 + sR F C F ) 



In order to achieve good stability, the phase margin must be greater than 45° when |Aj3| = 1. 

|A/J| 



That means that, at f F = — — J— — — , must be |A j3 | < 1 (see fig. 7), that is 
2 IT R F C F 



2ir R F Cf 



R s RpCp 

r 4 c VI 



Fig. 7 - Open-loop frequency response 



phase margir 



(5) 



(6) 



390 



APPLICATION INFORMATION (continued) 



L292 



Closed-loop system step response 
a) Small-signals analysis. 

The transfer function (3) can be written as follows: 

0.044 1 



Fig. 8 - Small signal step 
response (normalized ampli- 
tude vs. t/R F C F ) r 



V, 



2?u 



1 + AUL + JL. 
oj co 



(7) 



where: co, 



'o = v 



Gmo 


R s 


R4C Rp 


c F 


' R 4 C 



is the cutoff frequency 
is the dumping factor 



By choosing the £ value, it is possible to determine the system 
response to an input step signal. Examples: 























!" 


H ' ; j 












V + 












f / 




■ 




/ 


















































I i ' . ' i 












I 






I 





1 ) £ = 1 from which 



OV I 



l M (t) 



0.044 



[1 



•e 2Rf ° F (1 



t 



R s ' 4 R F C F 

(where Vj is the amplitude of the input step). 



Fig. 9 -Motor current and pin 7 voltage 
waveforms (application of fig. 5). Small 
signal response 

r: "TnrrsrTw 

J W jII I^ B jBB 



£13 



Eia 



Wi 



mm 






2) £ = — -!= from which 
V2 



Im (t) = 



0.044 



(1 - cos 



2R f TTf" 



2R F C F 



)Vi 






V 7 = 200mV/div. 
I M = lOOmA/div. 
t = lOO^s/div. 
with V, = 1.5 Vp. 



From fig. 9, it is possible to verify that the L292 works in "closed-loop" conditions during the entire 

motor current rise-time: the voltage at pin 7 (inverting input of the error amplifier) is locked to the 

reference voltage V R , present at the non-inverting input of the same amplifier. 

The previous linear analysis is correct for this example. 

Decreasing the £ value, the rise-time of the current decreases. But for a good stability, from relationship 

(6), the minimum value of £ is: 



£ 



1 



2 \J2 



(phase margin = 45°) 



391 



L292 



APPLICATION INFORMATION (continued) 
bj Large signal response 

The large step signal response is limited by slew-rate and inductive load. 

In this case, during the rise-time of the motor current, the L292 works in open-loop condition, as 

can be seen from the photograph of fig. 10. 



Fig. 10 - Motor current and pin 7 voltage waveforms 
(application of fig. 5) Large signal respons.e. 



OV 



V 7 = 1V/div. 
I M = 0.5A/div. 
t = 500 M s/div. 



OA 




The voltage at pin 7 (inverting input of the error amplifier) departs from the reference voltage V R 

present at the non-inverting input and the feedback loop is open. 

The fedback loop is on when the motor current reaches its steady-state value (2A). 



Closed loop system bandwidth 

A good choice for £ is the value 1/\/~2. In this case: 



V, 



0.044 



1 + s R F C F 



The module of the transfer function is: 



l-^-l 
V, 



0.044 



R s 1 + 2s R F C F + 2s 2 R F 2C F 2 

2 y^l +co 2 R F 2 C F 2 

V [ (1 + 2 to R F C F ) 2 + 1 ] • [IT- 2 co -r7(V) 2 + 1 



(8) 



(9) 



The cutoff frequency is derived by the expression (9) by putting j 
from which: 



0.707--°^i(-3dB) 



COy 



0.9 
R F C F 



f = 0-9 
T 2ir R F C F 



392 



APPLICATION INFORMATION (continued) 



L292 



Example: 



a) Data 



b) Calculation 



Motor characteristics : L M = 5 mH 
R M - 5n 

L M /R M = 1 msec 

Voltage and current characteristics: 

V s = 20V l M = 2A 

Closed loop bandwidth: 3 kHz. 



From relationship (4): 
and from (1): 



Rs= ™ V| =0.2 Si 
2 V, 



G mn = 



R M V R 

RC = 1 msec [ from expression (2) ]. 
Assuming £ = 1A/T7 from (7) follows: 



1 n 



¥ = 



400 C 



c) Summarising 



The cutoff frequency is: 



- RC= 1 • 10-3 sec 
1000 C _ , 
R F C F 

- R F C F = 47 /js 



JL = 

2 4 R F C F ■ 0.2 

143 • 10-3 



V, = 9.1V 



R F C F 



= 3 kHz 

C= 47 nF 
R = 22 Kn 

For R F = 510 S2 ->• C F = 92 nF 



393 



^^^^^Ws 



L293 
L293E 



PUSH-PULL FOUR CHANNEL DRIVERS 



• OUTPUT CURRENT 1A PER CHANNEL 

• PEAK OUTPUT CURRENT 2A PER CHAN- 
NEL (NON REPETITIVE) 

• INHIBIT FACILITY 

• HIGH NOISE IMMUNITY 

• SEPARATE LOGIC SUPPLY 

• OVERTEMPERATURE PROTECTION 

The L293 and L293E are quad push-pull drivers 
capable of delivering output currents to 1A per 
channel. Each channel is controlled by a TTL- 
compatible logic input and each pair of drivers 
(a full bridge) is equipped with an inhibit input 
which turns off all four transistors. A separate 
supply input is provided for the logic so that 
it may be run off a lower voltage to reduce 
dissipation. 

Additionally, the L293E has external connec- 
tion of sensing resistors, for switchmode control. 



The L293 and L293E are packaged in 16 and 20- 
pin plastic DIPs respectively; both use the four 
center pins to conduct heat to the printed circuit 
board. 



^rr? 




DIP-16 Plastic 

(0.4) 



Powerdip 
16 + 2 + 2 



ORDERING NUMBERS: L293B (16 leads) 
L293E (20 leads) 



ABSOLUTE MAXIMUM RATINGS 



V s 


Supply voltage 


36 


V 


Vss 


Logic supply voltage 


36 


V 


v. 


Input voltage 


7 


V 


Vinh 


Inhibit voltage 


7 


V 




Peak output current (non-repetitive t = 5ms) 


2 


A 


Ptot 


Total power dissipation at T ground _ piris = 80°C 


5 


W 


T stg / Tj 


Storage and junction temperature 


-40 to 1 50 


U C 



DC motor control 



Bidirectional DC motor control 





395 



12/86 



L293 
L293E 



CONNECTION AND BLOCK DIAGRAM (L293) 

(top view) 









\J 




CHIP ENA 


3LE 1 


1 




16 ] 


INPUT 1 




2 




' 5 ] 


OUTPUT 1 




3 




U 1 


GND 




(, 




13 ] 


GN D 




5 




12 ] 


OUTPUT 2 




6 




"1 


INPUT 2 




' 




10 ] 


V s 




8 




9 1 



INPUT A 
OUTPUTS 
GND 
GND 
OUTPUT 3 
INPUT 3 
CHIP ENABLE 2 




,, _TL 


J L293 ., 


-tl; 


•£ 


*± 


-T.V- V; 




— i 


JT- 


^ ^ 


"1 




* ± 1. 
i„:i_r 


T-r-i 


HM 


_L 


. — s 


j_. 


:<i> 



CONNECTION AND BLOCK DIAGRAM (L293E) 

(top view) 







\J 




CHIP ENABLE ll 


1 




20 


INPUT 1 I 


2 




19 


OUTPUT 1 1 


3 




13 " 


SENSE 1 I 


' 




17 1 


GND I 


5 




16 1 


GND I 


6 




15 ] 


SENSE 2 I 


7 




14 ] 


output; P 


e 




13 ] 


INPUT 2 [ 


9 




12 1 


[ 


10 




11 1 



INPUT U 
OUTPUT L 
SENSE i. 



SENSE 3 

OUTPUT j 

■.NPUT 3- 

h:p enable 2 





W' 


L293E 2C 

19 

1 7 


0* v ss 


ii^z 


4 

5 

7 

6 H 




16 

15 

_H 

13 






9 


LA 


-TLo 


_ - L 




S ■ S ' 6 / ,■ ; 





396 



L293 
L293E 




o en 



1- O 



397 



L293 
L293E 



THERMAL DATA 



Rth j-case Thermal resistance junction-case 
"m i-amb Thermal resistance junction-ambient 



max 
max 



14 
80 



3 C/W 
°C/W 



ELECTRICAL CHARACTERISTICS (For each channel, 
unless otherwise specified) 



V s = 24V, V ss = 5V, T al 



25°C, 



Parameter 


Test conditions 


Min, 


Typ. 


Max. 


Unit 


V s 


Supply voltage 




V s s 




36 


V 


V B 


Logic supply voltage 




4.5 




36 


V 


Is 


Total quiescent supply 
current 


Vj = L l o =0 


V|nh=H 




2 


6 


mA 


Vi = H l o = 


V ln h=H 




16 


24 


V inh =L 






4 


Iss 


Total quiescent logic 
supply current 


Vi = L l o =0 


V in n=H 




44 


60 


mA 


V, = H l o =0 


Vinh=H 




16 


22 


Vinh=L 




16 


24 


V|L 


Input low voltage 




-0.3 




1.5 


V 


v iH 


Input high voltage 


V ss < 7V 


2.3 




V s s 


V 


V S5 > 7V 


2.3 




7 


l|L- 


Low voltage input current 


V, L = 1.5V 






-10 


HA 


liH 


High voltage input current 


2.3V < V iH < V ss 


-0.6V 




30 


100 


MA 


v lnhL 


Inhibit low voltage 




-0.3 




1.5 


V 


v inhH 


Inhibit high voltage 


V ss < 7V 


2.3 




Vss 


V 


V 5S > ™ 


2.3 




7 


'inhL 


Low voltage inhibit current 


V in hL=1-5V 




-30 


-100 


M A 


'inhH 


High voltage inhibit 
current 


2.3V < V inhH < V 


ss -0.6V 






± 10 


ma 


V CEsatH 


Source output saturation 
voltage 


l = -1A 




1.4 


1.8 


V 


v CEsatL 


Sink output saturation 
voltage 


l =1A 




1.2 


1.8 


V 


V 5ENS 


Sensing Voltage 

(pins 4, 7, 14, 17) (**) 








2 


V 


tr 


Rise time 


0.1 to 0.9 V (*) 




250 




"~rf " 


tf 


Fall time 


0.9 to 0.1 V (*) 




250 




ns 


ton 


Turn-on delay 


0.5 V| to 0.5 V (*) 




750 




ns 


x of1 


Turn-off delay 


0.5 V, to 0.5 V D (*) 




200 




ns 



(*) See fig. 1. 

(**) Referred to L293E. 



398 



L293 
L293E 



TRUTH TABLE 



Fig. 1 - Switching times 



v i 


(eacn channel) 


Vo 


Vinh.<°°> 




H 


H 


H 




L 


L 


H 




H 


X(°) 


L 




L 


X <°) 


L 



(°) High output impedance. 

{°°) Relative to the considerate channel. 




Fig. 2 - Saturation voltage 
vs. output current 




Fig. 3 - Source saturation Fig. 4 - Sink saturation volt- 

voltage vs. ambient tempe- age vs. ambient temperature 

rature . .„« 



( V) 


_ljj ;_; _ 






3 


— I — _ — ... — . - - - 




_L_ _j — ■- ■ - 


2 




^^^T..- 












__-t "'o^ 1 * 















' ' l^O.IA 



Fig. 5 - Quiescent logic 
supply current vs. logic 
supply voltage . j5l 



50 - — 



V ; LOW ! 



Fig. 6 - Output voltage vs. 
input voltage 





5 = 24V 
ss= v inhifc.it ^ 5V 

h 




"' 


v s" v C£ satH 








— T amb = 25 *" 














] 


T7 













V CE s 


a.L 





Fig. 7 - Output voltage vs. 
inhibit voltage 



3 V ss ( V ) 



25 v, (v; 




399 



L293 
L293E 



APPLICATION INFORMATION 



Fig. 8 - DC motor controls (with connection 
to ground and to the supply voltage) 



Fig. 9 - Bidirectional DC motor control 



rr^-j 





Vinh 


A 


M1 


B 


M2 


H 


H 


Fast motor 
stop 


H 


Run 


H 


L 


Run 


L 


Fast motor 
stop 


L 


X 


Free running 
motor stop 


X 


Free running 
motor stop 





INPUTS 






FUNCTION 


Vinh'H 


C = H; 


D = 


L 


Turn right 


C = L; 


D = 


H 


Turn left 


C = D 


Fast motor stop 


V in h=L 


C = X; 


D = 


X 


Free running 
motor stop 



L = Low H= High X= Don't care 



L = Low H^ High X= Don't care 



Fig. 10 - Bipolar stepping motor control 



2* i TT :0'* 



"' ' ;> r- 


] 




L293 



="* T7 



n . nH _ | V F < 1.2V@ I = 300 mA 
D1 " D8_ |trr« 500 ns 



400 



L293 
L293E 



APPLICATION INFORMATION (continued) 

Fig. 1 1 - Stepping motor driver with phase current control and short circuit protection 




*:„*-. 



trr < 200 ns 



401 



L293 
L293E 



MOUNTING INSTRUCTIONS 

The R th ;_ amb of the L293 and the L293E can 
be reduced by soldering the GND pins to a 
suitable copper area of the printed circuit board 
as shown in figure 12 or to an external heatsink 
(figure 13). 



During soldering trie pins temperature must 
not exceed 26CTC and the soldering time must 
not be longer than 12 seconds. 
The external heatsink or printed circuit copper 
area must be connected to electrical ground. 



Fig. 12 - Example of P.C. board copper area 
which is used as heatsink 



Fig. 13 - External heatsink mounting 
example (R m = 30 °C/W) 



COPPER AREA 35 M THICKNESS 





/ 

/ 










ffa^faM 

vfa//';, 'fa 


2 

T\^..zfa 






-4- 


L_i 


i 






S#f# 



402 



^^^^^^s 



L293C 



ADVANCE DATA 



PUSH-PULL FOUR CHANNEL/DUAL H-BRIDGE DRIVER 



• 600mA OUTPUT CURRENT CAPABILITY 
PER CHANNEL 

• 1.2A PEAK OUTPUT CURRENT (NON 
REPETITIVE) PER CHANNEL 

• ENABLE FACILITY 

• OVERTEMPERATURE PROTECTION 

• LOGICAL "0" INPUT VOLTAGE UP TO 
1.5V (HIGH NOISE IMMUNITY) 

• SEPARATE HIGH VOLTAGE POWER SUP- 
PLY (UP TO 44V) 

The L293C is a monolithic high voltage, high 
current integrated circuit four channel driver in 
a 20 pin DIP. It is designed to accept standard 
TTL or DTL input logic levels and drive induc- 
tive loads (such as relays, solenoids, DC and step- 
ping motors) and switching power transistors. 



The device may easily be used as a dual H-bridge 
driver: separate chip enable and high voltage 
power supply pins are provided for each H- 
bridge. In addition, a separate power supply 
is provided for the logic section of the device. 

The L293C is assembled in a 20 lead plastic 
package which has 4 center pins connected 
together and used for heatsinking. 



^W 


Powerdip 


rrf^ 


16+2 + 2 


ORDER CODE: 


L293C 



BLOCK DIAGRAM 



VccO— 




O 6 

0UT1 OUT 2 



O ENABLE 2 



O ENABLE 1 



1N2 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

403 12/86 



L293C 



ABSOLUTE MAXIMUM RATINGS 



v s 
v ffi 

V, 
V'en 

'out 



Supply voltage 

Logic supply voltage 

Input voltage 

Enable voltage 

Peak output current (non-repetitive t = 5ms) 

Total power dissipation at T jrou „ cl _p| n5 — 80"C 

Storage and junction temperature 



50 


V 


7 


V 


7 


V 


7 


V 


1.2 


A 


5 


VV 


-40 to 150 


~r 



CONNECTION DIAGRAM 

(Top view) 



TRUTH TABLE 



output ] [ 

(NO 

GNU 

GNO 

OUTPUt 2 [ 

INPUT 2 



G ;c 



^_y- 







"ss 

) ] INPUT 4 
1 8 ] OUTPUT k 
iNC! 
GND 
GND 
(NO 
I ] OUT PUT 3 
'- ] INPUT 3 
' ] ENABLE 2 



INPUT 


ENABLE 


OUTPUT 


H 
L 
X 


H 
L 


H 
L 
Z 



Z = High output irnpedar 
X ^ Don't care 



SWITCHING TIMES 




THERMAL DATA 



™th j-case 
°th j-amb 



Thermal resistance junction-case 
Thermal resistance junction-ambient 



Tiax 
nax 



14 
80 



"C/W 
°C/W 



404 



L293C 



ELECTRICAL CHARACTERISTICS (For each channel, V s = 24V, V ss = 5V, T arr)b = 25°C, 
unless otherwise specified) 





Parameter 


Test Conditions 




Min. 


Typ. 


Max. 


Unit 


v s 


Supply voltage (pin 9, 10) 




Vss 




44 


V 


Vss 


Logic supply voltage (pin 20) 




4.5 




7 


V 


is 


Totai quiescent supply current 
(pin 9, 10) 


V, = L; l = 0; 


Ven = 


H 




2 


6 


mA 


V, = H; l - 0; 


Ven = 


H 




16 


24 




Ven = 


L 






4 


'ss 


Total quiescent logic supply 
current (pin 20) 


V| = L; l = 0; 


Ven = 


H 




44 


60 


mA 


Vj = H; i - 0; 


Ven - 


H 




16. 


22 




Ven " 


L 




16 


24 


V|L 


Input low voltage 
(pin 2, 8, 12, 19) 








-0.3 




1.5 


V 


V|H 


Input high voltage 
(pi-i2, 8 12, 19) 








2.3 




Vss 


V 


l|L 


Low voltaae input current 
(pin 2, 8 "12, 19) 


V| = 1.5V 










-10 


M A 


l|H 


High voltage input current 
(pin 2, 8, 12, 19) 


2.3V < V, < V ss - 


0.6V 






30 


100 


mA 


V ENL 


Enable low voltage (pin 1, 11) 








-0.3 




1.5 


V 


V ENH 


Enable high voltage (pin 1 , 1 1 ) 








2.3 




Vss 


V 


'en l 


Low voltage enable current 
(pi" 1,11) 


V ENL =1.5V 








-30 


-100 


nA 


'enh 


Hich voitage enable current 
(pin 1,11) 


2.3V « VENH < V ss 


-0.6 






,' * 10 


uA 


V CE(sat)H 


Source output saturation voltage 
(pins 3, 7, 13, 18) 


l = -0.6 A 






! 1.4 


1.8 


V 


v CE(sat)L 


Sink output saturation voltage 
(pins 3, 7, 13, 18) 


l = +0.6A 








1.2 


1.8 


V 


V 


Rise time (*) 


0.1 to 0.9 V 








250 




ns 


tf 


Fall time (*) 


0.9 to 0.1 V 




250 




ns 


*on 


Tui-n-orfdelay (*! i 

. | 


0,5 V ; to 0.5 V 








750 




ns 

I 


toff 


Turn-off delay (*) j 


0.5 V, to 0.5 V 








200 




ns i 
i 



(*) See switching times diagram 



405 



^^^^^^' 



L293D 



PRELIMINARY DATA 



PUSH-PULL FOUR CHANNEL DRIVER WITH DIODES 



• 600mA OUTPUT CURRENT CAPABILITY 
PER CHANNEL 

• 1.2A PEAK OUTPUT CURRENT (NON RE- 
PETITIVE) PER CHANNEL 

• ENABLE FACILITY 

• OVERTEMPERATURE PROTECTION 

• LOGICAL. "0" INPUT VILTAGE UP TO 
1.5V (HIGH NOISE IMMUNITY) 

• INTERNAL CLAMP DIODES 

The L293D is a monolithic integrated high volt- 
age, high current four channel driver designed to 
accept standard DTL or TTL logic levels and 
drive inductive loads (such as relays solenoides, 
DC and stepping motors) and switching power 
transistors. 



To simplify use as two bridges each pair of chan- 
nels is equipped with an enable input. A separate 
supply input is provided for the logic, allowing 
operation at a lower voltage and internal clamp 
diodes are included. 

This device is suitable for use in switching appli- 
cations at frequencies up to 5 kHz. 

The L293D is assembled in a 16 lead plastic 
package which has 4 center pins connected 
together and used for heatsinking. 



%i 






Powerdip 
12 + 2 + 2 



>9\ 

ORDERING NUMBER: L293D 



BLOCK DIAGRAM 



IN I ID- 



ENABLE I O- 



IN 2 O- 




X" 



OUT I OUT 3 

9 9 



9 9 

OUT 2 OUT k 




-O IN 3 



-O ENABLE 2 



-O IN 4 



407 



12/86 



L293D 



ABSOLUTE MAXIMUM RATINGS 



V s 


Supply voltage 


36 


V 


Vss 


Logic supply voltage 


36 


V 


V] 


Input voltage 


7 


V 


V en 


Enable voltage 


7 


V 


lo 


Peak output current (100/is non repetitive) 


1.2 


A 


'tot 


Total power dissipation at T qround _ pins = 80 C 


5 


W 


T stg. T J 


Storage and junction temperature 


-40 to 150 


"C 



CONNECTION DIAGRAM 







KJ 






ENABLE 1 [ 


i 




16 


] V SS 


INPUT) [ 


2 




15 


J INPUT 4 


OUTPUT 1 [ 


3 




14 


] OUTPUT 4 


SND [ 


4 




13 


] GND 


GNC 


5 




12 


J GNO 


OUTPUT 2 [ 


6 




11 


J OUTPUT 3 


INPUT 2 [ 


7 




10 


] INPUT 3 


v s [ 


8 




9 


1 ENABLE 2 



THERMAL DATA 



R th j_ case Thermal resistance junction-case 



'th j-amb 



Thermal resistance junction-ambient 



max 14 
max 80 



C/W 
°C/W 



408 



L293D 



ELECTRICAL CHARACTERISTICS (For each channel, V s = 24V, V s = 5V, T amb = 25°C, 
unless otherwise specified) 



Parameter 


Test condition 


Min. 


Typ. 


Max. 


Unit 


v s 


Supply voltage (pin 8) 




Vss 




36 


V 


v« 


Logic supply voltage (pin 16} 




4.5 




36 


V 


Is 


Total quiescent supply 
current (pin 8) 


V;=L l o = V en = H 




2 


6 


mA 


V, = H l = V en = H 




16 


24 


V en =L 






4 


Iss 


Total quiescent logic supply 
current (pin 1 6) 


Vj = L l o = V en =H 




44 


60 


mA 


Vj=H l o = V en =H 




16 


22 


V en =L 




16 


24 


V|L 


Input low voltage 
(pin 2,7, 10, 15) 




-0.3 




1.5 


V 


V| H 


Input hiqh voltage 
(pin 2, 7, 10, 15) 


V ss < 7V 


2.3 




Vss 


V 


V ss > 7V 


2.3 




7 


l|L 


Low voltage input current 
{pin 2, 7, 10, 15) 


V| L = 1.5 V 






-10 


MA 


l|H 


High voltage input current 
(pin 2, 7, 10, 15) 


2.3V < V, H *( V ss -0.6V | 


30 


100 


mA 


VenL 


Enable low voltage (pin 1 , 9) 




-0.3 




1.5 


V 


V enH 


Enable high voltage (pin 1, 9) 


Vss < 7V 


2.3 




Vss 


V 


Vss > 7V 


2.3 




7 


'enL 


Low voltage enable current 
current (pin 1 , 9) 


V enL =1.5V 




-30 


-100 


MA 


'enH 


High voltage enable current 
(pin 1,91 


2.3V < V enH < V ss -0.6V 






: 10 


ma 


v CEsatH 


Source output saturation 
voltage (pins 3, 6, 1 1, 14) 


l = -0.6A 




1.4 


1.8 


V 


v CEsatL 


Sink output saturation 
vo tage (pins 3, 6, 11 , 14) 


l o = + 0.6A 




1.2 


1.8 


V 


V F 


Clamp diode forward voltage 


l = 600 mA 




1.3 




V 


t r 


Rise time (*) 


0.1 to 0.9 V Q 




250 


ns I 
i 


tf 


Fall time (*) 


0.9 to 1 V Q 




250 




ns 


1-on 


Turn-on delay (*) 


0.5 V, to 0.5 V 




750 




ns j 


t off 


Turn-off delay (*) 


0.5 V, to 0.5 V 




200 




ns 



*) See fig. 1 



409 



L293D 



TRUTH TABLE (One channel) 



INPUT 


ENABLE (*) 


OUTPUT 


H 


H 


H 


L 


H 


L 


H 


L 


Z 


L 


L 


Z 



Z = High output impedance 

("*) Relative to the considered channel 



Fig. 1 -- Switching Times 



0.5V, A/. 
/ 


'— — \ 


^. 






"o 


i 

tr 


r- 0.9V o 

NT °' 5V ° 




•f 


5-4171 


•on 


•off 



410 



^^^^^Ws> 



L294 



SWITCH-MODE SOLENOID DRIVER 



• HIGH VOLTAGE OPERATION (UP TO 50V) 

• HIGH OUTPUT CURRENT CAPABILITY 
(UP TO 4A) 

• LOW SATURATION VOLTAGE 

• TTL-COMPATIBLE INPUT 

• OUTPUT SHORT CIRCUIT PROTECTION 
(TO GROUND, TO SUPPLY AND ACROSS 
THE LOAD) 

• THERMAL SHUTDOWN 

• OVERDRIVING PROTECTION 

• LATCHED DIAGNOSTIC OUTPUT 

The L294 is a monolithic switchmode solenoid 
driver designed for fast, high-current applications 
such as hammer and needle driving in printers 



and electronic typewriters. Power dissipation is 
reduced by effecient switchmode operation. An 
extra feature of the L294 is a latched diagnostic 
output which indicates when the output is short 
circuited. 

The L294 is supplied in a 1 1 -lead Multiwatt® 
plastic power package. 



^ 



,rvl*\. V Multiwatt 11 



ORDER CODE: L294 



BLOCK DIAGRAM 



33KA j ~i.7nF 



'IH 




_p^SCURCE 
•"\_SJA0E 



\/ SINK 
"K^ STAGE 



= 2j 



pins.! 



411 



12/86 



L294 



ABSOLUTE MAXIMUM RATING 



V s 


Power supply voltage 


50 


V 


V ss 


Logic supply voltage 


7 


V 


Ven 


Enable voltage 


7 


V 


V, 


Input voltage 


7 


V 


Ip 


Peak output current (repetitive) 


4.5 


A 


Ptot 


Total power dissipation (at T case = 75°C) 


25 


W 


Tstg , Tj 


Storage and junction temperature 


-40 to 1 50 


°C 



CONNECTION DIAGRAM 

{top view) 




SINK OUTPUT 



Z^> CURRENT SENSING 
ENABLE 
TIMING 

INPUT VOLTAGE 
GND 

DIAGNOSTIC OUTPUT 
LOGIC SUPPLY VOLTAGE 
ON TIME LIMITER 
SOURCE OUTPUT 
POWER SUPPLY VOLTAGE 



Tab connected \o pin 6 



THERMAL DATA 



R th ^ case Thermal resistance junction-case 



"C/W 



412 



L294 



ELECTRICAL CHARACTERISTICS(Refer to the test circuit, V s -40V, 
unless otherwise specified). 



V«-5V, T„ mh -25°C, 



(°) After a :ime interval t max = KC 2 , the output stages are disabled, 

(°" : ) See the olock diagram. 

{■-°v) Allowec range of V SE:NS without the intervention of the short circuit protection. 



Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


V s Power supply voltage (pin 1) 


Operative condition 


12 




46 


V 


1^ Quiescent drain current (pin 1} 


V ENflBLE : H 




20 


30 


mA 


V, .,- 0,6V; V ENABLE - L 




70 




V 5S Logic supply voltage (pin 4) 




4.5 




7 


V 


l ss Quiescent logic supply current 


Vdiag= l 




5 


8 


mA 


OiAG output at nigh 
impedance 




10 


100 


WA 


Vj I nput voltage (pin 7| 


Operating output 


0.6 






V 


Non-operative output 






0.45 


lj Input current (pin 7) 


V| » 0.6V 




-1 




uf\ 


V, », 0.45V 




-3 




^ENABLE Enable input voltage (pin 9) 


Low level 


-0.3 




0.8 


V 


H igh level 


2.4 






'ENABLE Enable input current (pin 9) 


V ENABLE" L 




-100 


mA 


V ENABLE = H 




100 


lj oact /Vj Transconductance 


R s = 0.2 n V, ' 1 V 


0.95 j 1 


1.05 


A/V 


V,= 4 V 


0.97 1 


1.03 


v sat H Source output saturation 
voltage 


l p =4A 


1.7 




V 


^sat L Sink output saturation 
voltage 


l p =4A 




2 




V 


V sat H + ^sat L Total saturation voltage 


lp--4A 






4.5 


V 


'leakage Output leakage current 


R s =- 0.2.Q; Vj -, 0,45V 




1 




mA 


K On time I im iter constant r ) 


^ENABLE" L 


120 






^DIAG Diagnostic output voltage 
(pin 5) 


OIAG = 10mA 






0.4 


V 


'diag Diagnostic leakage current 
(pin 51 


V D IAG=40V 






10 


M A 


v pin 8 0P AMP and 0TA DC uolta 9 e 


V pm 10 = 100 to 800 mV 




5 






gain ('-) 
v pin 10 


V SENS Sensing voltage (pin 10) I- - ) 








0.9 


V 



413 



L294 



CIRCUIT OPERATION 

The L294 works as a transconductance amplifier: it can supply an output current directly proportional 

to an input voltage level (V,), Furthermore, it allows complete switching control of the output current 

waveform (see fig. 1 ). 

The following explanation refers to the Block Diagram, to fig. 1 and to the typical application circuit of 

fig. 2. 

The t on time is fixed by the width of the Enable input signal (TTL compatible): it is active low and 

enables the output stages "source" and "sink". At the end of t on , the load current l !oad recirculates 

through D1 and D2, allowing fast current turn-off. 

The rise time t r depends on the load characteristics, on V; and on the supply voltage value (V s , pin 1). 

During the t on time, l ioad is converter into a voltage signal by means of the externa! sensing resistance 

R s connected to pin 10. This signal, amplified by the op amp and converted by the transconductance 

amplifier OTA, charges the external RC network at pin 8 (R1, C1). The voltage at this pin is sensed by 

the inverting input of a comparator. The voltage on the non-inverting input of this one is fixed by the 

externa! voltage V: (pin 7). 

After t r , the comparator switches and the output stage "source" is switched off. The comparator output 

is confirmed by the voltage on the non-inverting input, which decreases of a constant fraction of V, 

(1/10), allowing hysteresis operation. The current in the load now flows through D1, 

Two cases are possible: the time constant of the recirculation phase is higher than R1.C1;the time 

constant is lower than R1.C1. In the first case, the voltage sensed on the non-inverting input of the 

comparator is just the value proportional to l ioad . In the second case, when the current decreases too 

quickly, the comparator senses the voltage signal stored in the R1 C1 network. 

In the first case t 1 depends on the load characteristics, while in the second case it depends only on the 

vasueof R1.C1. 

In other words, R1 C1 fixes the minimum vaiue of tj (tj > 1/10 R1 .C1 . Note that C1 should be chosen 

in the range 2.7 to 10 nF for stability reasons of the OTA). 

After t L , the comparator switches again: the output is confirmed by the voltage on the non-inverting 

input, which reaches V, again (hysteresis). 

Now the cycle starts again: t 2 , t 4 and t 6 have the same characteristics as t r , whiie t 3 and t b are similar to 

tj. The peak current l p depends on V, as shown in the typical transfer function of fig. 3. 

It can be seen that for V, lower than 450 mV the device is not operating. 

For Vi greater than 600 mV, the L294 has a transconductance of 1A/V with R s = 0.2n. For V, included 

between 450 and 600 mV, the operation is not guaranteed. 

The other parts of the device have protection and diagnostic functions. At pin 3 is connected an external 

capacitor C2, charged at constant current when the Enable is low. 

After a time interval equal to K • C2 (K is defined in the table of Electrical Characteristics and has the 

dimensions of ohms) the output stages are switched off independently by the Input signal. 

This avoids the load being driven in conduction for an excessive period of time (overdriving protection). 

The action of this protection is shown in fig. 1b. Note that the voltage ramp at pin 3 starts whenever 

the Enable signal becomes active (low state), regardless of the Input signal. To reset pin 3 and to restore 

the normal conditions, pin 9 must return high. 

This protection can be disabled by grounding pin 3. 

The thermal protection included in the L294 has a hysteresis. 

It switches off the output stages whenever the junction temperature increases too much. After a fall of 

about 20°C, the circuit starts again. 

Finally, the device is protected against any type of short circuit at the outputs: to ground, to supply and 

across the load. 

When the source stage current is higher than 5A and/or when the pin 10 voltage is higher then 1 V (i.e. 

for a sink current greater than 1 V/R s ) the output stages are switched off and the device is inhibited. 

This condition is indicated at the open-collector output DIAG (pin 5); the internal flip-flop F/F changes 

and forces the output transistor into saturation. The F/F must be supplied independently through V ss 

(pin 4). The DIAG signal is reset and the output stages are still operative by switching off the supply 

414 



L294 



CIRCUIT OPERATION (continued) 

voltage at pir. 1 and then by switching the device on again. After that, two cases are possibie: the reason 
for the "bad operation" is still present and the protection acts again; the reason has been removed and 
the device starts to work properly. 



Fig. 1 - Output current waveforms 




J". 



Fig. 2 - Test and typical 
application circuit 



'"I 



D1 : 3A fast diode | 
D2: 1A fast diode f 



trr < 200 ns 



Fig. 3 - Peak output current 
vs. input voltage 




Fig. 4 - Output saturation 
voltages vs. peak output 
current 



Fig. 5 - Safe operating areas 



3F 



Fig. 6 - Turn-off phase 




415 



L294 



CALCULATION OF THE SWITCHING TIMES 

Referring to the block diagram and to the waveforms of fig. 1, it is possible to calculate the switching 
times by means.of the following relationships. 

where: VI = V s - V^l - V^h - V R sens 



where: V2 = V s + V D1 + V D2 

Ik<Io<I p 

l is the value of the oad current at the and 

of t nn . 



L 


l "« 1 -^ 


• l P ) 


L 


, V2 




Rl 


'" V2 + R L - 


"o 



tl = t 3 -= t 5 = 



a) L |„ 09 l P - R L + V3 whe-e 

Rl I p Rl + V3 V3==V satL +V Rsens +V D1 

b) - R1 C1 In 0.9 =i -—- Rl C1 



t 2 = U ^ X 6 



Rl V1 ~I k R l 



Note that the time interval t x — t 3 — t 5 — . . . . takes the longer value between case a) and case b). The 
switching frequency is always: 



In the case a) the main regulation loop is always closed and it forces: 



l K = (0.9 ±S) l p 



where: S - 3% @ V; = 1V 
S- 1.5% <s> V, - 4V 



In the case b), the same loop is open in the recirculation phase and ! K , which is always lower than 0.9 l p , 
is obtained by means of the following relationship. 



__1 j!j=_ 
L 



V3 M 

-R L (1 - e 



ti r l 



With the typical application circuit, in the conditions V s = 40V, l p = 4A, the following switching times 
result: 



t r = 255 us 

a) 70 ms 
1 b) 16ms 



t f = 174 ms @ l = l p 
t 2 - 29 Ms 



f =- 10.2 KHz 



416 



^t^^^0» 



L295 



PRELIMINARY DATA 



DUAL SWITCH-MODE SOLENOID DRIVER 



HIGH CURRENT CAPABILITY (UP TO 
2.5A PER CHANNEL) 

HIGH VOLTAGE OPERATION (UP TO 
46V FOR POWER STAGE) 

HIGH EFFICIENCY SWITCHMODE OPERA- 
TION 

REGULATED OUTPUT CURRENT (AD- 
JUSTABLE) 

FEW EXTERNAL COMPONENTS 

SEPARATE LOGIC SUPPLY 

THERMAL PROTECTION 



levels at the inputs and can drive 2 solenoids. 
The output current is completely controlled by 
means of a switching technique allowing very 
efficient operation. Furthermore, it includes 
an enable input and dual supplies (for interfacing 
with peripherals running at a higher voltage than 
the logic). 

The L295 is particularly suitable for applications 
such as hammer driving in matrix printers, step 
motor driving and electromagnet controllers. 



The L295 is a monolithic integrated circuit in 
a 15-lead Multiwatt® package; it incorporates 
all the functions for direct interfacing between 
digital circuitry and inductive loads. The L295 is 
designed to accept standard microprocessor logic 

ABSOLUTE MAXIMUM RATINGS 




£v 



& 



Multiwatt 15 



ORDERING NUMBER: L295 



V s 




Supply voltage 


50 


V 


V w 




Logic supply voltage 


12 


V 


v FN 


, V; 


Enable and input voltage 


7 


V 


v rP , 




Reference voltage 


7 


V 


lo 




Peak output current (each channel) 










— non repetitive (t = 100 jusec) 


3 


A 






- repetitive (80% on -20% off; t on = 10 ms) 


2.5 


A 






— DC operation 


2 


A 


Ptot 




Total power dissipation (at T case = 75°C) 


25 


W 


Tstg> 


Tj 


Storage and junction temperature 


-40 to 150 


°C 



APPLICATION CIRCUIT 




jl D4 



417 



12/86 



L295 



CONNECTION DIAGRAM 

(top view) 




BLOCK DIAGRAM 



oHI-r ^ 



I 3 



_4 



Ad4 





THERMA_ 
SHUTDOWN 








.-■ 




M 7 
DRIVER 


- 






i \ 








LOG.C 




Q R 
FF2 










L2 
DRIVER 


1 







05CILLATOR 



^l^ 1 



±_±_ 



: -Gl 



THERMAL DATA 



Thermal resistance junction-case 
Thermal resistance junction-ambient 



max 3 °C/W 

max 35 °C/W 



418 



L295 



ELECTRICAL CHARACTERISTICS (Refer to the application circuit, V ss = 5V; V s = 36V; 
T = 25°C; L = low; H = high; unless otherwise specified) 



Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


V s Supply Voltage 




12 




46 


V 


V ss Logic Supply voltage 




4.75 




10 


V 


l d Quiescent drain current 
(from V s ) 


V 5 = 46V; V;^ V i2 = V EN = L 






4 


mA 


l ss Quiescent drain current 
(from V ss ) 


V ss = 10V 






46 


mA 


Vq, Vj 2 Input Voltage 


Low 


-0.3 




0.8 


V 


High 


2.2 




7 


Vein Enable Input Voltage 


Low 


-0.3 




0.8 


V 


High 


2.2 




7 


Ijl , Ij2 input Current 


v il" V i2 = L 






-100 


M A 


V :1 - V i2 - H 






10 


l EN Enable Input Current 


Ven- L 






-100 


m a 


Ven^H 






10 


V refl , Input Reference Voltage 
v ref2 




0.2 




2 


V 


l refl Input Reference Current 
'ref2 








-5 


M A 


^osc Oscillation Frequency 


C = 3.9 nF; R = 9.1 K£: 




25 




KH^ 




V ref = IV R 5 '0.5P. 


1.9 


2 


2.1 


A/V 


Vref 


V dfop Total output voltage drop 
(each channel) ( *) 


l -2A 




2.8 


3.6 


V 


V sen5 1 External sensing resistors 
v sens 2 voltage drop 






| 


2 


V 



(*' v drop- v CEsat Ql + v CEsat Q2- 



419 



L295 



APPLICATION CIRCUIT 



JD3 



it 04 



O.UjF 




L295 



13 12 11 7 6 



0.5J1]- V ref2 ^ EN ^ 



'in2 v in! 




D2, D4 = 2A High speed diodes 
D1,D3 = 1 A High speed diodes 

R1 = R2 = 2S1 
LI = L2 = 5mH 



trr «; 200 ns 



FUNCTIONAL DESCRIPTION 

The L295 incorporates two independent driver channels with separate inputs and outputs, each capable 
of driving an inductive load (see block diagram). 

The device is controlled by three microprocessor compatible digital inputs and two analog inputs. These 
inputs are: 

EN chip enable (digital input, active low), enables both channels when in the low state. 

Vini. ^in2 channel inputs (digital inputs, active high), enable each channel independently. A channel 

is activated when both EN and the appropriate channel input are active, 

V refl ,V ref2 reference voltages (analog inputs), used to program the peak oad currents. Peak load 
current is proportional to V ref . 

Since the two channels are identical, only channel one will be described. 

The following description applies also the channel two, replacing FF2 for FF1, V ref2 for V refl etc. 

When the channel is activated by a low level on the EN input and a high level on the channel input, V in2 , 

the output transistors Q1 and Q2 switch on and current flows in the load according to the exponential 

law: 

- R1 t 



L1 



where: R1 and L1 are the resistance and inductance of the load and V is the voltage available on the 
load (V s - V drop - V sense ). 



420 



L295 



The current increases until the voltage on the external sensing resistor, R S1 .reaches the reference voltage, 
V refl . This peak current, l pl , is given by: 

V rpf1 



pl ~ R 



si 



At this point the comparator output, Comp1,sets the RS flip-flop, FF1, that turns off the output 
transistor, Q1 . The load current flowing through D2, Q2, R si , decreases according to the law: 



Va 


+ I 1 r 11 A 


R1 


+ lpi) e LI R1 


V A = 


VcEsat Q2 + V se nse 1 + ^D; 



where 

If the oscillator pin (9) is connected to ground the load current falls to zero as shown in fig. 1 . 

At the time t 2 the channel 1 is disabled, by taking the inputs V inl low and/or EN high, and the output 
transistor Q2 is turned off. The load current flows through D2 and D1 according to the law: 

V F " R1t 



+ l T2 > e L1 



R1 " R1 

where V B = V s + V D1 + V D2 

l T2 = current value at the time t 2 . 

Fig. 2 in shows the current waveform obtained with an RC network connected between pin 9 and ground. 
From to t 1 the current increases as in fig. 1 . A difference exists at the time t 2 because the current starts 
to increase again. At this time a pulse is produced by the oscillator circuit that resets the flip flop, FF 1 , 
and switches on the output transistor, Q1. The current increases until the drop on the sensing resistor 
R sl is equal to V refl (t 3 ) and the cycle repeats. 

The switching frequency depends on the values of R and C, as shown in fig. 4 and must be chosen in the 
range 10 to 30 KHz. 

It is possible with external hardware to change the reference voltage V ref in order to obtain a high peak 
current l p and a lower holding current l h (see fig. 3). 

The L295 is provided with a thermal protection that switches off all the output transistors when the 
junction temperature exceeds 150°C. The presence of a hysteresis circuit makes the IC work again after 
a fall of the junction temperature of about 20°C. 

The analog input pins (V ref: , V ref2 ) can be left open or connected to V ss ; in this case the circuit works 
with an internal reference voltage of about 2.5V and the peak current in the load is fixed only by the 
value of R s : 

, - 2.5 



421 



L295 



SIGNAL WAVEFORMS 

Fig. 1 - Load current waveform with pin 9 
connected to GND. 



'0 / M, '2' \ , 

I I ' 

I I I 

1 J I I 



Fig. 2 - Load current waveform with external R-C 

network connected between pin 9 and ground. 



1 ' 


'o 


/ v 


'2 


'3 




! 5 






1 


















1 1 
1 1 








II; 




1 , 1 
1 i 


Mil 














OFF 




















ON 
OFF 


































i- 56 s; 



Fig. 3 - With V ref changed by hardware 



Fig. 4 - Switching frequency vs. 
values of R and C 





422 



^^^^^Ws 



L296 
L296P 



ADVANCE DATA 



HIGH CURRENT SWITCHING REGULATORS 



• 4A OUTPUT CURRENT 

• 5.1V TO 40V OUTPUT VOLTAGE RANGE 

• TO 100% DUTY CYCLE RANGE 

• PRECISE (±2%) ON-CHIP REFERENCE 

• SWITCHING FREQUENCY UP TO 200KHz 

• VERY HIGH EFFICIENCY (UP TO 90%) 

• VERY FEW EXTERNAL COMPONENTS 

• SOFT START 

• RESET OUTPUT 

• EXTERNAL PROGRAMMABLE LIMITING 
CURRENT (L296P) 

• CONTROL CIRCUIT FOR CROWBAR SCR 

• INPUT FOR REMOTE INHIBIT AND SYN- 
CHRONUS PWM 

• THERMAL SHUTDOWN 

The L296 and L296P are stepdown power 
switching regulators delivering 4A at a voltage 
variable from 5.1V to 40V. 

Features of the devices include soft start, remote 



inhibit, thermal protection, a reset output for 
microprocessors and a PWM comparator input 
for synchronization in multichip configurations. 

The L296P includes external programmable 
limiting current. 

The L296 and L296P are mounted in a 15-lead 
Multiwatt® plastic power package and requires 
very few external components. 

Efficient operation at switching frequencies up 
to 200KHz allows a reduction in the size and 
cost of external filter components. A voltage 
sense input and SCR drive output are provided 
for optional crowbar overvoltage protection 
with an external SCR. 



Multiwatt® 
(15-lead) 




^ 




ORDERING NUMBER: ' j 
L296 L296HT 

L296P L296PHT 



BLOCK DIAGRAM 



OSCILLATOR 



HI 




^>ii> 




— O RESET INPUT 
■ -O RESET OU1PU 1 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 



423 



12/86 



L296 
L296P 



ABSOLUTE MAXIMUM RATINGS 



v i 


Input voltage (pin 3) 




50 


V 


V|- v 2 


Input to output voltage difference 




50 


V 


v 2 


Output DC voltage 




-1 


V 




Output peak voltage at t = 0.1 ,usec f 


= 200 kHz 


-7 


V 


Vi.V 12 


Voltage at pins 1,12 




10 


V 


v 15 


Voltage at pin 1 5 




15 


V 


v 4 ,v 5 ,v 7 ,v 9 ,v 13 


Voltage at pins 4, 5, 7, 9 and 13 




5.5 


V 


v 10 , v 6 


Voltage at pins 1 and 6 




7 


V 


v 14 


Voltage at pin 14 (l 14 < 1 mA) 




v i 




"9 


Pin 9 sink current 




1 


mA 


111 


Pin 1 1 source current 




20 


mA 


>14 


Pin 14 sink current (V 14 < 5V) 




50 


mA 


Ptot 


Power dissipation at Tease <90 °C 




20 


W 


Tj . T st g 


Junction and storage temperature 




-40 to 150 


"C 



THERMAL DATA 



R th 



Thermal resistance junction-case 
Thermal resistance junction-ambient 



max 3 °C/W 

max 35 °C/W 



CONNECTION 

(top view) 



DIAGRAM 




CROWBAR DRIVE 

RESET OUTPUT 

RESET DELAY 

RESET INPUT 

OSCILLATOR 

FEEDBACK INPUT 

FREQUENCY COMPENSATION 

GROUND 

SYNC INPUT 

INHIBIT INPUT 

SOFT-START 

CURRENT LIMIT 

SUPPLY VOLTAGE 

OUTPUT 

CROWBAR INPUT 



Tab connected to pin 8 



424 



L296 
L296P 



PIN FUNCTIONS 



NAME 



FUNCTION 



CROWBAR INPUT 



Voltage sense input for crowbar overvoltage protection. 
Normally connected to the feedback input thus trig- 
gering the SCR when V out exceeds nominal by 20%. 
May also monitor the input and a voltage divider can be 
added to increase the threshold. Connected to ground 
when SCR not used. 



OUTPUT 



Regulator output. 



SUPPLY VOLTAGE 



Unregulated voltage input. An internal regulator powers 
the L296's internal logic. 



CURRENT LIMIT 



A resistor connected between this terminal and ground 
sets the current limiter threshold. 

If this terminal is left unconnected the threshold is 
internally set (see electrical charateristics). 



SOFT START 



Soft start time constant. A capacitor is connected bet- 
ween this terminal and ground to define the soft start 
time constant. This capacitor also determines the average 
short circuit output current. 



INHIBIT INPUT 



TTL — level remote inhibit, 
input disables the device. 



A logic high level on this 



SYNC INPUT 



Multiple L296s are synchronized by connecting the pin 7 
inputs together and omitting the oscillator RC network 
on all but one device. 



GROUND 



Common ground terminal. 



FREQUENCY COMPENSATION 



A series RC network connected between this terminal 
and ground determines the regulation loop gain charac- 
teristics. 



10 



FEEDBACK INPUT 



The feedback terminal of the regulation loop. The out- 
put is connected directly to this terminal for 5.1V oper- 
ation; it is connected via a divider for higher voltages. 



11 



OSCILLATOR 



A parallel RC network connected to this terminal deter- 
mines the switching frequency. This pin must be connec- 
ted to pin 7 input when the internal oscillator is used. 



425 



L296 
L296P 



PIN FUNCTIONS (continued) 



NAME 



FUNCTION 



12 



13 



14 



15 



RESET INPUT 



RESET DELAY 



RESET OUTPUT 



CROWBAR OUTPUT 



Input of the reset circuit. The threshold is roughly 5V. 
It may be connected to the feedback point or via a div- 
ider to the input. 



A capacitor connected between this terminal and ground 
determines the reset signal delay time. 



Open collector reset signal output. This output is high 
when the supply is safe. 



SCR gate drive output of the crowbar circuit. 



CIRCUIT OPERATION (refer to the block 
diagram) 

The L296 and L296P are monolithic stepdown 
switching regulators providing output voltages 
from 5.1V to 40V and delivering 4A. 

The regulation loop consists of a sawtooth oscil- 
lator, error amplifier, comparator and the output 
stage. An error signal is produced by comparing 
the output voltage with a precise 5.1V on-chip 
reference (zener zap trimmed to ± 2%). This error 
signal is then compared with the sawtooth signal 
to generate the fixed frequency pulse width 
modulated pulses which drive the output stage. 
The gain and frequency stability of the loop can 
be adjusted by an external RC network connected 
to pin 9. Closing the loop directly gives an output 
voltage of 5.1V. Higher voltages are obtained by 
inserting a voltage divider. 

Output overcurrents at switch on are prevented 
by the soft start function. The error amplifier 
output is initially clamped by the external ca- 
pacitor C ss and allowed to rise, linearly, as this 
capacitor is charged by a constant current 
source. 

Output overload protection is provided in the 
form of a current limiter. The load current is 
sensed by an internal metal resistor connected to 
a comparator. When the load current exceeds a 
preset threshold this comparator sets a flip flop 
which disables the output stage and discharges 
the soft start capacitor. A second comparator 



resets the flip flop when the voltage across the 
soft start capacitor has fallen to 0.4V. The output 
stage is thus re-enabled and the output voltage 
rises under control of the soft start network. If 
the overload condition is still present the limiter 
will trigger again when the threshold current is 
reached. The average short circuit current is 
limited to a safe value b/ the dead time introduced 
by the soft start network. 

The reset circuit generates an output signal when 
the supply voltage exceeds a threshold pro- 
grammed by an external divider. The reset signal 
is generated with a delay time programmed by an 
external capacitor. When the supply falls below 
the threshold the reset output goes low immedi- 
ately. The reset output is an open collector. 

The crowbar circuit senses the output voltage 
and the crowbar output can provide a current of 
100 mA to switch on an external SCR. This SCR 
is triggered when the output voltage exceeds the 
nominal by 20%. There is no internal connection 
between the output and crowbar sense input 
therefore the crowbar can monitor either the 
input or the output. 

A TTL - level inhibit input is provided for appli- 
cations such as remote on/off control. This input 
is activated by high logic level and disables circuit 
operation. After an inhibit the L296 restarts 
under control of the soft start network. 

The thermal overload circuit disables circuit op- 
eration when the junction temperature reaches 
about 150"C and has hysteresis to prevent un- 
stable conditions. 



426 



L296 
L296P 



CIRCUIT OPERATION (continued) 
Fig. 1 - Reset output waveforms 



OUTPUT NOW AN INTERRUPTION 

STABLE, RESET OF SUPPLY CAUSES 

GOES HIGH RESET OF MICRO 




RESET 

OUTPUT 



AT POWER DOWN 
MICRO IS INHIBITED 
/ IMMEDIATELY 



Fig. 2 - Soft start waveforms 



CLAMPED ER=0=> 




Fig. 3 - Current limiter waveforms 

i,» 



flVEPAGE 
SHORT CIRCUIT 
CUAREN7 



njtfiMMt-^Mji 



427 



L296 
L296P 



ELECTRICAL CHARACTERISTICS (Refer to the test circuits T, = 25°C, V, = 35V, unless 



otherwise specified) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Fig. 



DYNAMIC CHARACTERISTICS (pin6toGND 


unless otherwise specified) 








V Output voltage range 


Vi = 46V l Q = 1A 


Vref 




40 


V 


4 


Vi Input voltage range 


v o = v ref to36v 'o < 3A 


9 




46 


V 


4 


V] Input voltage range 


Noted) V =V REF to36V l = 4A 






46 


V 


4 


A V Q Line regulation 


^ = 10V to 40V, V Q = V ref , l = 2A 




15 


50 


mV 


4 


AV Load regulation 


Vo = V ref 


l = 2Ato4A 




10 


30 


mV 


4 


l o = 0.5Ato4A 




15 


45 


mV 


4 


V re f Internal reference 
voltage (pin 10) 


Vj =9V to 46V 
l D = 2A 


5 


5.1 


5.2 


V 


4 


AV ref Average temperature 
^ j coefficient of reference 
voltage 


Tj = 0°C to 125°C l = 2A 




0.4 




mV/°C 




V d Dropout voltage bet- 
ween pin 2 and pin 3 


l = 4A 




2 


3.2 


V 


4 


l = 2A 




1.3 


2.1 


V 


4 


l 2 [_ Current limiting 
threshold (pin 2) 


L296 pin 4 open 
V, = 9V to 40V 
V = V ref to 36V 


4.5 




7.5 


A 


4 


L296P 

V, =9V to 40V 

Vo = v ref 


pin 4 open 


5 




7 


A 


4 


R|im = 22Kn 


2.5 




4.5 


A 


4 


l S H Input average current 


Vj = 46V; Output short-circuited 




60 


100 


mA 


4 


77 Efficiency 


I . - 1& 


Vo = V ref 




75 




% 


4 




V Q = 12V 




85 




% 


4 


SVR Supply voltage ripple 
rejection 


^Vi = 2V rms Vipple = 100Hz 
V = V ref l = 2A 


50 


56 




dB 


4 


f Switching frequency 




85 


100 


115 


KHz 


4 


Af Voltage stability of ■ V; = 9V to 46V 
~^\/~ switching frequency 




0.5 




% 


4 


Af Temperature stability ! Tj = 0°C to 125°C 

A T of switching frequency ; 

a ij , 




1 




% 


4 


f max Maximum operating V Q = V ref ; ! = 1A 
switching frequency 


200 






KHz 


- 


T SC | Thermal shutdown 

junction temperature 




135 


145 




°C 


- 



DC CHARACTERISTICS 



'3(5 


Quiescent drain curr. 


V, = 46V V 7 = 0V 

51 : B 

52 : B 


V 6 = 0V 




66 


85 


mA 


6a 


V 6 = 3V 




30 


40 


mA 


6a 


-I2L 


Output leakage curr. 


V,= 46V, V 6 = 3V, S1 : B, S2 : A, Vy= 0V 






2 


mA 


6a 



Note (1 ) : Using min. 7A schottky diode 



428 



L296 
L296P 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Fig. 



SOFT START 
















i 5 so Source current 


V 6 = OV, 


V 5 = 3V 


100 


130 


160 


M A 


6b 


l 5 S | Sink current 


V 6 = 3V, 


V 5 = 3V 


50 


70 


120 


ma 


6b 



INHIBIT 



V 6 L 


Low input voltage 


V| = 9V to 46V 
V 7 = 0V 


51 : B 

52 : B 


-0.3 




0.8 


V 


6a 


V 6 H 


High input voltage 


2 




5.5 


V 


6a 


-I6L 


Input current with low 
input voltage 


V, = 9V to 46V 

V 7 = 0V 

51 : B 

52 : B 


V 6 = 0.8V 






10 


MA 


6a 


-l 6 H 


Input current with 
high input voltage 


V 6 = 2V 






3 


ma 


6a 



ERROR 


AMPLIFIER 
















V 9 H 


High level output volt. 


V 10 =4.7V, l 9 = 


100mA, S1 :A, S2:A 


3.5 






V 


6c 


V 9L 


Low level output volt. 


V 10 = 5.3V, l 9 = 


100mA, S1 :A, S2:E 






0.5 


V 


6c 


■s SI 


Sink output current 


V 10 = 5.3V, 


SI : A, S2 : B 


100 


150 




nA 


6c 


_l 9so 


Source output current 


V 10 = 4.7V, 


S1 : A, S2 : D 


100 


150 




MA 


6c 


'10 


Input bias current 


V 10 = 5.2V 


S1 : B 




2 


10 


ma 


6c 


V 10 = 6.4V, 


SI : B, L296P 




2 


10 


ma 


6c 


Gv 


DC open loop Gain 


V 9 = 1 V to 3V, 


SI : A, S2 : C 


46 


55 




dB 


6c 



OSCILLATOR AND PWM COMPARATOR 
















-l 7 Input bias current of 
PWM comparator 


V 7 = 0.5V to 3.5V 






5 


MA 


6a 


-In Oscillator source curr. 


V n = 2V, S1 


A 


S2 : B 


5 






mA 


6A 



RESET 



V 12 R 


Rising threshold 
voltage 


V, = 9V to 46V, 


S1 : B, S2 : B 


Vref 
-150mV 


Vref 
-100mV 


Vref 
-50mV 


V 


6d 


V12F 


Falling threshold 
voltage 


4.75 


Vref 
-150mV 


Vref 
-100mV 


V 


6d 


v 13 D 


Delay threshold volt. 


V 12 = 5.3V. 


S1 : A, S2 : B 


4.3 


4,5 


4.7 


V 


6d 


Vl3H 


Delay threshold 
voltage hysteresis 




100 




mV 


6d 


Vl4S 


Output saturation volt. 


I 14 = 16mA; V :2 


:4.7V; S1, S2 ; B 






0.4 


V 


6d 


>12 


Input bias current 


V 12 = 0VtoV ref , 


S1 : B, S2 : B 




1 


3 


MA 


6d 


■'l3so 


Delay source current 


V 13 = 3V 

51 : A 

52 : B 


V 12 = 5.3V 


70 


110 


140 


HA 


6d 


1 13 si 


Delay sink current 


V 12 = 4.7V 


10 






mA 


6d 


'14 


Output leakage curr. 


V, = 46V, V 12 = 5. 


JV, S1 : B, S2 : A 






100 


MA 


6d 



429 



L296 
L296P 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 



Test Condition 



Typ. 



Max. Unit 



Fig. 



CROWBAR 



Vl 


Input threshold 
voltage 


S1 : B 


5.5 


6 


6.4 


V 


6b 


Vl5 


Output saturation 
voltage 


V, =9V to 46V, 
Il5 = 5mA 


V x = 5.4V 
S1 : A 




0.2 


0.4 


V 


6b 


ll 


Input bias current 


Vj - 6V, 


S1 : B 






10 


MA 


6b 


-Il5 


Output source current 


V; = 9V to 46V, 
V 15 = 2V 


Vj = 6.5V 
S1 : B 


70 


100 




rnA 


6b 



Fig. 4 - Dynamic test circuit 

ViO- T — ■ 



1 Cl 
( * ) ^ IOuF 



RESET 

o 



CROWBAR 

Q 

1 .^ 




R3 

C3 




3 15 1 14 1 


10 
2 


11 

7 6 5 9 


(. e 



v.. 



! R2 X 15 " I ,i-, 

i ?■? !390 l 



;Schottky ; 



■^ ■!-: 



6 

INHIBIT 



C7, C8: EKR (ROE) 
L1 : L = 300mH at 8A Core type: MAGNETICS 58930 - A2 MPP 

R = 50mS2 N° turns: 43 Wire Gauge: 1 mm (18 AWG) COGEMA 946044 

(*) Minimum suggested value (10fiF) to avoid oscillations. Ripple consideration leads 
to typical value of 1000mF or higher. 

Fig. 5 - PC. board and component layout of the circuit of fig. 4(1:1 scale) 



iESEtQ Qinhibit 



CROWBAR 

O It 




G ,N D (' 



430 



Fig. 6 - DC test circuits 



L296 
L296P 



Fig. 6a 



Fig. 6b 



-0- 



&« &>- 



&, 0, 



0-, 



^0— 

J 



5 8 6 



k 



i 



I— -c&i: 



& 



r 



Fig. 6c 



Fig. 6d 



1 &. 



"1§ Y" 

— 9 oc 



-|& ^ 



#Voltm»Hr with inpul imp*d«n<:*> 50MQ 



1 -Set V 10 for V 9 = 1V 

2 - Change V 10 to obtain V 9 = 3V 
AV 9 _ 2V 



3-Gv = 



T 



1 1 







T 






1 


M^- 


3 

e 13 


• 

S2 V 6 

o^- 


12 


-L 


S 







I j. 



<af. 



AV in AVi 



431 



L296 
L296P 



Fig. 7 - Quiescent drain cur- 
rent vs. supply voltage (0% 
duty cycle - see fig. 6a) 



Fig. 8 - Quiescent drain 
current vs. supply voltage 
( 1 00% duty cycle see fig. 6a) 



30 


, , i ' M ' M 








' , | ; j 








' ' ' 








I I 




f j__, — - — : — | — ; * 






i ! 











— |-- 




J . T L_ 


n 


, : 



Fig. 9 - Quiescent drain cur- 
rent vs. junction tempera- 
ture (0% duty cycle - see 
fig. 6a) 



1» 






\ \ 
























Vj = 35V 






34 


















































30 
28 

22 








s*^ 



































































75 100 125 150 7j t'C ) 



Fig. 10 - Quiescent drain 
currentvs. junction tempera- 
ture (100% duty cycle - see 
fig. 6a) 



3Q 






I 


' 


































V| =35V 








































>-T 










--- 




















































Fig. 11 - Reference voltage 
(pin 10) vs. V, (see fig. 4) 



v r»f 




























i .:a 


















J 


















_4__ 




I 




_ 






1 t~ 




























, i. 





Fig. 12 - Reference voltage 
(pin 1 0) vs. junction tempera- 
ture (see fig. 4) 



"T> 


! ! 


5.125 






lo.JA 








^-^ 


~T~>~^. 








5.025 










i 





25 50 75 100 125 ISO T. CO 



-25 25 50 75 100 T s CC1 



Fig. 13 - Open loop fre- 
quency and phase response 
of error amplif ier(see fig. 6c) 



- _...- ... 


■ -— 


\ G v 


r\Y~ 


- — 


i i 


vj N 


\ 



Fig. 14 - Switching fre- 
quency vs. input voltage (see 
fig. 4) 







! , ° - "'" 




I I ' ' I 












I I 


-- 






I ' i 




— r ; ^~r^ _t 


--r-4— 


, 



Fig. 15 - Switching fre- 
quency vs. junction tempera- 
ture (see fig. 4) 







! 




I 










Vis 35V 
























I , 












-*" 


-' 


























j 


I 


















i I I I , i ■ I 



432 



L296 
L296P 



Fig. 16 - Switching fre- 
quency vs. R1 (see fig. 4) 




Fig. 17 - Line transient 
response (see fig. 4) 




Fig. 18 - Load transient 
response (see fig. 4) 



j . . : i. .-' «o.v,„ ~.-| 




LOAD Ci.,aHEN 


V ■ 1 
. - . j 




I j 






0„i»>jt FOLIAGE 1 .... 




^— 




I 





.. . . - , 



Fig. 19 - Supply voltage 
ripple rejection vs. fre- 
quency (see fig. 4) 




Fig. 20 - Dropout voltage 
between pin 3 and pin 2 vs. 
current at pin 2 




Fig. 21 - Dropout voltage 
between pin 3 and pin 2 vs. 
junction temperature 



15 2 25 3 .15 I; (A 





I 
















1 


i J _[ ! 




L_, 1 


^ — r~"^'?-" 


i 1 




: 






■ -j— - 


! 1 






""" 






_ _ i._, 


T ; 








! i : i 



-25 25 50 75 100 >25 



Fig. 22 - Power dissipation 
derating curve 




Fig, 23 - Power dissipation 
(device only) vs. input volt- 
age 



I \ 






o=" 




, * svwbc 




4. 


^-j- 


— 


' l "i-- 














I ! 




! C = 2A 


1 ••-Je^' 


; ^_,BV«80 










i 1 ■ ■ ■■ 1 


■ i ; i 



Fig. 24 - Power dissipation 
(device only) vs. input volt- 
age 



10 '5 20 25 3C 35 




433 



L296 
L296P 



Fig. 25 - Power dissipation 
(device only) vs. output 
voltage (see fig. 4) 




Fig. 26 - Power dissipation 
(device only) vs. output 
voltage (see fig. 4) 



1o, 


! ■ 

*= SOKtV 




I : 














Tj = 125 # C i ! 










_- 




^ 


■:1- 










MBR10t5 




—^"TnT^fl . __ 






»* 












j I 





















Fig. 27 - Voltage and cur- 
rent waveforms at pin 2 
(see fig. 4) 




Fig. 28 - Efficiency vs. 
output current 




Fig. 29 - Efficiency vs. 
output current 



DIODE MBfi'0^5 



Fig. 30 - Efficiency vs 
output voltage 




.4 i- : J 



DlODt MRR 



Fig. 31 - Current limiting 
threshold vs. R P | n 4 
(L296P only) 




Fig. 32 - Current limiting 
threshold vs. junction tem- 
perature 



-- 




i : i 

__i i 1 









t = TOO KHz | 












i : 














PIN 4 OPEN 






































T 




-■ 










= 22KJ1 














.. 




— 1" " ! - 














U296P ONW 

ill. 



Fig. 33 - Current limiting 
threshold vs. supply voltage 



7.6 10 15 20 27 



- 50 -25 25 50 75 100 




434 



L296 
L296P 



APPLICATION INFORMATION 

Fig. 34 - Typical application circuit 



o — r- 



(*), 



63V 



r^R2 

i ) 100 




C7, C8: EKR (ROE) 



?oTi c i R5 q^i 
Kn Y 2 iT c £ c 4 

l33nT P 1 




6 
INHIBIT 



(*) Minimum value UOmF) to avoid oscillations; ripple consideration leads to typical value of 1000/jF or higher 
L1 : 58930 - MPP COGEMA 946044; GUP 20 COGEMA 946045 

SUGGESTED INDUCTOR (L1) 



Core Type 


No 
Turns 


Wire 
Gauge 


Air 
Gap 


Magnetics 58930 - A2MPP 


43 


1.0 mm. 


- 


Thomson GUP 20x16x7 


65 


0.8 mm. 


1 mm. 


Siemens EC 35/1 7/10 
(B6633&-G0500-X127) 


40 


2 x 0.8 mm. 


- 


VOGT 250 mH Toroidal coil, part number 5730501800 



Resistor values for 
standard output voltages 


Vo 


R8 


R7 


12V 
15V 
18V 
24 V 


4.7 kii 
4.7 k« 
4.7 kfi 
4.7 kn 


6.2 kS2 
9.1 k« 
12 kfl 
18 kfi 



Fig. 35 - P.C. board and component layout of the circuit of fig. 34 (1:1 scale) 

resetQ Qinhibit 

CS-0192/2 



Vo O 



gndQ- 




435 



L298 
L296P 



SELECTION OF COMPONENT VALUES (See fig. 31) 



Component 


Recommended 
: Value 


Purpose 


Allow 
Min 


2d rage 
Max 


NOTES 


B1 
R2 


100 ksl 


Set input voltage 
threshold for 
reset. 




220 kn 


R1/R2- — Unin. ..-, 

If output voltage is sensed 
R1 and R2 may be limited 
and pin 12 connected to 
Pin 10. 


R3 


4.3 kn 


Sets switching 
frequency 


1 kn 


100 kn 




R4 


10 kn 


Pull-down 
resistor 




22 kn 


May be omitted and pin 6 
grounded if inhibit not used. 


R5 


15 kn 


Frequency 
compensation 


10 kn 






R6 




Collector load for 
reset output 


v c . 




Omitted if reset function 
not used. 


0.05A 


R7 
R8 


4.7 kn 


Divider to set 
output voltage 


_ 


10 kn 


V,, - v ref 

R7/R8 =—-£ J^- 1 -- 

v ref 


R lim 


— 


Sets current limit 
level 


7.5 kn 




tf R|j m is omitted and pin 4 
left open the current limit is 
internally fixed. 


C1 


10 uF 


Stability I 2.2 mF 






C2 


2.2 nf 


Sets reset delay 




Omitted if reset function 
not used. 


C3 


2.2 nF 


Sets switching 
frequency 


1 nF 


3.3 nF 




C4 


2.2 mF 


Soft start 


1 MF 




Also determines average 
short circuit current. 


C5 


33 nF 


Frequency ] 
compensation ; 




C6 


390 pF 


High frequency 
compensation 


| 


Not required for 5V 
operation 


C7.C8 
L1 


100 /jF 
300 At H 


Output filter 


100 iiH 


- 




Q1 




Crowbar 
protection 






The SCR must be able to 
withstand the peak discharge 
current of the output 
capacitor end the short 
circuit current of the device. 


D1 




Recirculation 
diode 






7A schottky or 35ns t rr 
diode, 



436 



L296 
L296P 



APPLICATION INFORMATION (continued) 

Fig. 36 - A minimal 5.1V fixed regulator. Very few components are required 

Q *iQV 10.46V 
1000/jf '50V ' iNpiJT 



7 



O 



-<. 



9. 



SHUTDOWN 



l 49>rt j 



X 



r O 

£ 220 



I 



Fig. 37 - 12V/10A Power supply 




T-(|^ 2N5038 
^-^ 3CG.UH 



2200 fa f\ 



437 



L296 
L296P 



APPLICATION INFORMATION (continued) 
Fig. 38 - Programmable power supply 




11-7 6 9 8 



I "t 33nF 

"P Una. iMol^Kn. 



300uH 







*5GS8R20 OR BYW8C 



V D = 5.1 to 15V 

l = 4A max. (min. load current = 100 mA) 

ripple < 20 mV 

load regulation (1A to 4A) = 10 mV (V = 5.1V) 

line regulation (220V ± 15% and to l = 3A) = 15 mV (V = 5.1V) 



Fig. 39 - Preregulator for distributed supplies 



v,C 






LA805 


5V/ 400 mA 
O 




J_ 




I 


14805 


5V/4«0mA 

— O 




± 






L387A 









J_ 



RESET 
OUTPUT 



(*) L2 and C2 are necessary to reduce the switching frequency spikes. 



438 



L296 
L296P 



APPLICATION INFORMATION (continued) 

Fig. 40 - In multiple supplies several L296s 
can be synchronized as shown. 



Fig. 41 - Voltage sensing for remote load 







y- 



S - 56 2 9/; 



Fig. 42 - A 5.1 V/15V/24V multiple supply. Note the synchronization of the three L296s. 




~i — r 

-T * ♦ i , plSKQ 

J27nF 43[ ^ b.z^ M 

i — r~ 



10pF 
40V 



ic :i 2 



6 15 9 



Kn,] V -»15V 



SG58R20* IOOjjFI 



xlx,,l 




rz, } - 1 ; „ 

■fBftvao-p 40v -p 47 

— -^ 



KnU V n = 24V 



juF V -— J^pr 

^33 

, ^Ls »^ ni: ^^ S-S8 2S IL 



439 



L296 
L296P 



Fig. 43 - 5.1V/2A Power supply using external limiting current resistor and crowbar protection on the 
supply voltage (L296Ponly) 





= 35v FUSE 
















Vi 


1 10 
15 4 


5.1V/2A 




O » <"' — >"> 


r 


/Yv\ 






cr: 




f 


c± 






s 5 


i 


A 


=n 








21 Kill! 





SOFT-START AND REPETITIVE 
POWER-ON 

When the device is repetitively powered-on, the 
soft-start capacitor, C&. must be discharged 
rapidly to ensure that each start is "soft". This 
can be achieved economically using the reset 
circuit, as shown in Fig. 44. 

In this circuit the divider Rj, R 2 connected to 
pin 12 determines the minimum supply voltage, 
beiow which the open collector transistor at the 
pin 14 output discharges C^. 



The approximate discharge times obtained with 
this circuit are: 



<^s 


l DIS 


2.2/iF 

4.7mF 

10mF 


2Q0,us 
300ms 
600,us i 



If these times are still too long, an external PNP 
transistor may be added, as shown in Fig. 45; 
with this circuit discharge times of a few micro- 
seconds may be obtained. 



Fig. 44 



n 



R2 



u 




Fig. 45 



K 



Css 



I_L 



1» J 



440 



L296 
L296P 



HOW TO OBTAIN BOTH RESET AND 
POWER FAIL 

Figure 46 illustrates how it is possible to obtain 
at the same time both the power fail and reset 
functions simply by adding one diode (D) and 
one resistor (R). 

In this case the reset delay time (pin 13) can only 
start when the output voltage is V > V REF - 
100mV and the voltage across R2 is higher 
than 4.5V. 

With the hysteresis resistor it is possible to fix 
the input pin 12 hysteresis in order to increase 



immunity to the 100Hz ripple present on the 
supply voltage. 

Moreover, the power fail and reset delay time 
are automatically locked to the soft start. Soft 
start and delayed reset are thus two sequential 
functions. 

The hysteresis resistor should be in the range 
of about WOKQ and the pull-up resistor of 
1 to 2.2KH. 



Fig. 46 



ViO 



PUi.L- up resistor 




*— OV =5.1V 



RESET OUT 



441 



^^^^^w® 



L297 
L297A 



STEPPER MOTOR CONTROLLERS 



• NORMAL/WAVE DRIVE 

• HALF/FULL STEP MODES 

• CLOCKWISE/ANTICLOCKWISE DIRECTION 

• SWITCHMODE LOAD CURRENT REGULA- 
TION 

• PROGRAMMABLE LOAD CURRENT 

• FEW EXTERNAL COMPONENTS 

• RESET INPUT & HOME OUTPUT 

• ENABLE INPUT 

• STEP PULSE DOUBLER (L297AONLY) 

The L297 Stepper Motor Controller IC generates 
four phase drive signals for two phase bipolar and 
four phase unipolar step motors in microcom- 
puter-controlled applications. The motor can be 
driven in half step, normal and wave drive modes 



and on-chip PWM chopper circuits permit switch- 
mode control of the current in the windings. 
A feature of this device is that it requires only 
clock, direction and mode input signals. Since 
the phase are generated internally the burden on 
the microprocessor, and the programmer, is 
greatly reduced. Mounted in a 20-pin plastic 
package, the L297 can be used with monolithic 
bridge drives such as the L298N or L293E, or 
with discrete transistors and darlingtons. The 
L297A also includes a clock pulse doubler. 




f -wy DIP-20 Plastic 

1 I f >ff (0.4) 

ORDERING NUMBERS: L297-L297A 



ABSOLUTE MAXIMUM RATINGS 



V s 

v i « 

"tot 
Tgtg. 



Supply voltage 

Input signals 

Total power dissipation (T amb = 70°C) 

Storage and junction temperature 



10 V 

7 V 

1 W 

-40 to +150 °C 



TWO PHASE BIPOLAR STEPPER MOTOR CONTROL CIRCUIT 



R si Rs2 = o.sn 

D1 to D8 - 2A Fast diodes 




443 



12/86 



L297 
L297A 



CONNECTION DIAGRAM 



SYNC 
GNO 
HOME 



1 

2 
3 


W 


20 
19 
18 


i. 




17 


5 


L297 


16 


6 




1 5 


7 




1 U 


e 




1 3 


9 




1 2 


10 




1 1 



RESET 

HALF/FULL 

CLOCK 

CW/CCW 

OSC 

Vref 
SENS 1 
SENS 2 



BLOCK DIAGRAM 



DIRECTION 
(CW/CCW) 



CLOCK CD- 



HOME o- 



r 



-* TRANSLATOR 



A INH1 B C 1NH2 D 

9OO999 



OUTPUT LOGIC 



~? 





066 

SENS 1 V ref SENS 2 



6 

OSC 



— -O CONTROL 



444 



L297 
L297A 



CONNECTION DIAGRAM 







W 




DOUBLER | 






20 


GND | 






■ 9 


HOME j 






l 8 


A 1 


- 




17 


1NH1 I 


5 


L297A 


'6 


B [ 


6 




", S 


C [ 






U 


mTz j 


8 




l 3 


D [ 


9 




' 2 


ENABLE [ 


)0 







RESET 

HALF/ FULL 

CLOCK 

CW/CCW 

OSC 

Vref 
SENS ! 
SENS 2 



BLOCK DIAGRAM 



HALF/FULL . 
STEP l 



RESET O- 



DtRECTION O'- 



CLOCK o- 



DIR-MEM O- 



1NH1 B C 1NH2 D 

o o ■■"* ^ O 



PULSE 
DOUBLER 



OUTPUT LOGIC 



OP 



FF1 ; : FF2 



^. 





DOUBLER GND 



6 6 o 6 

HOME SENS 1 V ref SENS? 



THERMAL DATA 



Thermal resistance junction-ambient 



max. 80 °C/W 



445 



L297 
L297A 



PIN FUNCTIONS - L297 



NAME 



FUNCTION 



SYNC 



Output of the on-chip chopper oscillator. 
The SYNC connections of all L297s to be synchronized 
are connected together and the oscillator components 
are omitted on all but one. If an external clock source 
is used it is injected at this terminal. 



GND 



Ground connection. 



HOME 



Open collector output that indicates when the L297 is 

in its initial state (ABCD = 0101). 

The transistor is open when this signal is active. 



Motor phase A drive signal for power stage. 



INH1 



Active low inhibit control for driver stages of A and B 
phases. When a bipolar bridge is used this signal can be 
used to ensure fast decay of load current when a winding 
is de-energized. Also used by chopper to regulate load 
current if CONTROL input is low. 



INH2 



Motor phase B drive signal for power stage. 



Motor phase C drive signal for power stage. 



Active low inhibit control for drive stages of C and D 
phases. Same functions as INH1. 



9 
10 



Motor phase D drive signal for power stage. 



11 



ENABLE 



CONTROL 



Chip enable input. When low (inactive) INH1, INH2, A, 
B, C and D are brought low. 



Control input that defines action of ch opper. 

When low chopper acts on fNH1 and INH2; when high 

chopper acts on phase lines ABCD. 



12 
13 



SENS, 



5V supply input. 



Input for load current sense voltage from power stages 
of phases C and D. 



446 



L297 
L297A 



PIN 


FUNCTIONS - 


- L297(continued) 




N° 


NAME 




FUNCTION 


14 


SENSj 




Input for load current sense voltage from power stages 
of phases A and B. 



15 



V ref 



16 



OSC 



17 



cw/ccw 



18 CLOCK 



19 HALF/FULL 



Reference voltage for chopper circuit. A voltage applied 
to this pin determines the peak load current. 



An RC network (R to V cc , C to ground) connected to 
this terminal determines the chopper rate. This terminal 
is connected to ground on all but one device in synchron 
ized multi - L297 configurations, f = 1/0.69 RC, 
R > 10 kn. 



Clockwise/counterclockwise direction control input. 
Physical direction of motor rotation also depends on 
connection of windings. 

Synchronized internally therefore direction can be 
changed at any time. 



Step clock. An active low pulse on this input advances 
the motor one increment. The step occurs on the rising 
edge of this signal. 



Half/full step select input. When high selects half step 
operation, when low selects full step operation. One- 
phase-on full step mode is obtained by selecting FULL 
when the L297's translator is at an even-numbered state. 
Two-phase-on full step mode is set by selecting FULL 
when the translator is at an odd numbered position. 
(The home position is designated state 1). 



20 



RESET 



Reset input. An active low pulse on this input restores 
the translator to the home position (state 1, ABCD = 
0101). 



447 



L297 
L297A 



PIN FUNCTIONS - L297A 

Pin function of the L297A are identical to those of the L297 except for pins 1 and 1 1. 



NAME 



FUNCTIONS 



1 DOUBLER 



An RC network connected to this pin determines the 
delay between an input clock pulse and the correspond- 
ing ghost pulse. 



11 



DIR-MEM 



Direction Memory. Inverted output of the direction 
flip flop. Open collector output. 



CIRCUIT OPERATION 

The L297(A) is intended for use with a dual bridge driver, quad darlington array or discrete power 
devices in step motor driving applications. It receives step clock, direction and mode signals from the 
systems controller (usually a microcomputer chip) and generates control signals for the power stage. 

The principal functions are a translator, which generates the motor phase sequences, and a dual PWM 
chopper circuit which regulates the cu rrent in the motor windings. The translator generates three diffe- 
rent sequences, selected by the HALF/FULL input. These are normal (two phases energised), wave drive 
(one phase energised) and half-step (alternately one phase energised/two phases energised). Two inhibit 
signals are also generated by the L297 in half step and wave drive modes. These signals, which connect 
directly to the L298's enable inputs, are intended to speed current decay when a winding is de-energised. 
When the L297 is used to drive a unipolar motor the chopper acts on these lines. 

An input ca lied C ONT ROL determines whether the chopper will act on the phase lines ABCD or the 
inhibit lines INH1 and INH2. When the phase lines are chopped the non-active phase line of each pair 
(AB or CD) is activated (rather than interrupting the line then active). In L297 + L298 configurations 
this technique reduces dissipation in the load current sense resistors. 

A common on-chip oscillator drives the dual chopper. It supplies pulses at the chopper rate which set 
the two flip-flops FF1 and FF2. When the current in a winding reaches the programmed peak value the 
voltage across the sense resistor (connected to one of the sense inputs SENSj or SENS 2 ) equals V ref and 
the corresponding comparator resets its flip flop, interrupting the drive current until the next oscillator 
pulse arrives. The peak current for both windings is programmed by a voltage divider on the V ref input. 

Ground noise problems in multiple configurations can be avoided by synchronising the chopper oscilla- 
tors. This is done by connecting all the SYNC pins together, mounting the oscillator RC network on one 
device only and grounding the OSC pin on all other devices. 

The L297A includes a pulse doubler on the step clock line which is intended to simplify the implementa- 
tion of multiple stepping. A ghost pulse is generated automatically after each input pulse, delayed by the 
time 0.75 R d C d . 

The RC network should be dimensioned to place the ghost pulse roughly halfway between clock pulses. 
If pin 1 (DOUBLER) is grounded the doubler function is disabled. 



448 



L297 
L297A 



MOTOR DRIVING PHASE SEQUENCES 

The L297's translator generates phase sequences for normal drive, wave drive and half step modes. The 
state sequences and output waveforms for thes e three modes are shown below. In all cases the trans- 
lator advances on the low to high transistion of CLOCK. 

Clockwise rotation is indicated; for anticlockwise rotation the sequences are simply reversed. RESET 
restores the translator to state 1, where ABCD = 0101 . 



Half step mode 

Half step mode is selected by a high level on the HALF/FULL input. 



era -TxinrYinrVir^ 



1001 1000 



0H0^-j_ 



0101 : 1 —| 8 •»— i 7 
HOME 0100 0110 



T_ 



U ^U L_ 



~i_r 



Normal drive mode 

Normal drive mode (also called "two-phase-on" drive) is selected by a low level on t he HA LF/ FULL 
input when the translator is at an odd numbered state (1, 3, 5 or 7). In this mode the INH1 and INH2 
outputs remain high throughout. 

1 3 5 7 13^713 57 

CL0CI 



* "innnnnnnnnrnnr 
_ i i l__^ r 



~ I I L__J L_^ L_ 



1001 ^'" , >_, 1010 

<0 

. | ( ( ( | 

oic,'f<] l\fo,c = 1 i 1 i 1 r 



449 



L297 
L297A 



MOTOR DRIVING PHASE SEQUENCES (continued) 

Wave drive mode 

Wave drive mode (also called "one-phase-on" drive) is selected by a low level on the HALF/FULL input 
when the translator is at an even numbered state (2, 4, 6 or 8). 



2 4 6 8 2 i. 6 8 2 4 6 8 

as™ TnTTTTTTTTTTT" 

_n n__r~L r 




_r~ l 



s~i 



J~~L 



j~i_ 



_ri_ 



J~L 



n_ 



_T"L 




ELECTRICAL CHARACTERISTICS (Refer to the block diagram T amb = 
otherwise specified) 


25°C, V 


s = 5V 


jnless 


Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


V s Supply voltage (pin 12) 




4.75 




7 


V 


l s Quiescent supply current 
(pin 12) 


Outputs floating 




50 


80 


mA 


Vj Input voltage 

(pins 11, 17, 18, 19, 20) 


Low 






0.8 


V 


High 


2 




V s 


V 


l| Input current 

(pin 11,17, 18, 19,20) 


V, = L 






-100 


MA 


Vi = H 






10 


ma 


V en Enable input voltage 
(pin 10) 


Low 






1.5 


V 


High 


2 




Vs. 


V 


l en Enable input current 
(pin 10) 


Ven=L 






-100 


MA 


V en =H 






10 


mA 



450 



L297A only. 



Fig. 1 



^y 



L297 
L297A 



ELECTRICAL CHARACTERISTICS (continued) 


Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


V Phase output voltage 
(pins 4, 6, 7, 9) 


l o =10mA V OL 






0.4 


V 


l = 5mA Vqh 


3.9 






V 


Vjp^ Inhibit output voltage 
(pins 5, 8) 


l - 10mA V inh L 






0.4 


V 


l = 5mA v inh H 


3.9 






V 


'leak Leakage current 
(pins 3, 11 *) 


V CE = 7V 






1 


mA 


^sat Saturation voltage 
(pins 3, 11 *S 


I = 5 mA 






0.4 


V 


Voff Comparators offset voltage 
(pins 13, 14, 15) 


V ref =1V 






5 


mV 


l b Comparator bias current 
(pins 13, 14, 151 




-100 




10 


MA 


V re f Input reference voltage 
(pin 15) 









3 


V 


t CLK Clock time 




0.5 






MS 


t s Set up time 




1 






MS 


t|_| Hold time 




4 






MS 


tp Reset time 




1 






MS 


f RCLK Reset to clock delay 




1 






MS 



cw/ccw 

HALF STEP/ 



X 



451 



L297 
L297A 



APPLICATION INFORMATION 

Two phase bipolar stepper motor control circuit 

This circuit drives bipolar stepper motors with winding currents up to 2A. The diodes are fast 2A types. 
Fig. 2 



Q5V 




CONTROL 

SYNC. 

R sl R S2 = 0.512 

D1 to D8 = 2A Fast diodes 



V F < 1.2V @ I =2A 
trr < 200 ns 



Fig. 3 - Synchronising L297s 



Fig. 4 - Pulse doubler (L297A) 







1 






1 






L297 




L297 




sv 


iv 


J' 






16 




S-S6£7 


l c 




0.6 


9 RC 



r d s 0.75 R d C d 



PULSE 

DOUBLER 

OUTPUT 



L297A 



t° 



u 



u — w 



U U LT 



452 



^^^^^^® 



L298N 



PRELIMINARY DATA 



DUAL FULL-BRIDGE DRIVER 



• POWER SUPPLY VOLTAGE UP TO 46V 

• TOTAL DC CURRENT UP TO 4A 

• LOW SATURATION VOLTAGE 

• OVERTEMPERATURE PROTECTION 

• LOGICAL "0" INPUT VOLTAGE UP TO 
1.5V (HIGH NOISE IMMUNITY) 

The L298N is an integrated monolithic circuit in 
a 15-lead Multiwatt® package. It is a high volt- 
age, high current dual full-bridge driver designed 
to accept standard TTL logic levels and drive 
inductive loads such as relays, solenoids, DC 
and stepping motors. Two inhibit inputs are 
provided to disable the device independently 

ABSOLUTE MAXIMUM RATINGS 



of the input signals. The emitters of the lower 
transistors of each bridge are connected together 
and the corresponding external terminal can be 
used for the connection of an external sensing 
resistor. An additional supply input is provided 
so that the logic works at a lower voltage. 



Multiwatt® 
i (15-lead) 




^ 




ORDERING NUMBER: 

L298N L298HN 



"o 



V 



sens 
■tot 
T s tg 



Power supply 
Logic supply voltage 
y, nh Input and inhibit voltage 

Peak output current (each channel) 
-- non repetitive (t = 100ps) 

- repetitive (80% on - 20% off; t on = 10 ms) 

— DC operation 
Sensing voltage 
Total power dissipation (T ca5e = 75°C) 



, — . . _. , > ■ cdse 

Tj Storage and junction temperature 



50 


V 


7 


V 


0.3 to 7 


V 


3 


A 


2.5 


A 


2 


A 


-1 to 2.3 


V 


25 


W 


10 to 150 


°C 



STEPPER MOTOR CONTROL CIRCUIT 



GND 


■ 


osc 




CW/CCW 


2 


6 12 


* 


CLOCK 


IS 


6 


13 


HAL!- /FULL 


19 7 

L297 

20 9 

10 b 


c 


RESET 


a 


ENABLE 


iNH-1 


.!■:" . 


15 


13 K 


1NH2 _^ 



R S1 R S2 = o.sa 



D1 ta D8 - 2A Fast diodes 



31 I DzT D3I dJ 



STEPPER 

MOTOR 

WINDINGS 



;s 1 . liii 



-r 

Del 



V F < 1.2V @ I = 2 A 
trr "5 200 ns 



1 



453 



12/86 



L298N 



CONNECTION 

(top view) 


DIAGR- 


<\M 










/ 

o- 


10 
1 9 








'-, 


CURRENT SENSING 

OUTPUT 4 




3 


OUTPUT 3 






INPUT 4 
ENABLE B 

INPUT 3 




^^ 






















3 


INPUT 2 




3 


ENABLE A 






















, 






~j 






\ 












S-5850/i 






— Tab conr 


ected to pin8 





BLOCK DIAGRAM 



OU T 1 OUT 2 



0UT3 0UT4 




6 
SENSE A 



THERMAL DATA 



n th j-case 
Rth j-amb 



Thermal resistance junction-case 
Thermal resistance junction-ambient 



max. 3 °C/W 

max. 35 °C/W 



454 



L298N 



Fig. 1 - Switching times test circuits 



Fig. 1a - Source Current Delay Times vs. Input or 
Enable Chopper. 



V SS= 5V V S --42V 




Note: For INPUT chopper, set EN = H 



I4V) ^ y- 



Fig. 2 - Switching times test circuits 



Fig. 2a - Sink Current Delay Times vs. Input or 
Enable Chopper. 



v ss=sv V S= 42V 

O 9 




Note: For INPUT chopper, set EN = H 



' L t 



ax(2A) -I— 
90-/. -I — 



50 7. J-/-- 



Y 



455 



L298N 



ELECTRICAL CHARACTERISTICS (for each channel, V s = 42V, V ss == 5V, T, = 25°C) 



Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


V s Supply voltage (pin 4) * 


Operative condition 


V,h+2.5 




46 


V 


V ss Logic supply voltage (pin 9) * 




4.5 




7 


V 


l s Quiescent supply current 
(pin 4) 


V inh =H V;=L 




3 


7 


mA 


V; = H 




15 


20 


Vinh = L 






1 


l ss Quiescent current from V ss 
(pin 9) 


V inh =H V;=L 

ii - n 




5 


10 


mA 


V; = H 




1.5 


3 


Vinh=L 




1 


1.5 


Vj (_ Input low voltage 
(pins5, 7, 10, 12) 




-0.3 




1.5 


V 


Vj h Input high voltage 
(pins5, 7, 10, 12) 




2.3 




V S s 


lj L Low voltage input current 
(pins5, 7, 10, 12) 


V, = L 






-10 


MA 


lj H High voltage input current 
(pins5, 7, 10, 12) 


V, = H < V s5 - 0.6V 




30 


100 


^inh L Inhibit low voltage 
(pins 6, 11) 




-0.3 




1.5 


V 


V jnh H Inhibit high voltage 
(pins 6, 11) 




2.3 




Vss 


I -, n h |__ Low voltage inhibit current 
(pins 6, 11) 


Vinh=L 






-10 


MA 


'inn H High voltage inhibit current 
(pins6, 11) 


Vinh = H<V ss -0.6V 




30 


100 


V CE sat(H) Source saturation voltage 


l L = 1A 




1.2 


1.8 


V 


l L = 2A 




1.8 


2.8 


^CE sat(L) Sink saturation voltage 


I L = 1 A 




1.2 


1.8 


V 


l L = 2A 




1.7 


2.6 


V CE sat Total dr °P 


l L = 1A 






3.4 


V 


l L = 2A 






5.2 


^sens Sensing voltage (pins 1 , 15) 




-1 1 " 




2 


V 


Tj (Vj) Source current turn off delay 


0.5 V, to 0.9 l L <2) 




1.7 




jUS 


T 2 (Vj) Source current fall time 


0.9 l L to 0.1 l L <2) 




0.2 




MS 


7" 3 (Vj) Source current turn-on delay 


0.5 V; to 0.1 l L <2) 




2.5 




MS 



456 



L298N 



ELECTRICAL CHARACTERISTICS (continued) 


Parameter 


Test conditions 


Min. 


Typ. 


Max 


Unit 


T4 (Vj) Source current rise time 


0.1 I L to 0.9 l L l2 ' 




0.35 




MS 
MS 


T5 (Vj) Sink current turn-off delay 


0.5 Vj to0.9l L <3) 




0.7 




Tg (Vj) Sink current fall time 


0.9 I ,_ to 0.1 l L (3) 




0.2 




MS 


T 7 (Vj) Sink current turn-on delay 


0.5 Vj to 0.1 l L (3 ' 




1.5 




MS 


Tg (Vj) Sink current rise time 


0.1 I L to 0.9 l L (3 ' 




0.2 




MS 


f c Commutation frequency 


l L = 2A 




25 


40 


KHz 



1) Sensing voltage can be - 1 V for t < 50 Msec; in steady state V sens min > -0.5V. 

2) See fig. 1a. 

3) See fig. 2a. 

* The correct sequence for power-on, is: 1 . V 5S on with EN = L - 2. V son - 3. EN = H 
and for power-off 1.EN=L - 2. V soff - 3. V ssoff 



Fig. 4 - Bidirectional DC motor control 



• v 5 
O- 



T0 CONTROL 
CIRCUIT 




1 



31 TO 04 1A HIGH-SPEED DIODE 



INPUTS 


FUNCTION 


Vjnh=H 


C = H; 


D = 


L 


Turn right 


C = L; 


D = 


H 


Turn left 


C = D 


Fast motor stop 


Vjnh= L 


C= X; 


D = 


C 


Free running 
motor stop 



H = High 



X = Don't care 



457 



L298N 



Fig. 5 - Two phase bipolar stepper motor control circuit {winding currents up to 2A) 

Q36V 



33nF _ 
GndT" "1 



cw/ccv* 

CLOCK. 



RESET 

ENABLE 



2 16 12 



)i I 

I 



Z\ D3\ Di. 

* * * 



STEPPER 
MOTOR 



R S1 R S2 =■ 0.512 

D1 to D8 - 2A Fast diodes 



V F < 1.2V @ I = 2A 
trr < 200 ns 



1 -J 



■* ; 1 WINDING 

i ^ 

_, _. „; Dal 

nil 



DSi D6 07 



Fig. 6 - Suggested printed circuit board layout for the circuit of fig. 5(1:1 scale) 



z>OzoJj < S s £z 



99999???? 



0,1/uF 




( ) 














I __ 


j 



01 O- 

GND O 



— © 



® 



@~ 



-1 © © ® ® 



220ajF 50V 



6 6 6 6 6 

02 03 04 Vct&ND 



CS-0204/1 



458 



^^^^^^^F® 



L387A 



ADVANCE DATA 



VERY LOW DROP 5V REGULATOR 



• PRECISE OUTPUT VOLTAGE (5V± 4%) 

• VERY LOW DROPOUT VOLTAGE 

• OUTPUT CURRENT IN EXCESS OF 500mA 

• POWER-ON, POWER-OFF INFORMATION 
(RESET FUNCTION) 

• HIGH NOISE IMMUNITY ON RESET 
DELAY CAPACITOR 

The L387A is a very low drop voltage regulator 
in a Pentawatt® package specially designed to 
provide stabilized 5V supplies in consumer and 
industrial applications. Thanks to its very low 
input/output voltage drop this device is very 
useful in battery powered equipment, reducing 
consumption and prolonging battery life. A reset 



output makes the L387A particularly suitable for 
microprocessor systems. This output provide a 
reset pulse when power is applied (after an ex- 
ternal programmable delay) and goes low when 
power is removed, inhibiting the microprocessor. 
An hysteresis on reset delay capacitor raises 
the immunity to the ground noise. 




Pentawatt® 



ORDERING NUMBER: L387A 



ABSOLUTE MAXIMUM RATINGS 



v, 


Forward input voltage 


35 


V 


V, 


Reverse input voltage 


-18 


V 


' op 


Operating junction temperature 


-40 to +125 


u c 


Ttfg 


Storage temperature 


-55 to +150 


°C 



TEST CIRCUIT 



inO- 



~100nF 



-!E C 



1 5 

L387A 

<- 3 2 



X 



OUTPUT 
VOLTAGE 
0+5V 



n — ^ 

L ! "TToOuF * 

-«-Q -J- 

RESET 

OUTPUT 



S-589B/1 



* Min 33/jF and max. ESR < 3fi over temperature range 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

459 12/86 



L387 A 



CONNECTION DIAGRAM 

(Top view) 




♦"OUT 

> DELAY CAPACITOR (Cd) 

GROUND 

> RESET OUTPUT 

♦ V IN 



(tab connected to pin 3 



BLOCK DIAGRAM 



INPUT 



PNP OUTPUT 
TRANSISTOR 




. DELAY 
40 CAPACITOR 



THERMAL DATA 



Rthj-case Thermal resistance junction-case 



C/W 



460 



L387A 



ELECTRICAL CHARACTERISTICS (Refer to the test circuit, V ( 
otherwise specified) 



14.4 T, = 25 C, unless 



Parameter 


Test: Conditions 


Min. 


Typ. 


Max. 


Unit 


Vo 


Output voltage 


l = 5mA to 500mA 


4.80 


5 


5.20 


V 


V| 


Operating input voltage 


(*) 






26 


V 


AV 


Line regulation 


V; = 6V to 26V 


l = 5mA 




5 


50 


mV 


AV 


Load regulation 


l = 5mA to 500mA 




15 


60 


mV 


V]-V 


Dropout voltage 


l = 500mA 






0.60 


0.8 


V 


'q 


Quiescent current 




l = 5mA 
l = 150mA 
l„ = 350mA 
l = 500mA 




5 

20 
60 
100 


15 
35 
100 
160 


mA 


V, = 6.2V 


l = 500mA 




160 


180 


AVp 

AT 


Temperature output 
voltage drift 






-0.5 




mV/°C 


SVR 


Supply voltage rejection 


l = 350mA 
C = 100mF 


f = 120Hz 

V,= 12V ± 5Vpp 




60 




dB 


Isc 


Output short circuit 
current 






0.8 


1.5 


A 


v R 


Reset output voltage 


l R = 16mA 


V < 4.75V 






0.8 


V 


>R 


Reset output leakage 
current 


V in regulation 






50 


MA 


td 


Delay time for reset 
output 


Cd = 100nF 






30 




ms 


V RT(off) 


Reset threshold (delay 
charging current on) 




4.75 


V o -0.15 


V o -0.04 


V 


>C4 


Charging current 
(current generator) 


V 4 = 3V 


10 




30 


M A 


v RT(on) 


Reset threshold (low) 






V RT(off) 
-10mV 




V 


v 4 


Comparator threshold 
(pin 4) 


Reset out = "0" 


3.2 




3.9 


V 


Reset out = "1" 


3.7 




4.3 


V 


v H 


Hysteresis voltage 






500 




mV 



(*) For a DC voltage 26 < V, < 35V the device is not operating 



461 



L387A 



Fig. 1 - Dropout Voltage 
vs. output current 



Fig. 2 - Quiescent current 
vs. output current 



Fig. 3 - Output voltage vs. 
temperature 



'l^ 



^Tr 



462 



-^dd 



100 L'OO 300 400 i Q . 



100 Z°0 300 400 l (m 






20 40 SO 80 100 I I: CC) 



SGS 



L601 L603 
L602 L604 



DARLINGTON ARRAYS 

• EIGHT DARLINGTONS PER PACKAGE 

• OUTPUT CURRENT 400mA PER DRIVER 
(500mA PEAK) 

• OUTPUT VOLTAGE 90V (V CE(sus , = 70V) 

• INTEGRAL SUPPRESSION DIODES FOR 
INDUCTIVE LOADS 

• OUTPUTS CAN BE PARALLELED FOR 
HIGHER CURRENT 

• TTL / CMOS / PMOS / DTL COMPATIBLE 
INPUTS 

• INPUTS PINNED OPPOSITE OUTPUTS TO 
SIMPLIFY LAYOUT 

The L601, L602, L603 and L604 are high volt- 
age, high current darlington arrays each contain- 
ing eight open collector darlington pairs with 
common emitters. Each channel is rated at 400 
mA and can withstand peak currents of 500mA. 
Suppression diodes are included for inductive 
load driving and the inputs are pinned opposite 
the outputs to simplify board layout. 



The four versions interface to all common logic 
families : 



L601 


General purpose 


L602 


14-25V PMOS 


L603 


5V TTL, CMOS 


L604 


6 - 15V CMOS, PMOS 



These versatile devices are useful for driving a 
wide range of loads, including solenoids, relays 
DC motors, LED dispalys, filament lamps, thermal 
printheads and high power buffers. 

The L601, L602, L603 and L604 are supplied 
in 18 pin plastic DIP packages with a copper 
leadframe to reduce thermal resistance. 



^^ry 



DIP-18 Plastic 

(U7P2) 



ORDERING NUMBERS: L601B, L603B 
L602B, L604B 



ABSOLUTE MAXIMUM RATINGS 



VcEX 


Collector emitter voltage (input open) 


90 


V 


lc 


Collector current 


0.4 


A 


lc 


Collector peak current 


0.5 


A 


V, 


Input voltage (for L602, L603 and L604) 


30 


V 


li 


Input current (for L601 only) 


25 


mA 


"tot 


Total power dissipation a T amb = 25°C 


1.8 


W 


1 op 


Operating junction temperature 


-25 to 150 


"C 


' stg 


Storage temperature 


-55 to 150 


°c 



SCHEMATIC DIAGRAM (L601 - One darlington only) 



inO — f- 



< 



EACH DRIVER 



< 



-X OCOM 



-J OOUT 



--- i 



463 



12/86 



L601 L603 
L602 L604 



CONNECTION DIAGRAM 

(top view) 




| 10 COMMON FREE 
WHEELING DIODES 



SCHEMATIC DIAGRAMS 



L601 



L602 



NO f 




EACH DRIVER 



-Pt—O COM 



I0.5kn ^— 4-- ♦ -O0UT 

vO t »■' >t I,' ) 

7.2kn i 3kC * 

■ i. >-i L_ 1— I 



- » 

EACH DRIVER 



L603 



L604 



2.7kn / 

iNo- r o-i — K, 



T -- < 



7.2kfl ; 3k0 



-j T -O0UT 



i4 

EACH DRIVER 



-c 



7.2kQ 3kH 




^ — -OOUT 



EACH DRIVER 



464 



L601 L603 
L602 L604 



THERMAL DATA 



R th 



Thermal resistance junction-ambient 



max 70 °C/W 



ELECTRICAL CHARACTERISTICS^ 



■ 25°C, unless otherwise specified) 



Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


'cex Output leakage current 


V CE = 90V 






10 


M A 


V C £ (sat ) Collector emitter saturation 
voltage 


l c = 300 mA I b =500(jA 
I c = 200 mA l B =350/iA 
l c = 100 mA ! B = 250 mA 






2 

1.7 
1.2 


V 
V 
V 


h FE DC forward current gain 
(L601 only) 


V CE =3V I c = 300 mA 


1000 






— 


Vj Minimum input voltage 
(ON condition) 


V CE =3V l c =30*0mA 
for L602 
for L603 
for L604 






11.5 
2.5 
2.5 


V 
V 
V 


Vj Maximum input voltage 
(OFF condition) 


V CE = 90V l c =25 M A 
for L601 
for L602 
for L603 
for L604 


0.55 

7 
0.75 

1 






V 
V 
V 
V 


I R Clamp diode reverse current 


V R = 90V 






50 


ma 


V F Clamp diode forward voltage 


l F = 300 mA 




2 


2.4 


V 


t on Turn-on delay 


0.5 Vj to 0.5 V 




0.4 




MS 


t off Turn-off delay 


0.5 Vj to 0.5 V 




0.4 




MS 



465 



^^^^^^® 



L702 



PRELIMINARY DATA 



2A QUAD DARLINGTON SWITCH 



• SUSTAINING VOLTAGE: 70V 

• 2A OUTPUT 

• HIGH CURRENT GAIN 

• IDEAL FOR DRIVING SOLENOIDS, DC 
MOTORS, STEPPER MOTORS, RELAYS, 
DISPLAYS, ETC. 

The L702 is a monolithic integrated circuit for 
high current and high voltage switching applica- 
tions it comprises four darlington transistors 
with common emitter and open collector suitable 
for current sinking applications mounted on the 
new POWERDIP and Multiwatt® packages. 
This circuit reduces components, sizes and costs; 
it can provide direct interface between low level 
logic and a variety of high current applications. 




Multiwatt-11 



\f 



Powerdip 8 + 8 

(V6P2) 



ORDERING NUMBER: L702B - Powerdip 
L702N - Multiwatt 



ABSOLUTE 


MAXIMUM RATINGS 












VcEX 


Collector-emitter voltage (input open) 








90 


V 


V i 


Input voltage 








30 


V 


lc 


Collector current 








3 


A 


Ptot 


Total power dissipation at T pin 9 to 16 < 90°C \ 
Total power dissipation at T amb < 70°C > 


Powerdip 






4 


W 








1.1 


W 




Total power dissipation at T ca5e < 90 C C 


Multiwatt 






20 


W 


T s tg 


Storage temperature 




-55 


to 


150 


°C 


Tj 


Operating junction temperature 




-25 


to 


150 


°C 



Stepping motor buffer 



J r 


l702b; n : 3 








*z< 








— 


f- ■ 




-^ ■— ■ 








-^ 


: **\ '' 


T 










-^ 






-*■ •+• 5 








— «s 


_ 




. »,,,- 


6 






■■>HT ■■■•'■ 


__ 


_ 




^r-fr 









4; 



467 



12/86 



L702 



CONNECTION DIAGRAMS (top view) 




/ 


i 


— ~^w 


n 

w 

9 
9 
7 
6 
5 
4 
3 
2 
1 




/ 


II ~> Bl 




II 1»! 
















r 


>l 






K 


J 


















II ~J nr 




II im 




\ 




\_ 


i 





THE TAB IS CONNECTED TO PIN 6 



Powerdip 



Multiwatt 



SCHEMATIC DIAGRAM (each Darlington) 




♦ OGND 



THERMAL DATA 



^th j-amB Thermal resistance junction ambient 

^th i-pins 9/16 Thermal resistance junction pins 9 to 16 
^tn i-case Thermal resistance junction-case 



Powerdip 

Multiwatt 



max 


70 


°C/W 


max 


14 


°c/w 


max 


3 


°c/w 



468 



L702 



ELECTRICAL CHARACTERISTICS (T case = 25°C unless otherwise specified) 


Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


'cex Output leakage current 


V ce =90V 




10 


50 


M A 


Vce (sust) Collector emitter (°) sustaining 
voltage 


l c = 100 mA 


70 






V 


V C £ ( sat j Collector emitter saturation 
voltage 


l c =1.25A 
1; = 2mA 




1.3 


1.9 


V 


hpr£ DC forward current gain 


l c = 1A 
V CE =3V 


1000 


4000 






1 , Input current 


V, = 3.75V 
Vj = 2.4V 
open collector 




7 
3 


11 
6 


mA 
mA 


Vj Input voltage off condition 


V CE =70V l c «;0.1 mA 






0.4 


V 


on condition 


V CE = 3V \ c > 1A 


2.4 






V 


t on Turn on time 


V, = 12V 

R L = 1 o n 




0.3 




MS 


t ff Turn off time 




1 




MS 



(°) Pulsed: pulse duration = 300 i±s, duty cycle = 1 .5%. 



Fig. 1 - Switching time 



\ 



Fig. 2 - t on and t off test circuit 



v,0 




Ov . 



JU U^' 



Fig. 3 - Peak collector cur- 
rent vs. duty cycle and num- 
ber of outputs! L702B only) 





















III 
















r amb =7o°c 

r = 100ms 








l\\ \ 












{ 














"v 
























'" fl 








































..- 


- 






































i 






- ■;---.-+- 


























































■ 






4--L-I- 




















3 


=^- 


















4-. l-M- 
















.(... i._ 








































i I ! 














, i 









10*/. 307. 507. 70V. 0(7. 



469 



L702 



Fig. 4 - Collector emitter 
saturation voltage vs. col- 
lector current 



- 












."J 
















00 










4 








JS 


E- 




















































































































- 


■- 































Fig. 5 - Collector current 
vs. input voltage 




Fig. 6 - Input current vs. 
input voltage 



(mA) 








XI 




\ 


1 
.1 




- 






- 
























bL 




























40 






1 ■ 








- 




- 
























JU 






^l 




























'" 






A^~ 




















10 






















\Y 




. i 


i 

















Fig. 7 - Safe operating areas 
(L702B) 



Fig. 8 - Safe operating areas 






(L" 


r02N 


«=-- + 1 ; !-. 


It ■ tVth 


A) 6 




SINGLE PUL5E ''V'^ 


"FlJfl 












ioc; 






" 




.--' ' 






ETT. 1 - : -23 












o' 




f 


n4n 


_ - t • H" 




— ■ ■■ * --j-*- 










l ; 






- 






. ! i 


_ 2 




: , 1 1 





Fig. 9 - DC current gain vs. 
collector current i 



i0< V CE (V) 




(») Pulse width = 300 (JS.duty cycle 1 .5%. 



470 



^^^^^^^r® 



L2720 
L2722 



ADVANCE DATA 



LOW DROP DUAL POWER OPERATIONAL AMPLIFIERS 



OUTPUT CURRENT TO 1A 
OPERATES AT LOW VOLTAGES 
SINGLE OR SPLIT SUPPLY 
LARGE COMMON-MODE AND DIFFER- 
ENTIAL MODE RANGE 
LOW INPUT OFFSET VOLTAGE 
GROUND COMPATIBLE INPUTS 
LOW SATURATION VOLTAGE 
THERMAL SHUTDOWN 



The L2720 and L2722 are monolithic inte- 
grated circuits in powerdip and minidip packages, 
intended for use as power operational amplifiers 
in a wide range of applications including servo 
amplifiers and power supplies. They are par- 



ticularly indicated for driving, inductive loads, 
as motor and finds applications in compact-disc, 
VCR automotive, etc. 

The high gain and high output power capability 
provide superior performance whatever an opera- 
tional amplifier/power booster combination is 
required. 



^ V 



Powerdip 8 + 8 



Minidip Plastic 



ORDERING NUMBERS: 

L2720 L2722 



ABSOLUTE MAXIMUM RATINGS 



v s 


Supply voltage 




28 


V 


v s 


Peak supply voltage (50ms) 




50 


V 


v, 


Input voltage 




V s 




v. 


Differential input voltage 




±v s 




lo 


DC output current 




1 


A 


Ip 


Peak output current (non repetitive) 




1.5 


A 


Ptot 


Power dissipation at T amb = 80°C (L2720), T amb = 


= 50°C (L2722) 


1 


W 




Tease = 75°C (L2720) 




5 


W 


T stg< T J 


Storage and junction temperature 




-40 to 150 


U C 



BLOCK DIAGRAMS 





L2720 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to Chan 

471 



without notice. 

12/86 



L2720 
L2722 



CONNECTION DIAGRAMS 

(Top view) 







W 




OUTPUT 1 | 


1 




16 


Vs 1 


2 




15 


OUTPUT 2 | 


3 




K 


GND 1 


- 




13 


INPUT- 2 1 


5 




12 


INPUT. 2 | 


6 




1 1 


INPUT.) 1 


7 




10 


INPUT -1 [ 


e 




9 



JGND 

]gnd 
]gnd 
]gnd 
]gnd 
|gnd 
Ignd 
Ignd 




L2722 



L2720 

SCHEMATIC DIAGRAM (one only) 




)0pF 

HH 



DUMP 
PROTEC 



< 



THERMAL 
PROTECTION 




-O 



THERMAL DATA 




Powerdip 


Minidip 


Rthj-case Thermal resistance junction-pins 
^thj-amb Thermal resistance junction-ambient 


max 
max 


15°C/W 
70° CAW 


*70°CAV 
100° CAW 



Thermal resistance junction-pin 4 



472 



L2720 
L2722 



ELECTRICAL CHARACTERISTICS (V s == 24V, T amB = 25°C unless otherwise specified) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


v s 


Single supply voltage 




4 




28 


V 


Vs 


Split supply voltage 




± 2 




- 14 


l s Quiescent drain current 


vf 


V s = 24V 




10 


15 


mA 


V s = 8V 




9 


15 


ib 


Input bias current 






0.2 


1 


MA 


Vos 


Input offset voltage 








15 


mV 


los 


Input offset current 






10 


50 


nA 


SR 


Slew rate 






2 




V/ms 


B 


Gain-bandwidth product 






1.2 




MHz 


Ri 


Input resistance 




500 






K« 


G v 


O.L. voltage gain 


f = 100Hz 


70 


80 




dB 


f = 1KHz 




60 




e N 


Input noise voltage 


B = 22Hz to 22KHz 




10 




M V 


In 


Input noise current 




200 




PA 


CMR 


Common Mode rejection 


f = 1KHz 


66 


84 




dB 


SVR 


Supply voitage rejection 


f = 100Hz V 5 = 24V 
R G = 10KJ2 V s = ±12V 
V R = 0.5V V s = ± 6V 


54 


70 
75 
81 




dB 
dB 
dB 


v DROP (HIGH) 


V s = ±2.5V to ± 12V 


lp = 100mA 




0.7 




V 


lp = 500mA 




1.0 


1.5 


V DROP (LOW) 


lp = 100mA 




0.3 




V 


lp = 500mA 




0.5 


1.0 


Cs 


Channel separation 


f = 1KHz; R L = 10n; G v = 30dB 
V s - 24V 
V s = ±6V 




60 
60 




dB 
dB 


Tsd 


Thermal shutdown 
junction temperature 






145 




°C 



473 



L2720 
L2722 



Fig. 1 - Quiescent current 
vs. supply voltage 






Fig. 2 - Open loop gain vs. 
frequency 






Fig. 3 - Open loop voltage 
gain 



1? 16 20 24 V S (V! 



10 3 10' 10 5 




Fig. 4 - Output swing vs. 
load current (V s = ± 5V) 













I 


































































































■JiL 


JATIW 


E 














POSl 


lVE 




J^ 































































Fig. 5 - Output swing vs. 
load current (V. = ± 12V) 





i 








: 




i 


























H 






T"SS^ 


- 














- 



200 400 600 li(W mA > 



Fig. 6 - Supply voltage 
rejection vs. frequency 



- 






1 
























12V 






































































1 . 
























































1 














- 





















































































Fig. 7 - Channel separation 
vs. frequency 



I i |G».»de| j ; : j 



474 



L2720 
L2722 



APPLICATION SUGGESTION 

In order to avoid possible instability occurring 
into final stage the usual suggestions for the 
linear power stages are useful, as for instance: 

— layout accuracy; 



A 100nF capacitor corrected between supply 
pins and ground; 

boucherot cell (0.1 to 0.2/nF +1ft series) bet- 
ween outputs and ground or across the load. 



Fig. 8 - Bidirectional DC motor control with /uP compatible inputs 




<=>- 



«s2 

? 



-,e 2 V S1 = logic supply voltage 
Must be V S2 > V S1 
E1, E2 = logic inputs 



Fig. 9 - Servocontrol for compact-disc 



REFLECTED k 

BEAM ) 




Fig. 10 - Compact-disc motor driver (1 12 section 




475 



L2720 
L2722 



Fig. 1 1 - Capstan motor control in video recorders 




x° 



Fig. 12 - Motor current control circuit 




R^ R8 

■3K0 1 13KQJ_ 
•'• 27. 



IOKQ 27. 



36 KQ 2.SKQ 

*<I7. i-5»30ll 

Note: The input voltage level is compatible with L291 (5-BIT D/A converter) 



Fig. 13 - Bidirectional speed control of DC motors. 

o □ O o pi 

For circuit stability ensure that R x > where R M = internal resistance of motor. The voltage 

V 2R ; R1 
available at the terminals of the motor is V M = 2 ( V, — ) + |RJ. I M where |R ! = and 

l M is the motor current. 




476 



Fig. 14 - VHS-VCR Motor control circuit 



L2720 
L2722 



UP 

Z8 



de: 

L293 



ft 



B-BIT 
OAC 
OBOB 



3 

3 



LOADING MOTOR 
CASSETTE MOTOR 



L2720 



(TT\ CAPSTAN 
VV MOTOR 



B-BIT 
> DAC — | 
; 0808 

I 



L2720 



UP 

INTER 
FACE 

TDA 
8114 



r-«P- 

-® 

n 



DRUM 
MOTOR 



CAPSTAN TACHO 



DRUM POSITION 



REC.PB 
REEL TACHO 



RIGHT 

LEFT 



kio 



VHS2: : DIS 



All 



^^^^^^® 



L3654S 



PRELIMINARY DATA 



PRINTER SOLENOID DRIVER 

The L3654S is a printer solenoid driver containing 
ten open-collector driver outputs and a ten-bit 
serial-in, parallel-out register. 

Data is clocked into the shift register serially 
and transferred to the open-collector outputs 
by an enable input. Serial input data is loaded 
by the rising edge of the clock. A serial output 
from the tenth bit is provided which changes 
at the falling edge of the clock. This output is 
not controlled by the enable input and remains 
active at all time. 

The L3654S is pin to pin compatible with the stan- 
dard L3654, but can work with V s down to 4.75V. 

Each output is rated at 250mA (sink) and is 



clamped to ground internally at 50V to dissipate 
stored energy in inductive loads. 

The L3654S is supplied in a 16 lead dual in-line 
plastic package, and its main fields of applica- 
tion comprise thermal printers, cash registers 
and printing pocket calculators. 




DIP-16 Plastic 

(0.25) 



ORDERING NUMBER: L3654S 



ABSOLUTE MAXIMUM RATINGS 



V s 


Supply voltage 


9.5 


V 


v i 


Input voltage 


9.5 


V 


V E 


External supply voltage 


45 


V 


lo 


Output current (single output) 


0.4 


A 


'g 


Ground current 


4.0 


A 


■tot 


Total power dissipation (T amb = 70°C) 


1 


W 


T stg , Tj 


Storage and junction temperature 


-65 to 150 


°C 



BLOCK DIAGRAM 



v output' h\o 

EN ENABLE U LX^ 


1 2 3 A 5 6 7 

1 Q C' O O O O C) r 

"T^W^.. . l 1 Mh 3 jj4 15 J2 [3 


D C 


1 

4 



? 
6 


V S 
SENS 

% R, A P T U A T £-[>> 
V C L 4 L P°U C T K O^ 


— 1 J>>- d o-i- D Q — *— D a — — 

U^ CLOCK CLOCK CLOCK 


to 

-i D Q - 

CLOCK 

[ 10 








1 1 

1 D 

CLK O- 






'_. - 5 1 3 ■■ ! 


^ OUTPL 


T 



479 



12/86 



L3654S 



CONNECTION 


DIAGRAM 






(top view) 










V^ 




OUTPUT ENABLE 1 | 






OUTPUT 6 


2 I 






OUTPUT 7 


3 I 






OUTPUT 8 


a[ 






OUTPUT 9 


5 I 






OUTPUT10 


6 [ 






DATA OUTPUT 


7 [ 






GND 


8 I 





16 V s 

15 OUTPUT 5 

14 OUTPUT 4 

13 OUTPUT 3 

12 OUTPUT 2 

11 OUTPUT 1 

10 DATA INPUT 

9 CLOCK 



Fig. 1 - Timing diagram 



'EN CLK 'CLK <CLK ' BIT 



--H 



* SET-UP^.j, 1 HOLD 



XZOCDC 



-fS- 



<CLK EN 



ri 



Vdo 



m 



THERMAL DATA 



Rth i-amb Thermal resistance junction-ambient 



max 80 °C/W 



480 



L3654S 



ELECTRICAL CHARACTERISTICS (V 5 = 5V, V E = 30V, T amb = 0° to 70°C, unless otherwise 
specified) 



Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


Vs 


Supply voltage 




4.75 




9.5 


V 


Is 


Suppiy current 


T amo" 25 C 
V 5 = 9.5V 


V EN =0V; V DO =0V 




27 


40 


mA 


V EN = 2.6V 

l D = 250 mA (each bit) 




55 


70 


mA 


v E 


External operating supply 
voltage 








40 


V 


'leak 


Output leakage current 
{each output) 


V E = 40V V EN =0V 






1 


mA 


V z 


Internal clamp voltage 


l z =0.3A* V EN =0V 


45 


50 


65 


V 


V CE sat 


Output saturation voltage 


\ a = 250 mA V EN =2.6V 






1.6 


V 


V CLK 
V E N 


Input logic levels 
(pins 1, 9, 10) 


Low State (L) 






0.8 


V 


High state !H) 


2.6 






'di 


Data input current 


V D| = 2.6V 


T amD =70 ; C 


0.3 


0.57 




mA 


T amD - 0'C 




0.57 


0.75 


V D ,= 1V T amD =70 ; C 




220 




/JA 


'CLK* 


Clock input current 


V CLK -2.6V 


T amB =70 ; C 


0.2 


0.33 




mA 


Tamb = ° C 




0.33 


0.5 


V CLK=1V T amb =70°C 




125 




MA 


'en 


Enable input current 


V EN =2.6V 


Tamb= 70°C 


0.2 


0.33 




mA 


Tamb= °°C 




0.33 


0.5 


V EN =1V T amb =70°C 




125 




uA 


R IN 


Input pull-down resistance 
Clock input 


T amB -25'C V CLK <V S 




8 




K.Q 


Enable input 


T amD =25 c C V EIN1 <.V S 




8 




Data input 


T amb =25 J C V DI <V S 




4.5 




v D o 


Output logic levels 
(pin 7) 


Low state (L) 

V D ,= 0V l DO (pin7)-0 




0.01 


0.5 


V 


High state (H) 

V D ,= 2.6V 

I DO (pin 7) = -0.75 mA 


2,6 


3.4 




V 


R DO 


Output pull-down 
resistance (pin 7) 


V DI =0V V DO =1V 




14 




KS"i 



Pulsed: pulse duration = 300ms, duty cycle = 2% 



L3654S 



ELECTRICAL CHARACTERISTICS (see fig. 1 and the section ' 


definition of terms") 




Parameter 


Test conditions 


Min. 


Typ. 


Max. 


Unit 


Clock, data and enable input 

tcLK 




4 






jUS 


'CLK 




5.5 






tSET-UP 




1 






'hold 




3 






Clock to enable delay 

•CLK EN 




2t B IT 








Enable to clock delay 

'EN CLK 




'bit 








Data output delay 

•pdh. 'pdl 


R L = 5Kn, C L < 10 pF 




0.8 


2.5 


MS 


Output delay 

tpDEL 






3 




MS 


tpDEH 






3.5 




Output rise time 


R L = 100 n, C L < 100 pF 




1.2 




MS 


Output fall time 


R L = 100 n, C L < 100 pF 




1.2 




MS 


V DO rise time 






0.4 




MS 


V DO fall time 






0.4 




MS 



DEFINITION OF TERMS 

V ss : External power supply voltage. The return for open-collector relay driver outputs. 

^di. V clk , V en ■. The voltages at the data, clock and enable inputs respectively. 



Vr 



The voltage at data output. 

Period of the incoming clock. 

The portion of t Bn - when V CLK > 2.6V. 

The portion of t B , T when V CLK < 0.8V. 

The time following the start of t CLK required to transfer data within the shift register. 

The time prior to the end of t CLK required to insure valid data at the shift register input 
for subsequent clock transitions. 



482 



^^^^^^® 



L4901 



PRELIMINARY DATA 



DUAL 5V REGULATOR WITH RESET 



• OUTPUT CURRENTS: l 01 = 300mA 

1 02 = 400mA 

• FIXED PRECISION OUTPUT VOLTAGE 5V 

±2% 

• RESET FUNCTION CONTROLLED BY IN- 
PUT VOLTAGE AND OUTPUT 1 VOLTAGE 

• RESET FUNCTION EXTERNALLY PRO- 
GRAMMABLE TIMING 

• RESET OUTPUT LEVEL RELATED TO 
OUTPUT 2 

• OUTPUT 2 INTERNALLY SWITCHED WITH 
ACTIVE DISCHARGING 

• LOW LEAKAGE CURRENT, LESS THAN 
1/uA AT OUTPUT 1 

• LOW QUIESCENT CURRENT (INPUT 1) 

• INPUT OVERVOLTAGE PROTECTION UP 
TO 60V 



• RESET OUTPUT HIGH 

• OUTPUT TRANSISTORS SOA PROTEC- 
TION 

• SHORT CIRCUIT AND THERMAL OVER- 
LOAD PROTECTION 

The L4901 is a monolithic low drop dual 5V 
regulator designed mainly for supplying micro- 
processor systems. 

Reset and data save functions during switch on/ 
off can be realized. 



r^~ 




Heptawatt 



ORDERING NUMBER: L4901 



ABSOLUTE MAXIMUM RATINGS 



V,r 



DC input voltage 

DC operating input voltage 

Transient input overvoltage (t = 40ms) 

Output current 

Storage and junction temperature 



24 


V 


20 


V 


60 


V 


internally limited 




-40 to 150 


"C 



BLOCK DIAGRAM 



VnO- 



i20- 



X 
X 

X 



t t t 



THERMAL 
PROTECTION 



DELAYED 
RESET 



X~ 



-KD v o1 



"X 
x 



-<5 V °2 



-O RESET 
-O TIMING 



483 



12/86 



L4901 



SCHEMATIC DIAGRAM 




484 



CONNECTION DIAGRAM 

(Top view) 



L4901 




> OUTPUT 1 

> OUTPUT 2 
RESET 

> GROUND 
? DISABLE INPUT 

> TIMING CAPACITOR 

> INPUT 



PIN FUNCTIONS 



N° 


NAME 


FUNCTION 


1 


INPUT 1 


Low quiescent current 300mA regulator input. 


2 


INPUT 2 


400mA regulator input. 



TIMING CAPACITOR 



If Reg. 2 is switched-ON the delay capacitor is charged 
with a 5/UA constant current. When Reg. 2 is switch- 
ed-OFF the delay capacitor is discharged. 



GND 



Common ground. 



RESET OUTPUT 



When pin 3 reaches 5V the reset output is switched high. 
5V , , 



Therefore t RD = C t 



5^A 



C t (nF) 



OUTPUT 2 



5V - 400mA regulator output. Enabled if V 1 > V RT 
and V| N2 > V, T . If Reg. 2 is switched-OFF the C 02 
capacitor is discharged. 



OUTPUT 1 



5V - 300mA regulator output with low leakage (in 
switch-OFF condition). 



THERMAL DATA 



Rthj-case Thermal resistance junction-case 



C/W 



485 



L4901 



TEST CIRCUIT 




I I 



1 1 r:. 



ELECTRICAL CHARACTERISTICS (V„ 



'ise specified) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V 01 Output voltage 1 


R load 1 K& 


4.95 


5.05 


5.15 


V 


V 02H Output voltage 2 HIGH 


R load 1 Kfl 


v i -0.1 


5 


Vol 


V 


v 02 L Output voltage 2 LOW 


'02 = -5mA 




0.1 




V 


l i Output current 1 


AV 01 = -100mV 


300 






mA 


'loi Leakage output 1 current 


V| N = 
V 01 < 3V 






1 


MA 


l 02 Output current 2 


AV 02 = -100mV 


400 






mA 


V i01 Output 1 dropout voltage (*) 


l 01 = 10mA 
l 01 = 100mA 
l 01 = 300mA 




0.7 
0.8 
1.05 


0.8 

1 

1.25 


V 
V 
V 


Vj T Input threshold voltage 




Voi+1.2 


6.4 


Vol +1.6 


V 


V (TH Input threshold voltage hyst. 






250 




mV 


AVqi Line regulation 1 


7V < V IN < 18V 

I oi ~ 5mA 




5 


50 


mV 


AVq 2 Line regulation 2 


Iq2 = 5mA 




5 


50 


mV 


AV i Load regulation 1 


V, N = 8V 

5mA < l i < 300mA 




40 


80 


mV 


AV 02 Load regulation 2 


5mA < l 2 < 400mA 




50 


100 


mV 


Iq Quiescent current 


< V, N < 13V 
6.3V < V, N < 13V 
l 02 = l 01 < 5mA 




4.5 
1.6 


6 
3.5 


mA 
mA 


Iq2 Quiescent current 1 


6.3V < V, N1 < 13V 

V|N2. = 

l 01 S 5mA l 02 = 




0.6 


0.9 


mA 

] 



486 



L4901 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Vrt 


Reset threshold voltage 




V 02 -0.15 


4.9 


V 02 -0.05 


V 


V RTH 


Reset threshold hysteresis 






50 


160 


mV 


Vrh 


Reset output voltage HIGH 


l R = 500mA 


V 02 -1 


4.12 


V 2 


V 


Vrl 


Reset output voltage LOW 


l R = -5mA 




0.25 


0.4 


V 


'rd 


Reset pulse delay 


C t = 10nF 


6 


10 


14 


ms 


td 


Timing capacitor discharge 
time 


C t = 10nF 






20 


MS 


AV 01 

AT 


Thermal drift 


-20°C <S T amb < 140°C 


-0.8 


0.3 


+0.8 


mV/°C 


AV 02 
AT 


Thermal drift 


-20°C < T amb < 140°C 


-0.8 


0.3 


+ 0.8 


mV/°C 


SVR1 


Supply voltage rejection 


f = 100Hz V R = 0.5V 
l = 100mA 


54 


84 




dB 


SVR2 


Supply voltage rejection 


50 


80 




dB 


T JSD 


Thermal shut down 






150 




°C 



* The dropout voltage is defined as the difference between the input and the output voltage when the output voltage 
lowered of 25mV under constant output current condition. 



APPLICATION INFORMATION 



In power supplies for p.P systems it is necessary 
to provide power continuously to avoid loss 
of information in memories and in time of day 
clocks, or to save data when the primary supply 
is removed. The L4901 makes it very easy to 
supply such equipments; it provides two voltage 
regulators (both 5V high precision) with separ- 
ate inputs plus a reset output for the data save 
function. 

CIRCUIT OPERATION (see Fig. 1) 

After switch on Reg. 1 saturates until V 01 
rises to the nominal value. 

When the input 2 reaches V, T and the output 1 
is higher than V RT the output 2 (V 02 ) switches 
on and the reset output (V R ) also goes high after 
a programmable time T RD (timing capacitor). 

V 02 and V R are switched together at low level 
when one of the following conditions occurs: 

— an input overvoltage 



— an overload on the output 1 (V 01 < V RT ); 

- a switch off (V| N < V, T - V| TH ); 

and they start again as before when the con- 
dition is removed. 
An overload on output 2 does not switch Reg. 2 



(V 



V r 



influence Reg. 1. 



at'' '02 = Isc2' ar| d does not 



The V 01 output features: 

— 5V internal reference without voltage divider 
between the output and the error comparator; 

- very low drop series regulator element util- 
izing current mirrors; 

permit high output impedance and then very 
low leakage current error even in power down 
condition. 

This output may therefore be used to supply 
circuits continuously, such as volatile RAMs, al- 
lowing the use of a back-up battery without a 



487 



L4901 



CIRCUIT OPERATION (continued) 

separation diode. The V 01 regulator also features 
low consumption (0.6mA typ.) to minimize 
battery drain in applications where the V x re- 
gulator is permanently connected to a battery 
supply. 

The V 02 output can supply other non essential 
5V circuits wich may be powered down when 
the system is inactive, or that must be powered 



down to prevent uncorrect operation for supply 
voltages below the minimum value. 

The reset output can be used as a "POWER 
DOWN INTERRUPT", permitting RAM access 
only in correct power conditions, or as a "BACK- 
UP ENABLE" to transfer data into in a NV 
SHADOW MEMORY when the supply is in- 
terrupted. 



Fig. 1 




'01 

OVERLOAD 



OVERLOAD ! OVERLOAD 



THERMAL 

SHUT SWITCH 

DOWN OFF 



APPLICATION SUGGESTIONS 



Fig. 2 shows an application circuit for a ,uP 
system typically used in trip computers or in 
car radios with programmable tuning. 

Reg. 1 is permanently connected to a battery 
and supplies a CMOS time-of-day clock and a 
CMOS microcomputer chip with volatile memory. 
Reg. 2 may be switched OFF when the system 
is inactive. 

Fig. 4 shows the L4901 with a back up battery 
on the V 01 output to maintain a CMOS time-of- 
day clock and a stand by type N-MOS piP- The 
reset output makes sure that the RAM is forced 
into the low consumption stand by state, so the 
access to memory is inhibit and the back up 
battery voltage cannot drop so low that memory 
contents are corrupted. 

In this case the main on-off switch disconnects 
both regulators from the supply battery. 



The L4901 is also ideal for microcomputer sys- 
tems using battery backup CMOS static RAMs. 
As shown in fig. 5 the reset output is used both to 
disable the /UP and, through the address decoder 
M74HC138, to ensure that the RAMS are disabled 
as soon as the main supply starts to fall. 

Another interesting application of the L4901 is 
in /J.P system with shadow memories, (see fig. 6) 

When the input voltage goes below V| T , the 
reset output enables the execution of a routine 
that saves the machine's state in the shadow 
RAM (xicor x 2201 for example). 

Thanks to the low consumption of the Reg. 1 
a 680/jF capacitor on its input is sufficient to 
provide enough energy to complete the operation. 
The diode on the input guarantees the supply 
of the equipment even if a short circuit on V, 
occurs. 



488 



APPLICATION SUGGESTION (continued) 
Fig. 2 



L4901 





INI I 








7 OUT 1 V DD 








REG.l 




CMOS 
CLOCK 


I 


4 

0.22,uF^r 






1" " 
— 1/uF 


BATTERY 








X 






CMOS 

/UP WITH 

VOLATILE 

RAM 










6 OUT2 






REG. 2 










C2^ 
1/uF 

3 

C3 

10 nF ± 






,-L, 1 tolO/uF 
^"C5 

5 RESET OUT 




V DD. 












U901 


OTHER 
LOGIC 

@5V 




j RESET _ 














*~ 



± 



Fig. 3 - P. C. board component layout of fig. 2 (1:1 scale) 




6 O 

GND IN1 



6 O 

OUT2 GND 



489 



L4901 



APPLICATION SUGGESTION (continued) 
Fig. 4 




OUT 1 '.LD1 



l, m* 1 "* 



1/uF 



T TT~ 1 



CMOS 
CLOCK 



T BACKUP 



BATTERY 
OUT 2 V 



X 

I 



1 tolO/uF 



5 RESET OUT 



DD J 



RESET ^ 



/uP(3875-2875) 

WITH BATTERY 

BACKUP 

RAM 



OTHER LOGIC 
@ 5V 



Fig. 5 




! 2.8to3V 

~L LITHIUM 
T BATTEHV 



TO OTHER 
MEMORY 

CHIPS 



X" 



490 



L4901 



APPLICATION SUGGESTION (continued) 
Fig. 6 



T^ 



N1 


OUT 1 - 




L4901 


N2 


our 2 


:t 


RESET 




GND 



"O,", 



1CyjF 




Fig. 7 - Quiescent current 
(Reg. 1) vs. output current 



Fig. 8 - Quiescent current 
(Reg. 1) vs. input voltage 



Fig. 9 - Total quiescent cur- 
rent vs. input voltage 



'a: I : atot 



3 6 9 



3 6 9 12 15 18 V| (V) 



Fig. 10 - Regulator 1 out- 
put current and short circuit 
current vs. input voltage 




Fig. 11 - Regulator 2 out- 
put current and short circuit 
current vs. input voltage 



























1 y 


'•* \ 










yr 




^ 




K^°T\ 
















. 


tt-h-U 


■ ; i 


\ 



Fig. 12 - Supply voltage 
rejection regulators 1 and 2 
vs. input ripple frequence 









T 


SVR1 










































' ! 








SVH2 




































II 








ill 








j 










*t 










M 




















tjj 




















tff 




















ll 








j 


| 


i i 


illi 



3 6 9 12 15 18 ¥| (V) 



15 18 21 24 V| ( V) 



491 



^^^^^^s 



L4902 



PRELIMINARY DATA 



DUAL 5V REGULATOR WITH 
AND DISABLE FUNCTIONS 



RESET 



• OUTPUT CURRENTS: I 



300mA 
400mA 



• FIXED PRECISION OUTPUT VOLTAGE 5V 

± 2% 

• RESET FUNCTION CONTROLLED BY IN- 
PUT VOLTAGE AND OUTPUT 1 VOLTAGE 

• RESET FUNCTION EXTERNALLY PRO- 
GRAMMABLE TIMING 

• RESET OUTPUT LEVEL RELATED TO 
OUTPUT 2 

• OUTPUT 2 INTERNALLY SWITCHED WITH 
ACTIVE DISCHARGING 

• OUTPUT 2 DISABLE LOGICAL INPUT 

• LOW LEAKAGE CURRENT, LESS THAN 
1/jA AT OUTPUT 1 

• RESET OUTPUT HIGH 



• INPUT OVERVOLTAGE PROTECTION UP 
TO 80V 

• OUTPUT TRANSISTORS SOA PROTEC- 
TION 

• SHORT CIRCUIT AND THERMAL OVER- 
LOAD PROTECTION 

The L4902 is a monolithic low drop dual 5V 
regulator designed mainly for supplying micro- 
processor systems. 

Reset and data save functions and remote switch 
on/off control can be realized. 




Heptawatt 
ORDERING NUMBER: L4902 



ABSOLUTE MAXIMUM RATINGS 



v„ 



T stg' T j 



DC input voltage 

DC operating input voltage 

Transient input overvoltage (t = 40ms) 

Output current 

Storage and junction temperature 



24 


V 


20 


V 


60 


V 


nternally limited 




-40 to 150 


°C 



BLOCK DIAGRAM 



"I O- 



DIS. 

o- 



~x 



DISABLE 



THERMAL. 
PROTECTION 



□CLAYED 
RESE' 




-O RESET 

-OTIMING 



493 



12/86 



L4902 



SCHEMATIC DIAGRAM 




494 



CONNECTION DIAGRAM 

(Top view) 



L4902 



rh 


I — ^-, 

6 
5 

L 
3 
2 

— <fV 




3 OUTPUT 1 




J OUTPUT 2 




> HI- Shi 




J (ikOUNU 


1 I 




> IMSABlh INPUT 




■> IIMING CAPACITOR 




> INPUI 


. 



PIN FUNCTIONS 



NAME 



INPUT 1 



FUNCTION 



Regulators common input. 



TIMING CAPACITOR 



If Reg. 2 is switched-ON the delay capacitor is charged 
with a 5/nA constant current. When Reg. 2 is switch- 
ed-OFF the delay capacitor is discharged. 



V 02 DISABLE INPUT 



A high level (> V DT ) disable output Reg. 2. 



GND 



RESET OUTPUT 



OUTPUT 2 



OUTPUT 1 



Common ground. 



When pin 2 reaches 5V the reset output is switched high. 



Therefore t RD = C t 



5V 
5/^A 



); t RD (ms) = C t (nF). 



5V - 400mA regulator output. Enabled if V 1 > V RT . 
DISABLE INPUT < V DT and V IN > V IT . If Reg. 2 is 
switched-OFF the C 2 capacitor is discharged. 



5V - 300mA. Low leakage (in switch-OFF condition) 
output. 



THERMAL DATA 



^thj-case Thermal resistance junction-case 



"C/W 



495 



L4902 



TEST CIRCUIT 




2.2uF 



ELECTRICAL CHARACTERISTICS (V 1N = 14.4V, T amb =25°C unless otherwise specified) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Vol 


Output voltage 1 


R load 1K52 


4.95 


5.05 


5.15 


V 


V 02 H 


Output voltage 2 HIGH 


R load 1K« 


Voi-0.1 


5 


Vol 


V 


V Q2L 
'01 


Output voltage 2 LOW 


I ? = -5mA 
AV„i = -100mV 




0.1 | 


V 


Output current 1 max. 


300 




mA 


'loi 


Leakage output 1 current 


V| N = ° 
V 01 < 3V 




! 1 


HA 


'02 


Output current 2 max. 


AV 02 = -100mV 


400 






mA 


ViOl 


Output 1 dropout voltage {*) 


l 01 - 10mA 
l i = 100mA 
l 01 = 300mA 




0.7 
0.8 
1.05 


0.8 

1 
1.25 


V 
V 
V 


V|T 


Input threshold voltage 




Voi + 1.2 


6.4 


Vqi+1.6 


V 


V |T H 


Input threshold voltage 
hysteresis 


i 


250 




mV 


AV 01 


Line regulation 1 


7V < V, N < 18V l 01 = 5mA 




5 


50 


mV 


AV 02 


Line regulation 2 


l 02 ^ 5mA 




5 


50 


mV 


AV 01 


Load regulation 1 


V| N = 8V 

5mA < l ] < 300mA 

5mA < l 02 < 400mA 

< V, N < 13V 
6.3V < V !N < 13V V 02 LOW 
6.3V < V| N < 13V V 02 HIGH 
! 01 = I02 < 5mA 




40 


80 


mV 


AV 02 


Load regulation 2 




50 


100 


mV 


'q 


Quiescent current 


L . ._. 


4.5 
2,7 
1,6 


6 
4 
3.5 


mA 
mA 
mA 


Vrt 


Reset threshold voltage 




V 02 -0.15 


4.9 


V 02 -0.05 


V 


VrtH 


Reset threshold hysteresis 




50 


160 


mV 



496 



L4902 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Vrh 


Reset output voltage HIGH 


l R = 500m A 


V 02 -1 


4.12 


V 02 


V 


Vrl 


Reset output voltage LOW 


l R = -5mA 




0.25 


0.4 


V 


t RD 


Reset pulse delay 


C t = 10nF 


6 


10 


14 


ms 


td 


Timing capacitor discharge 
time 


C, = 10nF 






20 


MS 


v DT 


V 2 disable threshold voltage 






1.25 


2.4 


V 


Id 


V 2 disable input current 


V D < 0.4V 
V D > 2.4V 




-100 
-2 




MA 

ma 


AVqi 
AT 


Thermal drift 


-20°C < T amb < 140°C 


-0.8 


0.3 


0.8 


mV/°C 


AV 02 
AT 


Thermal drift 


- 20 °C < T amb < 140°C 


-0.8 


0.3 


0.8 


mV/°C 


SVR1 


Supply voltage rejection 


f = 100Hz V R = 0.5V l = 100mA 


54 


84 




dB 


SVR2 


Supply voltage rejection 


50 


80 




dB 


T JSD 


Thermal shut down 






150 




°C 



* The dropout voltage is defined as the difference between the input and the ou 
lowered of 25mV under constant output current condition. 



tput voltage when the output voltage is 



APPLICATION INFORMATION 



In power supplies for nP systems it is necessary 
to provide power continuously to avoid loss 
of information in memories and in time of day 
clocks, or to save data when the primary supply 
is removed. The L4902 makes it very easy to 
supply such equipments; it provides two voltage 
regulators (both 5V high precision) with common 
inputs plus a reset output for the data save func- 
tion and a Reg. 2 output disable. 



CIRCUIT OPERATION (see Fig. 1) 

After switch on Reg. 1 saturates until V 01 
rises to the nominal value. 

When the input reaches V IT and the output 1 
is higher than V RT the output 2 (V 02 ) switches 
on and the reset output (V R ) also goes high after 
a programmable time T RD (timing capacitor). 

V 02 and V R are switched together at low level 
when one of the following conditions occurs: 
- a high level (> V DT ) is applied on pin 3; 



— an input overvoltage; 

— an overload on the output 1 (V 01 < V RT ); 

— a switch off (V, N < V| T - V ITH ); 

and they start again as before when the con- 
dition is removed. 

An overload on output 2 does not switch Reg. 2 
< v o2 - V R = V CEsat ; l 02 = l SC2 ) and does not 
influence Reg. 1. 

The V 01 output features: 

— 5V internal reference without voltage divider 
between the output and the error comparator 

— very low drop series regulator element util- 
izing current mirrors 

permit high output impedance and then very 
low leakage current error in power down con- 
dition. 

This output may therefore be used to supply 
circuits continuously, such as volatile RAMs, al- 
lowing the use of a back-up battery without a 
separation diode. 



497 



L4902 



CIRCUIT OPERATION (continued) 



The V 02 output can supply other non essential 
5V circuits wich may be powered down when 
the system is inactive, or that must be powered 
down to prevent uncorrect operation for supply 
voltages below the minimum value. 

The reset output can be used as a "POWER 
DOWN INTERRUPT", permitting RAM access 



only in correct power conditions, or as a "BACK- 
UP ENABLE" to transfer data into in a NV 
SHADOW MEMORY when the supply is in- 
terrupted. 

The disable function can be used for remote 
on/off control of circuits connected to the V 02 
output. 



Fig. 1 




SWITCH 
OFF 



APPLICATION SUGGESTION 



Fig. 2 illustrates how the L4902's disable input 
may be used in a CMOS ^Computer application. 

The V 0] regulator (low consumption) supply 
permanently a CMOS time of day clock and a 
CMOS /^computer chip with volatile memory. 
V 02 output, supplying non-essential circuits, is 
turned OFF under control of a n? unit. 

Configurations of this type are used in products 
where the OFF switch is part of a keyboard 
scanned by a micro which operates continuously 
even in the OFF state. 

Another application for the L4902 is supplying a 
shadow-ram microcomputer chip (SGS M38SH72 
for exemple) where a fast NV memory is backed 
up on chip by a EEPROM when a low level on 



the reset output occurs. 

By adding two CMOS CHMIDT-TRIGGER and 
few external components, also a watch dog 
function may be realized (see fig. 5). During 
normal operation the microsystem supplies a 
periodical pulse waveform; if an anomalous 
condition occours (in the program or in the 
system), the pulses will be absent and the disable 
input will be activated after a settling time de- 
termined by R1 C1. In this condition all the 
circuitry connected to V 02 will be disabled, 
the system will be restarted with a new reset 
front. 

The disable of V 02 prevent spurious operation 
during microprocessor malfunctioning. 



498 



L4902 



APPLICATION SUGGESTION (continued) 
Fig. 2 



I ^T 



CtJc2 



*>j RES. ; ~j- 



L4902 



7 OUT 1 



S 1/uF 
3 V 02 DIS 



J_ I toK) 



nF 



5 RtSET OUT 



CMOS 
CLOCK 



OUT 2 IN PORT , 



CMOS 

/uP WITH 

VOLATILE 

RAM 



ICO. 



RESET 



OTHER 
LOGIC 

@5V 



Fig. 3 - P.C. board and component layout of the circuit of Fig. 2(1:1 scale) 



mi 



C3 C4 



6 oo 



C2 

CD 



©00 © © Q> © 



IN 



o 

RESET 



o 

OUT1 



o 6 o 6 

GND DIS. OUT2 GND 



499 



L4902 



APPLICATION SUGGESTION (continued) 
Fig. 4 

Vol 



O 



DISABLE 

O 



10nF 



I 



1 



LA902 



X 



v o2 TO OTHER E= 

f *5V CHIPS |10uF 
= 10uF _L r 



100nF 



X" 



>'DD 



M38SH72 



RESET 
V SH 



GND 

X" 



Fig. 5 



o— 



I — ' i-.i. 

1" 



IN 0UT1 



OUT2 



L4902 



RST 



DIS. TIM , 

GND 

V—T c ± 



Ji 10nl 



T ^~^ T 

= 4.7uF — - 



T 



■x 








OUTPUT 
PORT 



JU1TL 



500 



APPLICATION SUGGESTION (continued) 



L4902 



Fig. 6 - Quiescent current 
vs. output current 




Fig. 7 - Quiescent current 
vs. input voltage 



'□ 




1 ! ' I 






M) 




J _ [ 










\ 


l 01 .l j<5m* 


e 






V 2 HIGH t • 








1 s 






i / \ / 


* 




— t\- '] — * f >' yf 






/ L s /\ 


7 




l\-'^X ! 




- 


/ ; ; ' ' ! ' " ; 



Fig. 8 - Regulator 1 output 
current and short circuit 
current vs. input voltage 



:0O 200 



) >I '5 




Fig. 9 - Regulator 2 output 
current and short circuit 
current vs. input voltage 




Fig. 10 - Supply voltage 
rejection regulators 1 and 2 
vs. input ripple frequence 



:::z^_ s 




. 




V 




S: >■ • ! ^ 


N\ 




Nlv 






:: \: 










.. __.^ 


















^ 









501 



^^^^^^^^^® 



L4903 



ADVANCE DATA 



DUAL 5V REGULATOR WITH RESET 
AND DISABLE FUNCTIONS 



OUTPUT CURRENTS: I 



01 
'02 
OUTPUT 



50mA 
100mA 

VOLTAGE 



FIXED PRECISION 
5V ±2% 

RESET FUNCTION CONTROLLED BY IN- 
PUT VOLTAGE AND OUTPUT 1 VOLTAGE 

RESET FUNCTION EXTERNALLY PRO- 
GRAMMABLE TIMING 

RESET OUTPUT LEVEL RELATED TO 
OUTPUT 2 

OUTPUT 2 INTERNALLY SWITCHED WITH 
ACTIVE DISCHARGING 

OUTPUT 2 DISABLE LOGICAL INPUT 

LOW LEAKAGE CURRENT, LESS THAN 
1/uA AT OUTPUT 1 

INPUT OVERVOLTAGE PROTECTION UP 
TO 60V 



• RESET OUTPUT LOW 

• OUTPUT TRANSISTORS SOA PROTEC- 
TION 

• SHORT CIRCUIT AND THERMAL OVER- 
LOAD PROTECTION 

The L4903 is a monolithic low drop dual 5V 
regulator designed mainly for supplying micro- 
processor systems. 

Reset, data save functions and remote switch 
on/off control can be realized. 



I rWjjfl Minidip Plastic 

ORDERING NUMBER: L4903 



ABSOLUTE MAXIMUM RATINGS 



V|N 


DC input voltage 


24 


V 


V,N 


DC operating input voltage 


20 


V 


v, 


Transient input overvoltage (t = 40ms) 


60 


V 


°tot 


Power dissipation at T amb = 50 C 


1 


W 


T s tg. Tj 


Storage and junction temperature 


-40 to 150 


°C 



BLOCK DIAGRAM 



VnO 



i20 



DIS.O- 



_Lj: 



THERMAL 
PROTECTION 



REG. 



REG. 2 



K 



DELAYED 

RESET 



"X 



-o v °1 



^v o2 



-O RESET 
-OTIMING 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

503 12/86 



L4903 



SCHEMATIC DIAGRAM 




504 



L4903 



CONNECTION DIAGRAM 

(Top view) 



INPUT 1 




5 I V 02 

1 DISABLE 

INPUT 



PIN FUNCTIONS 



N° 

1 
2 
3 



NAME 



INPUT 1 



INPUT 2 



FUNCTION 



Low quiescent current 50mA regulator input. 



100mA regulator input. 



TIMING CAPACITOR 



If Reg. 2 is switched-ON the delay capacitor is charged 
with a 5/liA constant current. When Reg. 2 is switched- 
OFF the delay capacitor is discharged. 



GND 



Common ground. 



V 02 DISABLE INPUT 



A high level (> V DT ) disable output Reg. 2. 



RESET OUTPUT 



When pin 3 reaches 5V the reset output is switched low. 

5V 
Therefore t RD = C, (=— r-); t RD (ms) = C t (nF). 



OUTPUT 2 



5V - 100mA regulator output. Enabled if V 1 > V RT . 
DISABLE INPUT < V DT and V IN 2 > V IT . If Reg. 2 is 
switched OFF the C 02 capacitor is discharged. 



8 OUTPUT 1 5V - 50mA regulator output with low leakage in switch- 

OFF condition. 


THERMAL DATA 


Rthj-pin Thermal resistance junction-pin 4 max 
Rthj-amb Thermal resistance junction-ambient max 


70 °C/W 
100 °C/W 



505 



L4903 




P.C. board and components layout 
of the test circuit (1 : 1 scale) 

GND V i2 V i1 
9 9? 




O^ 



GND DIS RS V„, V n 



ELECTRICAL CHARACTERISTICS (V 1N = 14.4V, T amb - 25°C unless otherwise specified) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Vol 


Output voltage 1 


R load 1 K^2 


4.95 


5.05 


5.15 


V 


V 02H 


Output voltage 2 HIGH 


R load 1Kii 


V i -0.1 


5 


Vol 


V 


V 02L 


Output voltage 2 LOW 


l 02 = -5mA 


50 


0.1 




V 


'01 


Output current 1 max. (*) 


AV 01 = -lOOmV 






mA 


'loi 


Leakage output 1 current 


V| N = 
V 01 < 3V 






1 


uA 


'02 


Output current 2 max. (*) 


AV 02 = -100mV 


100 






mA 


VlOl 


Output 1 dropout voltage {*) 


l 01 = 10mA 
l 01 = 50mA 


|_ _ . _ 


0.7 
0.75 


0.8 
0,9 


V 
V 


V|T 


Input threshold voltage 




^01 + 1.2 


6.4 


Vfll+16 


V 


V|TH 


Input threshold voltage 
hysteresis 






250 




mV 


AV 01 


Line regulation 1 


7V < V iN < 18V i 0i - 5mA 




5 


50 


mV 


AV 02 


Line regulation 2 


l 2 = 5mA 




6 


50 


mV 
mV 


AVoi 


Load regulation 1 


V !N1 = 8V 5mA < l 01 < 50mA 




5 


20 


AV 02 


Load regulation 2 


5mA < 1 02 < 100mA 


10 


50 


t mV 


|q 


Quiescent current 


< V| N < 13V 
6.3V < V IN < 13V V 02 LOW 
6.3V < V| N < 13V V 02 HIGH 
•oi = ! 02 < 5mA 




45 
2.7 
1.6 


6 

4 
3.5 


mA : 
mA 
mA i 


Iqi 


Quiescent current 1 


6.3V < V, N1 < 13V 

V,N2 = ° 

l 01 < 5mA l 02 = 




0.6 


0.9 


mA i 



506 



L4903 



ELECTRICAL CHARACTERISTICS (continued) 



v 



RT 



RD 



Parameter 



Test Conditions 



Reset threshold voltage 



Vrjh Reset threshold hysteresis 
V RH Reset output voltage HIGH 

V RL Reset output voltage LOW 



Min, 



V 02 -0.4 



Ir = 500mA 
l R = -5mA 



Reset pulse delay 



10nF 



t d Timing capacitor discharg 

time 



10nF 



Typ. 



Max. 



V 02 -0.2 



160 



Unit 



0.25 



10 



0.4 



14 



20 



Vdt 


V u2 disable threshold voltage 






1.25 


2.4 


V 


lo 


V 02 disable input current 


V D < 0.4V 
V D > 2.4V 




-100 
-2 




MA 

ma 


AV 01 

AT 


Thermal drift 


-20°C<T amb < 140 C C 


-0.8 


0.3 


0.8 


mV/°C 


AV 02 
AT 


Thermal drift 


-20 c C<T amb < 140°C 


-0.8 


0.3 


0.8 


mV/°C 


SVR1 


Supply voltage rejection 


f=100Hz V R = 0.5V l o = 50mA 


54 


84 




d8 


SVR2 


Supply voltage rejection 


l = 100mA 


50 


80 




dB 


T JSD 


Thermal shut down 






150 




°C 



The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is 
lowered of 25mV under constant output current conditions. 



APPLICATION INFORMATION 

In power supplies for /uP systems it is necessary 
to provide power continuously to avoid loss 
of information in memories and in time of day 
clocks, or to save data when the primary supply 
is removed. The L4903 makes it very easy to 
supply such equipments; it provides two voltage 
regulators (both 5V high precision) with separate 
inputs plus a reset output for the data save func- 
tion and Reg. 2 output disable. 

CIRCUIT OPERATION (see Fig. 1) 

After switch on Reg. 1 saturates until V 01 rises 
to the nominal value. 

When the input 2 reaches V, T and the output 1 
is higher than V RT the output 2 (V 02 ) switches 
on and the reset output (V R ) goes low after 
a programmable time T RD (timing capacitor). 

V 02 is switched at low level and V R at high level 
when one of the following conditions occurs: 



— a high level (> V DT ) is applied on pin 5; 

— an input overvoltage; 

— an overload on the output 1 (V 01 < V RT ); 

— a switch off (V| N < V| T -V| TH ); 

and they start again as before when the condi- 
tion is removed. 
An overload on output 2 does not switch Reg. 2 



(V 



- V c 



l SC2 ) and does not 



2 - vr - V CEsat ; 
influence Reg. 1. 

The V 01 output features: 

— 5V internal reference without voltage divider 
between the output and the error comparator 

— very low drop series regulator element util- 
izing current mirrors 

permit high output impedance and then very 
low leakage current error in power down con- 
ditions. 

This output may therefore be used to supply 
circuits continuously, such as volatile RAMs, al- 
lowing the use of a back-up battery without a 
separation diode. 



507 



L4903 



CIRCUIT OPERATION (continued) 



The V 02 output can supply other non essential 
5V circuits wich may be powered down when 
the system is inactive, or that must be powered 
down to prevent uncorrect operation for supply 
voltages below the minimum value. 

The reset output can be used as a "POWER 
DOWN INTERRUPT", permitting RAM access 

Fig. 1 



only in correct power conditions, or as a "BACK- 
UP ENABLE" to transfer data into in a NV 
SHADOW MEMORY when the supply is in- 
terrupted. 

The disable function can be used for remote 
on/off control of circuits connected to the V 02 
output. 




SWITCH 
ON 



APPLICATION SUGGESTION 



Fig. 2 illustrates how the L4903's disable input 
may be used in a CMOS uComputer application. 

The V 01 regulator (low consumption) supply 
permanently a CMOS time of day clock and a 
CMOS ^computer chip with volatile memory. 
V 02 output, supplying non-essential circuits, is 

Fig. 2 



BATTER' 

1 



"X 



I 



T 



turned OFF under control of a jizP unit. 

Configurations of this type are used in products 
where the OFF switch is part of a keyboard 
scanned by a micro which operates continuously 
even in the OFF state. 



I 



CMOS 
CLOCK 



CMOS 
W P WITH 
VOLATILE 



CTHE'R 
LOGIC 

^5v 



508 



L4903 



Fig. 3 - Quiescent current 
(Reg. 1) vs. output current 




Fig. 4 - Quiescent current 
(Reg. 1) vs. input voltage 




9 12 15 



Fig. 5 - Total quiescent 
current vs. input voltage 



j 






| ! l Ol- l 02- 5 
j : "02 


IGH "I ? 

V 

f - 


! 


v 2 


I\. \ .* 


y i s" 


.l^'^fyi 




I rt ; ~ 


— - 





Fig. 6 - Supply voltage re- 
jection regulators 1 and 2 
vs. input ripple frequence 











L.SVR1 






' 








































■* 


:Sv-2 
































\\ 
























^ 
















































60 - - •■ 



3 6 9 1? 15 



509 



^^^^^^^p® 



L4904 



ADVANCE DATA 



DUAL 5V REGULATOR WITH RESET 



1 02 = 100mA 

• FIXED PRECISION OUTPUT VOLTAGE 
5V ± 2% 

• RESET FUNCTION CONTROLLED BY IN- 
PUT VOLTAGE AND OUTPUT 1 VOLTAGE 

• RESET FUNCTION EXTERNALLY PRO- 
GRAMMABLE TIMING 

• RESET OUTPUT LEVEL RELATED TO 
OUTPUT 2 

• OUTPUT 2 INTERNALLY SWITCHED WITH 
ACTIVE DISCHARGING 

• LOW LEAKAGE CURRENT, LESS THAN 
1//A AT OUTPUT 1 

• LOW QUIESCENT CURRENT (INPUT 1) 

• INPUT OVERVOLTAGE PROTECTION UP 
TO 60V 



• RESET OUTPUT HIGH 

• OUTPUT TRANSISTORS SOA PROTEC- 
TION 

• SHORT CIRCUIT AND THERMAL OVER- 
LOAD PROTECTION 

The L4904 is a monolithic low drop dual 5V 
regulator designed mainly for supplying micro- 
processor systems. 

Reset and data save functions during switch on/ 
off can be realized. 



I Ifl Minidip Plastic 

ORDERING NUMBER: L4904 



ABSOLUTE MAXIMUM RATINGS 



V|N 


DC input voltage 


24 


V 




DC operating input voltage 


20 


V 




Transient input overvoltage (t = 40ms) 


60 


V 


lo 


Output current 


internally limited 




Ptot 


Power dissipation at T amb = 50 C 


1 


W 


Tj 


Storage and junction temperature 


-40 to 150 


C 



BLOCK DIAGRAM 



v i20- 



~x 



"X 



L 4904 



THERMAL 
PROTECTION 



DELAYED 
RESET 



"X 



O v ol 



J^ W 



-O RESET 
-OTIMING 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

511 12/86 



L4904 



SCHEMATIC DIAGRAM 




512 



CONNECTION DIAGRAM 

(Top view) 



PIN FUNCTIONS 



L4904 




N° 


NAME 


FUNCTION 


1 


INPUT 1 


Low quiescent current 50mA regulator input. 


2 


INPUT 2 


100mA regulator input. 



TIMING CAPACITOR 



If Reg. 2 is switched-ON the delay capacitor is charged 
with a 5/nA constant current. When Reg. 2 is switched- 
OFF the delay capacitor is discharged. 



GND 



Common ground. 



RESET OUTPUT 



When pin 3 reaches 5V the reset output is switched high. 

5V 

Therefore t RD = C t ( — — ); t RD (ms) = C t (nF). 

bjuA 



OUTPUT 2 



5V - 100mA regulator output. Enabled if V 1 > V RT 
and V| N2 > V, T . If Reg. 2 is switched-OFF the C 02 
capacitor is discharged. 



OUTPUT 1 



5V - 50mA regulator output with low leakage in switch- 
OFF condition. 



THERMAL DATA 



Rthj-«mb Thermal resistance junction-ambient 



100 



C/W 



513 



L4904 



TEST CIRCUIT 



*MO- 



v,2 °~t\ 



L4904 



6 reset! 



__ X ^ 1 T =L T 

S= 5p2.2/jF 10nF=^C, ^2.2jjF 

a^« — ^ S-903/1 ^^ ^" ■*■ ^" 



o2 



P.C. board and components layout 
of the test circuit (1 : 1 scale) 

GND V i2 V i1 

9 



c„ 0©# 



i_Til 



© ® <$> ® ^ 



6 

GND 



O O O 
RS V o2 V o1 



ELECTRICAL CHARACTERISTICS (V IN = 14.4V, T amb = 25°C unless otherwise specified) 





Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Vol 


Output voltage 1 


R load 1KH 


4.95 


5.05 


5.15 


V 


V 02 H 


Output voltage 2 HIGH 


R load 1 Kf! 


V i -0.1 


5 


Vol 


V 


V 02L 


Output voltage 2 LOW 


I 02 = -5mA 




0.1 




V 


"01 


Output current 1 


AV 01 = -100mV 


50 






mA 


'loi 


Leakage output 1 current 


V| N = 
V 01 < 3V 






1 


ma 


'02 


Output current 2 


AV 02 = -100mV 


100 






mA 


V,01 


Output 1 dropout voltage (*) 


l 01 = 10mA 
l 01 = 50mA 




0.7 
0.75 


0.8 
0.9 


V 
V 


V|T 


Input threshold voltage 




V 01 +1.2 


6.4 


V 01 +1.6 


V 


VlTH 


Input threshold voltage hyst. 






250 




mV 


AV 01 


Line regulation 


7V < V, N < 18V l 01 = 5mA 




5 


50 


mV 


AV 02 


Line regulation 2 


I02 = 5mA 




5 


50 


AV 01 


Load regulation 1 


V, N = 8V 5mA < l 01 < 50mA 




5 


20 


mV 


AV 02 


Load regulation 2 


5mA < l 02 < 100mA 




10 


50 


'q 


Quiescent current 


< V| N < 13V 
6.3V < V| N < 13V 
! 02 = 'oi * 5mA 




4.5 

1.6 


6 
3.5 


mA 
mA 


Iqi 


Quiescent current 1 




6.3V < V| N1 < 13V 

V|N2 = 

l 01 < 5mA l 02 = 

u 




0.6 


0.9 


mA 



514 



L4904 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Vrt 


Reset threshold voltage 




V 02 -0.15 


4.9 


V 02 -0.05 


V 


V RTH 


Reset threshold hysteresis 






50 


160 


mV 


Vrh 


Reset output voltage HIGH 


l R = 50GVA 


V 02 -1 


4.12 


V 02 


V 


Vrl 


Reset output voltage LOW 


l R = -5mA 




0.25 


0.4 


V 


*RD 


Reset pulse delay 


C t = 10nF 


6 


10 


14 


ms 


*d 


Timing capacitor discharge 
time 


C, = 10nF 






20 


MS 


AV 1 
AT 


Thermal drift 


-20°C < T amb < 140°C 


-0.8 


0.3 


+ 0.8 


mV/°C 


AV 02 

AT 


Thermal drift 


-20°C < T amb < 140°C 


-0.8 


0.3 


+0.8 


mV/°C 


SVR1 


Supply voltage rejection 


l = 50mA 
f = 100Hz 
V R - 0.5V 

l = 100mA 


54 


84 




dB 


SVR2 


Supply voltage rejection 


50 


80 




dB 


T JSD 


Thermal shut down 






150 




°C 



* The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is 
lowered of 25mV under constant output current condition. 

APPLICATION INFORMATION 



In power supplies for juP systems it is necessary 
to provide power continuously to avoid loss 
of information in memories and in time of day 
clocks, or to save data when the primary supply 
is removed. The L4904 makes it very easy to 
supply such equipments; it provides two voltage 
regulators (booth 5V high precision) with separ- 
ate inputs plus a reset output for the data save 
function. 

CIRCUIT OPERATION (see Fig. 1) 

After switch on Reg. 1 saturates until V 01 
rises to the nominal value. 

When the input 2 reaches V| T and the output I 
is higher than V RT the output 2 (V 02 ) switches 
on and the reset output (V R ) also goes high after 
a programmable time T RD (timing capacitor). 

V 02 and V R are switched together at low level 
when one of the following conditions occurs: 
— an input overvoltage 



— an overload on the output 1 (V 01 < V RT ); 

— a switch off (V !N < V| T - V| TH ); 

and they start again as before when the con- 
dition is removed. 
An overload on output 2 does not switch Reg. 2 



<V 



V B 



VcEsat; 'o2 = Isc2> and does not 



influence Reg. 1. 

The V 01 output features: 

— 5V internal reference without voltage divider 
between the output and the error comparator; 

— very low drop series regulator element util- 
izing current mirrors; 

permit high output impedance and then very 
low leakage current error in power down con- 
dition. 

This output may therefore be used to supply 
circuits continuously, such as volatile RAMs, al- 
lowing the use of a back-up battery without a 
separation diode. The V 01 regulator also features 



515 



L4904 



CIRCUIT OPERATION (continued) 

low consumption (0.6mA typ.) to minimize 
battery drain in applications where the Vj re- 
gulator is permanently connected to a battrey 
supply. 

The V 02 output can supply other non essential 
5V circuits which may be powered down when 
the system is inactive, or that must be powered 
down to prevent uncorrect operation for supply 



voltages below the minimum value. 

The reset output can be used as a "POWER 
DOWN INTERRUPT", permitting RAM access 
only in correct power conditions, or as a "BACK- 
UP ENABLE" to transfer data into in a NV 
SHADOW MEMORY when the supply is in- 
terrupted. 



Fig. 1 




OVERLOAD; OVERLOAD ! DOWN 



APPLICATION SUGGESTIONS 

Fig. 2 shows an application circuit for a MP 
system. 

Reg. 1 is permanently connected to a battery 
and supplies a CMOS time-of-day clock and a 
CMOS microcomputer chip with volatile memory. 

Reg. 2 may be switched OFF when the system 
is inactive. 

Fig. 3 shows the L4904 with a back up battery 



on the V 01 output to maintain a CMOS time-of- 
day clock and a stand by type C-MOS a/P The 
reset output makes sure that the RAM is forced 
into the low consumption stand by state, so the 
access to memory is inhibit and the back up 
battery voltage cannot drop so low that memory 
contents are corrupted. 

In this case the main on-off switch disconnects 
both regulators from the supply battery. 



516 



L4904 



APPLICATION SUGGESTIONS (continued) 

Application Circuits of a Microprocessor system (Fig. 2) or with data save battery (Fig. 3). The reset 
output provide delayed rising front at the turn-off of the regulator 2. 



Fig. 2 



BAT 



TERY I 



IN! t 



! 0.22juf"| 

L ^ 1N2 
i — c^b 1 — 



1/jF 



10 nF 



-c 



REG.1 



-c^ny- 2 



U904 



OUT 1 



I" 



'DD 



/uF 



CMOS 

CLOCK 



'DP 



7 OUT 2 



RESET 



C 2 



tolO^jF 



CMOS 

fjP WITH 

VOLATILE 

RAM 



"DD 



S RESET OUT I RESET 



OTHER 
LOGIC 

@5V 



Fig. 3 



I c^o f 

BATTERY 

T 



0.22,uF ; 



i- 



IN 2 2 

T 



4.7 ju F I 



C T 
10nF 



r 

I 



REG. t 



REG. 2 



L4904 



OUT I ' j-01 ■" 1 ^ A V DC 



i 4- 



C MOS 
CLOCK 



"SB 



iBACKU 
BATTE! 



P 

BATTERY 



OUT 2 



I 



"DD, 



olOwF 



6 RESET OUT 



RESET, 



WITH BATTERY 

BACKUP 

RAM 



*DD 



RESET 



OTHER LOGIC 
Q 5V 



517 



L4904 



APPLICATION SUGGESTIONS (continued) 



Fig. 4 - Quiescent current 
(Reg. 1) vs. output current 



'01 
















1 












i 1 


























T/|j.0V 




























































































































































































































































0.6 




























































































































































j 




I 


1 








1 









Fig. 6 - Total quiescent cur- 
rent vs. input voltage 

















G 


-JM7/1 


>Qlot 

ImA) 


























'oi sl OI* s 


m* 










i 






























/I 


















/ 
















' 


' 
























/ 

















Fig. 5 - Quiescent current 
(Reg. 1) vs. input voltage 



J Q1 


- I-U 


i ! ! 


6 


1 ! 






», 2 .o 


J 1 














r 














_, 








/ 




/l 










/ 






\l 








/ 








A 






y 

















3 6 9 12 15 Iti V ( , tV) 



Fig. 7 - Supply voltage 
rejection regulators 1 and 2 
vs. input ripple frequence 



SVR 
(dB) 






5VR1 










' £=--. 


; ; — 








' SVR 2 










V~ 










V 










V 










- -.,,, 

































3 6 9 II 15 IB V, (V) 



518 



^^p^^^^^r® 



L4920 
L4921 



PRELIMINARY DATA 



VERY LOW DROP ADJUSTABLE REGULATOR 



• VERY LOW DROP VOLTAGE 

• ADJUSTABLE OUTPUT VOLTAGES FROM 
1.25V TO 20V 

• 400mA OUTPUT CURRENT 

• LOW QUIESCENT CURRENT 

• OVERVOLTAGE AND REVERSE VOLT- 
AGE PROTECTION 

• +60/-60 TRANSIENT PEAK VOLTAGE 

• SHORT CIRCUIT PROTECTION WITH 
FOLDBACK CHARACTERISTICS 

• THERMAL SHUT-DOWN 

The L4920 and L4921 are adjustcble voltage 
regulators with a very low voltage drop (0.4V 
typ. at 0.4A), low quiescent current and com- 
prehensive on-chip protection. 

These devices are protected against load dump 
transients of ± 60V, input overvoltage, polarity 
reversal and over heating. 



A foldback current limiter protects against load 
short circuits. 

The output voltage is adjustable through an 
external divider from 1.25V to 20V. The mini- 
mum operating input voltage is 5.2V. 

These regulators are designed for automotive, 
industrial and consumer applications where low 
consumption is particularly important. 

In battery backup and standby applications the 
low consumption of these devices extends bat- 
tery life. 






L4920 



Pentawatt 
ORDERING NUMBERS 



Minidip (4 + 4) 



L4921 



BLOCK DIAGRAM 



INPUT 

o — 



THERMAL 
PROTECTION 









p- a n -"- 






PRF.REC-ULi-OR 




REFERENCE 

A NIC 

ERROR 

AMPL'EIEP 






i 






— 






DUMP 

PR0TEC T ION 

















FOLDBAC". 

CURRENT 

LIMITER 



T~~ 



GN0 
— O- 



519 



12/86 



L4920 
L4921 



ABSOLUTE MAXIMUM RATINGS 






V, 


DC input operating voltage 




26 


v t 


Positive transient peak voltage (t = 300ms 


1% duty cycle) 


+ 60 


V, 


Negative transient peak voltage (t = 100ms 


1% duty cycle) 


-60 


v. 


Reverse input voitage 




-18 


"^stg 


Storage temperature 




-55 to 150 


* op 


Operating junction temperature 




-40 to 150 



V 
V 
V 
V 

°c 
°c 



CONNECTION 


DIAGRAMS 


(top 

G.R1X: 


view) 

■j D 








,,, [ 


2 
I 
U 


8 
7 
6 


! 
I 
l 
! 


r ._J 


— : 


6 






_. 


> output 












OUTPUT [ 




o 












w 


2 

1 




INPUT j 


t=: — 


> Nf 


Mf f 




-:-i _ij 


- 


> INPUT 


\.C. [ 


X T, 


16 

awatt 






Minidip 






-<-..-. Tab connected to pi 

Pent 





APPLICATION CIRCUIT 



IN OUT 

GND REf^ 



10.1 /iF 



O — 



-»^-o 



R2 



1—1 



RUR2 
V ° = ~T?2 W 



o 

S-7917 a 



C = 100>F is required for stability (ESR < 3S2 o»er T range) 
R2 " 6.2KS2 



THERMAL DATA 



nth j-amb 
nth j-pins 



Thermal resistance junction ambient 
Thermal resistance junction pins 



■Hhj-case Thermal resistance junction case 



max 
max 
max 



Minidip 
(4 + 4) 



80'C/W 
15"C/W 



Pentawatt 



60 C/W 
4 = C/W 



520 



L4920 
L4921 



ELECTRICAL CHARACTERISTICS (For V, = 14.4V V = 5V; T, = 25°C; C = 100/uF; R2 : 
6.2KA unless otherwise noted) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Vj Operating input 
voltage 


Vo > 4.5V 
lo = 400mA 


Vo + 0.7 




26 


V 


Vref < Vo < 4.5V 
lo = 400mA 


5.2 




26 


V 


Vref Reference voltage 


5.2V < V, < 26V 
lo < 400mA (*) 


1.20 


1.25 


1.30 


V 


AV Line regulation 


Vo + 1V < Vj < 26V V > 4.5V 

lo = 5mA 




1 


10 


mV/V 


AV Load regulation 


5mA < lo < 400mA (*) V > 4.5V 




3 


15 


mV/V 


V D Dropout voltage 


lo = 10mA 
lo = 150mA 
lo = 400mA 




0.05 
0.2 
0.4 


0.4 
0.7 


V 
V 
V 


| D Quiescent current 


lo = 0mA 

V + 1 V < Vi < 26V 




0.8 


3 


mA 


lo = 400mA (*) 
Vo+ 1V< Vi< 26V 




65 


100 


mA 


l Maximum output 
current 






650 


900 


mA 


'osc Short circuit output 
current (*) 




200 


350 


500 


mA 


V R Reverse polarity input 
voltage (DC) 


Vo> -1.5V R L < 50012 






-18 


V 



(*) Foldback protection 



521 



L4920 
L4921 



Fig. 1 - Output voltage vs. 
temperature 



_I .5mA I 



Fig. 2 - Foldback current 

limiting 





























































































































































































V =5V 














































































































































































































































*7 















































































































































































































































































































































































Fig. 3 - Quiescent current 
vs. outputcurrent (V = 5V) 



iq 


J :._ 


' ' mm 


(mA) 


! 1 






' 
























— < 1 — 
































itTT 






















— 1 ,- 












; ■ 














































i 






■ 
















i 


80 




























60 




























___. i 






















40 






















.^1 












20 


" ' \ 1 




1 — u 






_J=trt 








^^ [ 









-40 -20 20 40 60 80 100 T. (*C I 



200 400 600 600 l„(mA) 



200 300 



APPLICATION INFORMATION 

1) The L4920 and L4921 have Vref a 1.25V. Then the output voltage can be set down to Vref but Vi must be 
greater than 5.2V. 

2) As the regulator reference voltage source works in closed loop, the reference voltage may change in foldback con- 
dition. 

3} For applications with high Vj the total power dissipation of the device with respect to the thermal resistance of 
the package may be limiting the application. The total power dissipation is: 

Ptot = Vi l q + (Vi - V ) l 
A typical curve giving the quiescent current l q as a function of the output current i »s shown in fig. 3. 



522 



^^^^^We 



L4941 



ADVANCE DATA 



VERY LOW DROP 1A REGULATOR 



• PRECISE 5V OUTPUT (±2%) 

• LOW DROPOUT VOLTAGE (450mV TYP. 
AT 1A) 

• VERY LOW QUIESCENT CURRENT 

• THERMAL SHUT DOWN 

• SHORT CIRCUIT CURRENT LIMITER 

• OVERVOLTAGE PROTECTION 

• REVERSE POLARITY PROTECTION 



The L4941 is a very low input/output voltage 
drop, low quiescent current and high output 



current capability IC particularly useful in ap- 
plications such as battery powered systems 
where power dissipation is a design constraint. 

Standard regulator features such as thermal shut 
down, current limiter and overvoltage protec- 
tion are also provided. 




TO-220 



ORDERING NUMBER: L4941BV 



BLOCK DIAGRAM 



IN 



o- 



PRERES . 



PROTECT 



BAND-GAP 
REF. 



S-9474 



._-. 



AMP -^ 



OUT 



ANTISAT. 
CIRCUIT 



GND 6 



I This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

! 523 



11/86 



L4941 



ABSOLUTE MAXIMUM RATINGS 



v, 


Forward input voltage (R = 100fi) 


40 


V 


V| 


Reverse input voltage (R = 10012) 


-15 


V 


'op 


Operating junction temperature range 


-40 to 125 


°C 


ll 


Maximum junction temperature 


150 


"C 


"^stg 


Storage temperature range 


-65 to 150 


°C 



CONNECTION 

(Top view) 



DIAGRAM 



GNO 



•€> 



Z> CXJTPUT 



3 GROUND 
^ INPUT 



S- 2568/1 



TEST AND APPLICATION CIRCUIT 



Vi 

O- 



1 

T 



100 nF 



22/uF 



r 

T 



-o 



THERMAL DATA 



'th j-case 



Thermal resistance junction-case 



C/W 



524 



L4941 



ELECTRICAL CHARACTERISTICS (V, = 14V, T, = 25°C) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V Q Output voltage 


l = 5mA 


4.9 


5 


5.1 


V 


Vo Output voltage 


V, = 6V to 14V 
l = 5mA to 1 A 


4.8 


5 


5.2 


V 


Vj Operating input voltage 


(*) See note 






16 


V 


V Line regulation 


6V < V; < 16V l = 5mA 




5 


25 


mV 


Vq Load regulation 


l = 50mA to 1 A 




15 


35 


mV 


l(j Quiescent current 


6V < V, < 16V l = 5mA 




3.5 


10 


mA 


l = 1A 




20 


50 


Vj-Vq Dropout voltage 


lo= 1A 




450 


700 


mV 


l = 100mA 




150 


250 


AVq/AT Output voltage drift 






0.6 




mV/°C 


SVR Supply voltage rejection 


f = 120Hz 
lo= 1A 


60 






dB 


lo Current limit 






1.3 




A 


Zo Output impedance 


lo = 200mA 
f = 120Hz 




30 




mil 


E N Output noise voltage 


f = 100Hz to 100KHZ 
lo = 10mA 




100 




rms 



(*) For a DC input voltage 16V < Vj < 40V the device is not operating 



525 



L4941 



Fig. 1 - Dropout output 
voltage vs. current 




Fig. 2 - Quiescent current 
vs. output current 









I 
























!v =SV 




































































































































I 















Fig. 3 - Quiescent current 
vs. load current 













































































L 1A 






























tin LOAD 










I I ! 



zoo 4oo 600 eoo i„(m 



Fig. 4 - Low voltage be- 
haviour , „„ 





1 














1 . 1000 mA 
Tj.i5*C 












































y 















/ 


- 














\ 




- 






l/ 









Fig. 5 - Output at voltage 
extremes 



1 




1 




| 






















i 


- 


R L =100 














° 


















































- 


























/ 










\ 










/ 








\ 














/ 










\ 














\i 






/I 











I 3 4 5 6 V, (V) 



-5 *5 *10 +1^ '20 



Fig. 6 - Line transient response 



Fig. 7 - Load transient response 



T 



OUTPUT 

VOtfAGE 

DEVIATION 



Vjn"6V 
1 =0.5A 
C =HmF 



INPUT 

VOLTAGE 

CHANGE 



10 20 30 



(mV) 








200 
100 


/ ' 


k 


OUTPUT 

VOLTAGE 

DEVIATION 


-100 




-200 






C =22/uF 
Tj =25"C 


(mA) 






V Q= 5V 


IK 
800 














600 
400 






LOAD 
CURRENT 


200 







20 UO 60 !^js) 

S-9A62 



526 



L4941 



APPLICATION INFORMATION 

Fig. 8 - Distributed supply with on-card L4941 low-drop regulators 



HIGH POWER 
PREREGULATOR 



X 



-o-5'- 



X 



X 



X 



Advantages of this application are: 

— Card isolation 

— Thermal and short-circuit protection 

— High efficiency (80%), like switching regula- 
tors, but without radiation and intermodula- 
tion problems 



U941 



r 



LA9A1 



X 



U941 



r 



x 



x 



-05V 



-05V 



X 



-05V 



527 



^i^^^^ws 



L4960 



PRELIMINARY DATA 



2.5A POWER SWITCHING REGULATOR 



• 2.5A OUTPUT CURRENT 

• 5.1V TO 40V OUTPUT VOLTAGE RANGE 

• PRECISE (± 2%) ON-CHIP REFERENCE 

• HIGH SWITCHING FREQUENCY 

• VERY HIGH EFFICIENCY (UP TO 90%) 

• VERY FEW EXTERNAL COMPONENTS 

• SOFT START 

• INTERNAL LIMITING CURRENT 

• THERMAL SHUTDOWN 

The L4960 is a monolithic power switching 
regulator delivering 2.5A at a voltage variable 
from 5V to 40V in step down configuration. 
Features of the device include current limiting, 

ABSOLUTE MAXIMUM RATINGS 



soft start, thermal protection and to 100% 
duty cycle for continuous operation mode. 

The L4960 is mounted in a Heptawatt plastic 
power package and requires very few external 
components. 

Efficient operation at switching frequencies 
up to 150KHz allows a reduction in the size 
and cost of external filter components. 




Heptawatt 



ORDERING NUMBER: L4960 (Vertical) 

L4960H (Horizontal! 



Vi 


Input voltage 




50 


V 


Vi-V 7 


Input to output voltage difference 




50 


V 


v 7 


Negative output DC voltage 




-1 


V 




Negative output peak voltage at t = 0.1jUs; f 


= 100KHz 


-5 


V 


v 3 ,v 6 


Voltage at pin 3 and 6 




5.5 


V 


v 2 


Voltage at pin 2 




7 


V 


u 


Pin 3 sink current 




1 


mA 


■s 


Pin 5 source current 




20 


mA 


Ptot 


Power dissipation at T case < 90°C 




15 


W 


T j. T stg 


Junction and storage temperature 




-40 to 150 


°C 



BLOCK DIAGRAM 



:1 



-L 
I 



?" 



h sawtooth 1 
oscillator) 




^r 



529 



12/86 



L4960 



CONNECTION DIAGRAM 




> SOFT START 
OSCILLATOR 

> GND 
FREQ, COMP 

5 FEEDBACK INPUT 
NPUT 



-Tab connected to pin 4 



THERMAL DATA 



^thj-case Thermal resistance junction-case 
Rttij-amb Thermal resistance junction-ambient 



max 
max 



4 
50 



C/W 

D c/w 



PIN 


FUNCTIONS 




N° 


NAME 


FUNCTION 


1 


SUPPLY VOLTAGE 


Unregulated voltage input. An internal regulator powers 
the internal logic. 


2 


FEEDBACK INPUT 


The feedback terminal of the regulation loop. The 
output is connected directly to this terminal for 5.1V 
operation; it is connected via a divider for higher volt- 
ages. 


3 


FREQUENCY 
COMPENSATION 


A series RC network connected between this terminal 
and ground determines the regulation loop gain charac- 
teristics. 


4 


GROUND 


Common ground terminal. 


5 


OSCILLATOR 


A parallel RC network connected to this terminal 
determines the switching frequency. 


6 


SOFT START 


Soft start time constant. A capacitor is connected bet- 
ween this terminal and ground to define the soft start 
time constant. This capacitor also determines the average 
short circuit output current. 


7 


OUTPUT 


Regulator output. 



530 



L4960 



ELECTRICAL CHARACTERISTICS (Refer to the test circuit, Tj = 25°C, V, 
otherwise specified) 



35V, unless 



Parameter 


I 

Test Conditions 1 Min. 


Typ. 


1 I 
Max. Unit 1 



DYNAMIC CHARACTERISTICS 



Vo 


Output voltage range 


V,=46V l =1A 


Vref 




40 


V 


v. 


Input voltage range 


V = V ref to 36V l = 2.5A 


9 




46 


V 


AV Q 


Line regulation 


Vi = 10Vto40V V = V ref l = 1A 




15 


50 


mV 


AV 


Load regulation 


V = V ref l = 0.5Ato2A 




10 


30 


mV 


Vref 


Internal reference voltage 
(pin 2) 


Vi = 9Vto46V l = 1 A 


5 


5.1 


5.2 


V 


A Vref 
AT 


Average temperature 
coefficient of refer, voltage 


Tj = 0°C to 125°C 
l = 1A 




0.4 




mV/°C 


'om 


Dropout voltage 


l =2A 




1.4 


3 


V 


Maximum operating load 
current 


V, = 9V to 46V 
V D = V ref to 36V 


2.5 






A 


>7L 


Current limiting threshold 
(Pin 7) 


V, = 9V to 46V 
V = V ref to 36V 


3 




4.5 


A 


'SH 


Input average current 


Vj = 46V; output short-circuit 




30 


60 


mA 


n 


Efficiency 


f = 100KHZ 
l = 2A 


v = v ref 




75 




% 


V = 12V 




85 




% 


SVR 


Supply voltage ripple 
rejection 


AVi=2V rms 

f r , pple = 100Hz 

V = V ref l =1A 


50 


56 




dB 


f 


Switching frequency 




85 


100 


115 


KHz 


Af 
AV, 


Voltage stability of 
switching frequency 


V, = 9V to 46V 




0.5 




% 


Af 
ATj 


Temperature stability of 
switching frequency 


Tj = 0°C to 125°C 




1 




% 


'max 


Maximum operating 
switching frequency 


Vo = V ref l = 2A 


120 


150 




KHz 


Tsd 


Thermal shutdown 
junction temperature 






150 




°C 



531 



L4960 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test Conditions Min. 


Typ. 


Max. 


Unit 



DC CHARACTERISTICS 



liQ Quiescent drain current 


100% duty cycle 
pins 5 and 7 open 


V, = 46V 




30 


40 


mA 


0% duty cycle 




15 


20 


mA 


-l 7L Output leakage current 


0% duty cycle 






1 


mA 



SOFT START 



'6SO Source current 




100 


130 


150 


MA 


IgSI Sink current 




50 


70 


120 


m a 



ERROR 


AMPLIFIER 














v 3H 


High level output voltage 


V 2 = 4.7V 


l 3 = 100mA 


3.5 






V 


V 3L 


Low level output voltage 


V 2 = 5.3V 


l 3 = 100mA 






0.5 


V 


'3SI 


Sink output current 


V 2 = 5.3V 


100 


150 




mA 


_l 3SO 


Source output current 


V 2 = 4.7V 


100 


150 




mA 


l 2 


Input bias current 


V 2 = 5.2V 




2 


10 


mA 


G v 


DC open loop gain 


V 3 = 1V to 3V 


46 


55 




dB 



OSCILLATOR 



-l 5 Oscillator source current 




5 




mA 



532 



L4960 



CIRCUIT OPERATION (refer to the block d 

The L4960 is a monolithic stepdown switching 
regulator providing output voltages from 5.1V 
to 40V and delivering 2.5A. 

The regulation loop consists of a sawtooth oscil- 
lator, error amplifier, comparator and the output 
stage. An error signal is produced by comparing 
the output voltage with a precise 5.1V on-chip 
reference (zener zap trimmed to ± 2%). 

This error signal is then compared with the saw- 
tooth signal to generate the fixed frequency 
pulse width modulated pulses which drive the 
output stage. 

The gain and frequency stability of the loop can 
be adjusted by an external RC network con- 
nected to pin 3. Closing the loop directly gives 
an output voltage of 5.1V. Higher voltages are 
obtained by inserting a voltage divider. 

Output overcurrents at switch on are prevented 
by the soft start function. The error amplifier 
output is initially clamped by the external capa- 



lagram) 

citor C ss and allowed to rise, linearly, as this 
capacitor is charged by a constant current source. 
Output overload protection is provided in the 
form of a current limiter. The load current is 
sensed by an internal metal resistor connected to 
a comparator. When the load current exceeds a 
preset threshold this comparator sets a flip flop 
which disables the output stage and discharges 
the soft start capacitor. A second comparator 
resets the flip flop when the voltage across the 
soft start capacitor has fallen to 0.4V. 

The output stage is thus re-enabled and the out- 
put voltage rises under control of the soft start 
network. If the overload condition is still present 
the limiter will trigger again when the threshold 
current is reached. The average short circuit cur- 
rent is limited to a safe value by the dead time 
introduced by the soft start network. The 
thermal overload circuit disables circuit oper- 
ation when the junction temperature reaches 
about 150°C and has hysteresis to prevent 
unstable conditions. 



Fig. 1 - Soft start waveforms 



OSCILLATOR 
OUTPUT 



CLAMPED- ERROR 
AMP OUTPUT 



Fig. 2 - Current limiter waveforms 



LIMIT 
THRESHOLD 



AVERAGE 
SHORT CIRCUIT 
CURRENT 




533 



L4960 



Fig. 3 - Test and application circuit 




O v ° 



2 x220;j' r 



S-7798/2 

C6, C7: EKR (ROE) 

L1 = 150/aH at 5A (COG EMA 946042) 

CORE TYPE: MAGNETICS 58206-A2 MPP 

N° TURNS 45, WIRE GAUGE: 0.8mm (20 AWG) 



Fig. 4 - Quiescent drain 
current vs. supply voltage 
(0% duty cycle) 



Fig. 5 - Quiescent drain 
current vs. supply voltage 
(100% duty cycle) 



Fig. 6 - Quiescent drain cur- 
rent vs. junction tempera- 
ture (0% duty cycle) 



"1Q 

(rr,A) 
























- 
















25 
2 








| 
















, 


























10 


























































— 














I ' 



















ho 


-- 


























































35 
30 




















































i 








20 




































































i 













I ! T v | = 35V ; 

HXt^-i--i— -— 

1 
— — I 1 1 — f -I — I — 



25 50 7 5 100 



534 



L4960 



Fig. 7 - Quiescent drain cur- 
rent vs. junction tempera- 
ture (100% duty cycle) 



I4 U : .Li - 






i T I 




.V| =35V 






-l-k 












-^-J 






~\~^' 


_ 


I 












I ! ~ 


' \ f T 

2 Ft 


i 


^^ > i 








' 




j I ; ; 



Fig. 8 - Reference voltage 
(pin 2) vs. V, 



"'•' 


' 


1 


[ 






1 1 




I =1 A 

[ 




















5 125 












_, 








1 




5 0-5 
5 050 










































! i ■ 








: i , , 1 , 1 ' ' 



Fig. 9 - Reference voltage 
vs. junction temperature 
(pin 2) 



V n?f 
(V) 


1 














1 


Vj*3SV 
t=2A 




5.100 
































5.050 
5.025 


— 












! ! 






r 


^H— 










' 


h 
1 





25 5D 75 100 T {'C 1 



20 30 to 



-75 25 50 75 100 T, CC) 



Fig. 10 - Open loop fre- 
quency and phase responde 
of error amplifier ri 



Fig. 1 1 - Switching fre- 
quency vs. input voltage 




Fig. 12 - Switching fre- 
quency vs. junction tem- 
perature 



<KH,) 






















-- 














Vi=35V 
V„. V re) 




105 
SOD 
95 












































































































































f 

















-25 25 50 75 100 125 150 Tj CO 



Fig. 13 - Switching frequen- 
cy vs. R2 (see test circuit) 































































































I 






















1 
















































1 

\ 


3. 


.5nF i 


















































































































ITS >■ 
























K\ 






















, nf \\ 








ir 




....... 








i ^VN 














' I 


i 


i i j\ 













Fig. 14 -- Line transient 
response 





: I = : i 

; INPUT voltage; 








! j 








i„.u 


















l~~ 














I . 




i i 




(mV) 








OUTPUT V0LTA3E CHANGE 










^^i 
















I 


pLT.. 












I f 










j 




' I 









Fig. 15 - Load transient 
response 



-- 




A 


' ! ! 


i LOAD CURRENT i i 


— 






I 










































\ 




















rt 


i . 






r 




j 


..^...^_: 








| 









2 3 Mm 



5 1 1.5 2 



535 



L4960 



Fig. 16 - Supply voltage 
ripple rejection vs. frequency 



SVR 
MB) 


jiir 


: ~~ ' 




















| 


i 


70 




I 








V;^35V 




||] 












A 




ill 


50 
40 










^1i 


ill 








: 












tti 






1 




















.1 
















: 












1 




j 






ill' 








|l 










H 


: 


















i|l 














I 






111 



Fig. 17 - Dropout voltage 
between pin 1 and pin 7 
vs. current at pin 7 











I ! 






















































Ti^lZS'C 
— -40 "C 
25*C 
































1 




































































i 













Fig. 18 - Dropout voltage 
between pin 1 and 7 vs. 
junction temperature 



! I ! 7 =2A 



100 IK f(H z ) 



100 T,('C) 



Fig. 19 - Power dissipation 
derating curve 









J 












! 






^,l 














\% 






sfe 








— 


— 



































Fig. 20 - Efficiency vs. 
output current 





















V|=35V 








■- 












». f = 2 

" 5 


5KHz 

OKHz 










1 - 


lOOHHz 








20 


OKHz 
















j 




DIODE 
BYW80 






' 










i 









Fig. 21 - Efficiency vs. 
output current 



Y~ 




REF 














— i 


V D = 












































--15V 
35V 


— 












































DIODE 
BYWftO 
























— 


















| 




| 













20 40 60 BO 100 120 T am fci*C ! 



0.5 1 1.5 2 2.5 



Fig, 22 - Efficiency vs. 
output current 



1 : ' 








I|r 


OOKHz 


— ' 









— 


— . 


^= 






V| =1SV 
35 V 








-F- 


1 

CIODE 
BYW80 


.._J 


- 






i 











Fig. 23 - Efficiency vs. 
output voltage 











1 




— 










1 =50KHz 












1 


XJKHz 
























































D = 


5V 
















YW80 





























































15 2 2.5 



5 10 15 20 25 



536 



APPLICATION INFORMATION 

Fig. 24 - Typical application circuit 



L4960 



o- 



C15 
100pF 



o— 

GND 



63V 



C5 
2.2fjF 

4.3KnM 



U960 



C2 



2.2 

nF 



L1 



150^1 H 

„. . SGS8R20 
D1 Ai OR 



R1 
15K.fi 



C 3 
S33nF 



2x 

2 20;jF 



BYW80 C6 40V C7 









R3 
4.7KA 



GND 



Ci,C 6 , C 7 : EKR (ROE) 
D ± : BYW80 OR 5A SCHOTTKY DIODE 
SUGGESTED INDUCTOR: L x = 150/nH at 5A 
CORE TYPE: MAGNETICS 58206 - A2 - MPP 

N° TURNS: 45, WIRE GAUGE: 0.8mm (20 AWG), COGEMA 946042 
U15/GUP15: N°TURNS:60, WIRE GAUGE: 0.8mm (20 AWG), AIRGAP:1mm, COGEMA 969051. 



Fig. 25 - P.C. board and component layout of 
the Fig. 24 (1 : 1 scale) 




Resistor values for 
standard output voltages 


Vo 


R3 


R4 


12V 
15V 
18V 
24V 


4.7KH 
4.7KS7 
4.7K« 
4.7KI2 


6.2K« 
9.1Kn 
12Kfi 
18K« 



537 



L4960 



APPLICATION INFORMATION (continued) 

Fig. 26 - A minimal 5.1V fixed regulator; Very few component are required 

T ni' 00 * jF 



lA.3 
Kfl 



^3 



SAWTOOTH 
OSCILLATOR 








L4960 



C0MP^>„d V 




INHIBIT 
FLIP 
FLOP 



THERMAL 
SHUTDOWN 



OUTPUT 
STAGE 



COGEMA 946042 (TOROID CORE) * 
969051 (U15CORE) -"- 
EKR (ROE) 




5.1V 

reference! 



!Cd 




~KT Qr 



1 



150,uH V =51V 



3G58R20 i 

OR ci-tj „ „ 

BYW80 1 U^ ** 
2x220 
| -'-iuF 
j 40V 



Fig. 27 - Programmable power supply 

40VA 



C^- 




V = 5.1V to 15V s . 7 eoo ( 2 

l =2.5A max 

Load regulation (lAto 2A) = 10mV |V = 5.1V) 

Line regulation (220V ± 15% and to l Q = 1 A) = 15mV (V Q = 5.1V) 



538 



L4960 



APPLICATION INFORMATION (continued) 

Fig. 28 - Microcomputer supply with + 5.1V, -5V, + 12V and -12V outputs 




539 



L4960 



APPLICATION INFORMATION (continued) 

Fig. 29 - DC-DC converter 5.1V/4A, ± 12V/2.5A; a suggestion how to synchronize a negative output 

ISOjuH 




L1, L3 = COGEMA 946042 (969051) 
L2 = COGEMA 946044 (946045) 
D 1: D 2 , D3 = SGS8B20 or BYW80 



# SGS6R20 OR BYW8 



Fig. 30 - In multiple supplies several L4960s can be synchronized as shown 



R ocs n -liosc 




LA960 



U960 



5-932'; I 



540 



APPLICATION INFORMATION (continued) 
Fig. 31 - Regulator for distributed supplies 



L4960 




-0 5V 



KESE T 
OUTPUT 



1_2 and C2 are necessary to reduce the switching frequency spikes when linear regulators are remote from L4960 



MOUNTING INSTRUCTION 

The power dissipated in the circuit must be 
removed by adding an external heatsink. 
Thanks to the Heptawatt package attaching the 
heatsink is very simple, a screw or a compression 
spring (clip) being sufficient. Between the heatsink 

Fig. 32 - Mounting example 



and the package it is better to insert a layer of 
silicon grease, to optimize the thermal contact, 
no electrical isolation is needed between the 
two surfaces. 




541 



^^^^^^s 



L4962 



PRELIMINARY DATA 



1.5A POWER SWITCHING REGULATOR 



• 1.5A OUTPUT CURRENT 

• 5.1V TO 40V OUTPUT VOLTAGE RANGE 

• PRECISE (± 20%) ON-CHIP REFERENCE 

• HIGH SWITCHING FREQUENCY 

• VERY HIGH EFFICIENCY (UP TO 90%) 

• VERY FEW EXTERNAL COMPONENTS 

• SOFT-START 

• INTERNAL LIMITING CURRENT 

• THERMAL SHUTDOWN 

The L4962 is a monolithic power switching 
regulator delivering 1.5A at a voltage veriable 
from 5V to 40V in step down configuration. 
Features of device include current limiting, 
soft start, thermal protection and to 100% 
duty cycle for continuous operating mode. 
The L4962 is mounted in a 16-lead Powerdip 

ABSOLUTE MAXIMUM RATINGS 



plastic package and Heptawatt package and 
requires very few external components. 

Efficient operation at switching frequencies 
up to 150KHz allows a reduction in the size 
and cost of external filter components. 




^L 




„ ,. Heptawatt 

Powerdip 

(12+ 2+2) 

ORDERING NUMBER: 

L4962 (12 + 2 + 2 Powerdip) 

L4962E (Heptawatt) 

L4962EH (Horizontal Heptawatt) 



BLOCK DIAGRAM 




v 7 


Input voltage 




50 


V 


V 7 -V 2 


Input to output voltage difference 




50 


V 


v 2 


Negative output DC voltage 




-1 


V 




Output peak voltage at t = 0.1/js, 


f = 100KHz 


-5 


V 


Vu.V 15 


Voltage at pin 11, 15 




5.5 


V 


v 10 


Voltage at pin 10 




7 


V 


In 


Pin 1 1 sink current 




1 


mA 


Il4 


Pin 14 source current 




20 


mA 


Ftot 


Power dissipation at Tp| ns < 90°C 


(Powerdip) 


4.3 


W 




Tease < 90° C 


(Heptawatt) 


15 


W 


Tj. T stg 


Junction and storage temperature 




-40 to 150 


°C 



543 



12/86 



L4962 



CONNECTION 


DIAGRAMS 




(Top view) 

N.C. | 










W 


•6 


] N.C 


OUTPUT | 






'^ 


JSOFT START 


N.C 1 






•' 


1 OSCILLATOR 


GND | 






'3 


] GND 


GNO | 






'-' 


] GND 


N.C | 






•' 


FREQXOMP 


INPUT | 






'C 


| FEEDBACK 


N.C | 


8 




9 


] 




ected to pin £ 



y SOFT START 
OSCILLATOR 

> GNO 

FREQ COMP 

> FEEDBACK INPUT 
NPUT 



THERMAL DATA 


Heptawatt 


Powerdip 


Rthj-case Thermal resistance junction-case max 
^thj-pins Thermal resistance junction-pins max 
^thj-amb Thermal resistance junction-ambient max 


4°C/W 
50°C/W 


14°C/W 
80°C/W* 



* Obtained with the GND pins soldered to printed circuit with minimized copper area. 

PIN FUNCTIONS 



HEPTAWATT 


POWERDIP 


NAME 


FUNCTION 


1 


7 


SUPPLY VOLTAGE 


Unregulated voltage input. An internal regu- 
lator powers the internal logic. 


2 


10 


FEEDBACK INPUT 


The feedback terminal of the regulation loop. 
The output is connected directly to this ter- 
minal for 5.1V operation; it is connected via a 
divider for higher voltages. 


3 


11 


FREQUENCY 
COMPENSATION 


A series RC network connected between this 
terminal and ground determines the regulation 
loop gain characteristics. 


4 


4, 5, 12, 13 


GROUND 


Common ground terminal. 


5 


14 


OSCILLATOR 


A parallel RC network connected to this ter- 
minal determines the switching frequency. This 
pin must be connected to pin 7 input when the 
internal oscillator is used. 


6 


15 


SOFT START 


Soft start time constant. A capacitor is con- 
nected between this terminal and ground to 
define the soft start time constant. The capaci- 
tor also determines the average short circuit 
output current. 


7 


2 


OUTPUT 


Regulator output. 




1, 3, 6, 
8, 9, 16 




N.C. 



544 



L4962 



ELECTRICAL CHARACTERISTICS (Refer to the test circuit, T, = 25 C, V, = 35V, unless 
otherwise specified) 



Parameter 


Test Conditions 


Min. Typ. 


Max, 


Unit 



DYNAMIC CHARACTERISTICS 



v 


Output voltage range 


V, = 46V 


l = 1A 


Vref 




40 


V 


V| 


Input voltage range 


V = V ref to 36V 


l =1.5A 


9 




46 


V 


AV 


Line regulation 


V| = 10V to 40V 


V = V ref l Q = 1A 




15 


50 


mV 


AV 


Load regulation 


Vo = V ref 


l = 0.5A to 1.5A 




8 


20 


mV 


Vref 


Internal reference voltage 
(pin 10) 


V, = 9V to 46V 


l =1A 


5 


5.1 


5.2 


V 


AV ref 
AT 


Average temperature 
coefficient of refer, voltage 


Tj = 0°C to 125°C 
l =1A 




0.4 




mV/°C 


v d 


Dropout voltage 


l = 1.5A 




1.5 


2 


V 


'om 


Maximum operating load 
current 


V, = 9Vto46V 
V = V ref to 36V 


1.5 






A 


»2L 


Current limiting threshold 
(pin 2) 


V, = 9V to 46V 
V = V ref to 36V 


2 




3.3 


A 


ISH 


Input average current 


Vj = 46V; output short-circuit 




15 


30 


tnA 


n 


Efficiency 


f = 100KHZ 
l =1A 


Vo = V ref 




70 




% 


V =12V 




80 




% 


SVR 


Supply voltage ripple 
rejection 


AVi = 2V rms 
fripple = 100Hz 

v = v ref 


l =1A 


50 


56 




dB 


f 


Switching frequency 




85 


100 


115 


KHz 


Af 


Voltage stability of 
switching frequency 


V, = 9V to 46V 




0.5 




% 


Af 
A Tj 


Temperature stability of 
switching frequency 


Tj = 0°C to 125°C 




1 




% 


*max 


Maximum operating 
switching frequency 


Vo = V ref 


l =1A 


120 


150 




KHz 


Tsd 


Thermal shutdown 
junction temperature 






150 




°C 



545 



L4962 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 



Test Conditions 



DC CHARACTERISTICS 



7q Quiescent drain current 



100% duty cycle 
pins 2 and 14 open 



-l 2 |_ Output leakage current 



0% duty cycle 



0% duty cycle 



V, = 46V 



SOFT START 



30 



15 



Min. Typ. Max. Unit 



40 



20 



mA 



mA 



'l5SO Source current 




100 


130 


160 


uA 


'l5Sl Sink current 




50 


70 


120 


,uA 


ERROR AMPLIFIER 


V 11H High level output voltage 


V 10 = 4.7V 


In = 100mA 


3.5 






V 


v liL Low level output voltage 


V 10 = 5.3V 


In = 100mA 






0.5 


V 


Ixi si Sink output current 


V 10 = 5.3V 


100 


150 




^A 


~'llSO Source output current 


V 10 = 4.7V 


100 


150 




<uA 


l 10 Input bias current 


V 10 = 5.2V 




2 


10 


MA 


G v DC open loop gain 


V 1X = 1V to 3V 


46 


55 




dB 


OSCILLATOR 


-1^4 Oscillator source current 




5 


| 


mA 



546 



L4962 



CIRCUIT OPERATION (refer to the block di 
The L4962 is a monolithic stepdown switching 
regulator providing output voltages from 5.1V 
to 40V and delivering 1.5A. 

The regulation loop consists of a sawtooth oscil- 
lator, error amplifier, comparator and the output 
stage. An error signal is produced by comparing 
the output voltage with a precise 5.1V on-chip 
reference (zener zap trimmed to ± 2% ). 

This error signal is then compared with the saw- 
tooth signal to generate the fixed frequency 
pulse width modulated pulses which drive the 
output stage. 

The gain and frequency stability of the loop can 
be adjusted by an external RC network con- 
nected to pin 11. Closing the loop directly gives 
an output voltage of 5.1V. Higher voltages are 
obtained by inserting a voltage divider. 

Output overcurrents at switch on are prevented 
by the soft start function. The error amplifier 
output is initially clamped by the external capa- 



agram) 

citor C B and allowed to rise, linearly, as this 
capacitor is charged by a constant current source. 
Output overload protection is provided in the 
form of a current limiter. The load current is 
sensed by a internal metal resistor connected to 
a comparator. When the load current exceeds a 
preset threshold this comparator sets a flip flop 
which disables the output stage and discharges 
the soft start capacitor. A second comparator 
resets the flip flop when the voltage across the 
soft start capacitor has fallen to 0.4V. 

The output stage is thus re-enabled and the out- 
put voltage rises under control of the soft start 
network. If the overload condition is still present 
the limiter will trigger again when the threshold 
current is reached. The average short circuit cur- 
rent is limited to a safe value by the dead time 
introduced by the soft start network. The 
thermal overload circuit disables circuit oper- 
ation when the junction temperature reaches 
about 150°C and has hysteresis to prevent 
unstable conditions. 



Fig. 1 - Soft start waveforms 



OSCILLATOR 
OUTPUT 



CLAMPED. ERROR 
AMP OUTPUT 



NOMINAL 
ERROR AMP - 

OUTPUT 




Fig. 2 - Current limiter waveforms 



LIMIT 
THRESHOLD 



'2 



AVERAGE 
5H0RT CIRCUIT 
CURRENT 



CURRENT 

LIMITER 

TRIGGERS 



f 




i^itflMttlL^-,^^ 



547 



L4962 



Fig. 3 - Test and application circuit (Powerdip) 



R1 



15K.fl 



2C3 
33 nF 



C1 



1000pF 
6 3V 



R4 



10 



LA962 



14 



s£te 



A.5,12,13 



L1 



15 
BYW98, 

C5 



R2 SC5 ^ = 

43K.fl 2.2pF |C7 |C 



150 uH 



D1 



« — o v ° 



2x220jjF 
"40V 
6 



1) Dj: BYW98 or 3A Schottky diode, 45V of VRRM; 

2) L 2 : CORE TYPE -MAGNETICS 58120 - A2 MPP 

N° TURNS 45, WIRE GAUGE: 0.8mm (20 AWG) 

3) C 6 ,C 7 : ROE, EKR 220//F 40V 



Fig. 4 - Quiescent drain 
current vs. supply voltage 
(0% duty cycle) 



'iQ 

(mA) 




! 










































































uJ 












i 




























1 1 ' 
















1 i 


L 1 1 i 





Fig. 5 - Quiescent drain 
current vs. supply voltage 
(100% duty cycle) 



Fig. 6 - Quiescent drain 
current vs. junction tem- 
perature (0% duty cycle) 















1 










i 








35V 


























,_ ._l 































; ; 


J 


— I 


" 


-Frrh 


- 


- 






+-^-^^- 




- 






T ; • i i i 





25 50 7 5 100 



548 



L4962 



Fig. 7 - Quiescent drain 
current vs. junction tem- 
perature (100% duty cycle) 



L U 1- 

trr: 


j ' j I ! 








^^-~~~T^~ 


uTitu 


' 1 

- -J--T- 

-T+ + - 




i i ; 


, : ^ i T 



Fig. 8 - Reference voltage 
(pin 10) vs. V, rdip) vs. V, 



Vr.t 


■ i--U-i- ! f^- 








• i pr- r 






1 l i 










: i i ' 


i 


5.05O 


! j ' 


_.: _L , — 


-^-i ._i_ 




" : ~Ti "" 







Fig. 9 - Reference voltage 
(pin 10) vs. junction tem- 
perature 



(V) 
















5.125 
5.XX) 

5.075 
5.050 
5025 












V i= 35V 




















































h 

















































-25 25 50 75 100 



10 20 30 



-26 25 5C 75 100 T,<-C) 



Fig. 10 - Open loop fre- 
quency and phase response 
of error amplifier G W19 



so - ■■ — 



40 - - 1 



_.. ___. .._ 


._. , — . 




^\ Gy 




f nNT "~ ~r _ 




■ \ 


- 1 -|— ! — ; \r - 



Fig. 11 - Switching fre- 
quency vs. input voltage 



I ' ' I 


I 






' 


'o-VrH 






i I , 


j 










I 






h I i 
































. J . ! . 












i , ! i 



10 100 m 10K 100K 



20 25 30 35 -0 45 



Fig. 12 - Switching fre- 
quency vs. junction tem- 
perature 



' 






I 












VJ.35V 
V v rH 






























































































































i 


J 











-25 25 50 75 100 125 150 Ij(X) 



Fig. 13 - Switching fre- 
quency vs. R2 (see test 
circuit) 

























Q 




Mil 


















(KHz) 




























































































































I 


















V 








| 














100 












s 


j. 


SnF 






































































































































! ii \X 












































i 






















i 


i 

1 


i 











Fig. 14 - Line transient 
response 



| j , inpu r 


VOLTAGE 


, o 








lo-U 


l± 


i 








' | 




_ ui 




i i 






OUTPU 


T VOLTAGE CHANGE 






^r; r 




























-f 






J 




















hill 


i ; 



Fig. 15 - Load transient 
response 





— 
















I 




-I- 








n 




| 
















[ ! 
















J 




I 




'OUTPUT VOLTAGE CHANGE" ft 

i I I I : L 






^_ 


lr^— I 




av 


_L_ 




I _^ | 




ImV) 




I ! 
















I I ! 





0.5 1 



549 



L4962 



Fig. 16 - Supply voltage 
ripple rejection vs. frequency 







till il 








illlll 




iiiliJ 






t 
i 


!l| , 




M 


Vj=35V 


mi 


|jf 






= !A 














. jj I |j| ; || III 






l| 






ii 




1\ 


it im 


- 






T 








lilii 


i 






I 


| 










Tf 




















I 


n 


; 




ii 






Illlll 







Fig. 17 - Dropout voltage 
between pin 7 and pin 2 vs. 
current at pin 2 



Fig. 18 - Dropout voltage 
between pin 7 and 2 vs. 
junction temperature 























(VI 

2 

1 .6 
1.2 
0.8 




























































































































































1 j = 


-4U 
25 


{.: 
c 
c - 


















































| 




































VISA 








































































,. 


I 
























I 













10 100 IK f(Hj) 



0.5 0.75 



2.5 50 100 



Fig. 19 - Efficiency vs. 
output current 





-LLU 














f= 50MHz 

1. 100 KHz 
















































»i 


15V. 


































"i 


"35 V 
































DIODE 
BYW98 













































Fig. 20 - Efficiency vs. 
output current 



1 
























vi, "■ 


35V 
V RFF 






























































































*Ht 


^ 














200 


KHz 


































DIODE 
VSK340 










1 


























1 









Fig. 21 - Efficiency vs. 
output current 



^ 



==£ 



* 



0.5 75 



1.25 I (A 



0.5 0.75 



125 l (A 



Fig. 22 - Efficiency vs. 
output voltage 

















1 1 
















f = 50KHz 
-lOOKHz 




































y 










Vi =35V 
!o=1A 
























































DIODE 
VSK340 




























i 




i 













Fig. 23 - Efficiency vs. 
output voltage 



"\ 


- 














1 
















f =50«Hz 






-■ 














10 


OKHz 


























//* 


V 


















70 


V 










V =35V 


















i 




















DIODE 
BVW98 

















































Fig.24-Maximum allowable 
power dissipation vs. ambi- 
ent temperature (Powerdip) 

















i 1 1 










1 










































































<* 












c 














\ 


i 1 




























* 














^ 
































V|* 














, > 


\ 














1 '"" 














1 ! v 














r" 


























1 














uJ J N 


\ 


































. 






















^~T 






f\ 


X 


















F f< 
























v - 


>*> 








' *■ l_l 


































































































i 




i . 








xK ^ 


















i i 






I v Sj 



5 10 15 20 25 V (vl 



50 100 T, mb [t; 



550 



L4962 



APPLICATION INFORMATION 

Fig. 25 - Typical application circuit 



O- 



100ljF 




L4962 

15 
U 4,5,12,13 11 1C 



C2 



T T- T 



o— 

GND 




GND 



Ci,C 6 , C 7 : EKR (ROE) 

Di: BYW98 OR VISK340 (SCHOTTKY) 

SUGGESTED INDUCTORS {L^: MAGNETICS 58120 - A2MPP - 45 TURNS - WIRE GAUGE 0.8mm (20AWG) 

COGEMA 946043 

ORU15, GUP15, 60TURNS1mm, AIR GAP 0.8mm (20AWG) - COGEMA 969051 



Fig. 26 - P.C. board and component layout of the circuit of Fig. 25 (1 : 1 scale) 




Resistor values for 
standard output 7 voltages 


Vo 


R8 


R7 


12V 
15V 
18V 
24V 


4.7K« 
4.7Kf2 
4.7KJ2 
4.7KS7 


6.2K£2 
9.1Kfi 
12KS7 
18Kn 



CS-02U 



551 



L4962 



APPLICATION INFORMATION (continued) 

Fig. 27 - A minimal 5.1V fixed regulator; very few components are required 



1? 



SAWTOOTH 
OSCILLATOR 




THERMAL 
SHUTDOWN 



INHIBIT 
FLIP 
FLOP 




I 



— o 



22 






tE ir 



COGEMA 946043 (TOROID CORE) 

969051 (U15CORE) 
EKR (ROE) 



r 



Af 



Fig. 27 - Programmable power supply 




V = 5.1V to 15V 

l Q = 1.5A max 

Load regulation (0.5A to 1 .5A) = 10mV (V = 5.1V) 

Line regulation (220V ± 15% and to l = 1A) = 15mV (V = 5.1V) 



552 



L4962 



APPLICATION INFORMATION (continued) 

Fig. 29 - DC-DC converter 5.1V/4A, ± 12V/1A. A suggestion how to synchronize a negative output 

150 *jH ,uv/u 



2x 

2200|ji 
50V" 
EVF 



I 




L4962 2 

15 11 4,5,12,1310 



I «.7| ial 



3 5 



L296 2 

9 8,6 10 



120pF 



1 T 33nF 



U96 2 2 

15 11 4,5,12,13 10 



rrp 



1500^jF 



-n ^ -TnF 

t"1 *a> 




L1, L3 = COGEMA 946043 (969051) 
L2 = COGEMA 946044 (9460451 



Fig. 30 - In multiple supplies several 
L4962s can be synchronized as shown 



Fig. 31 - Preregulator for distributed supplies 



h ocsr 



L4962 



LA962 



S - 9339/1 L . 






L4805 


SV/AOOmA 

I 




-L 


-n 


L4805 


5V/Z.00 mA 




X 






L 387A 






77 " 


7* 


— 


RESET 

OUTPUT 



* L2 and C2 are necessary to reduce the switching frequency spikes 
when linear regulators are remote from L4962 



553 



L4962 



MOUNTING INSTRUCTION 

The R th j-amb °f the L4962 can be reduced by 
soldering the GND pins to a suitable copper 
area of the printed circuit board (Fig. 32). 
The diagram of figure 33 shows the R t huamb as 
a function of the side "S." of two equal square 
copper areas having the thickness of 35ju (1.4 



mils). During soldering the pins temperature 
must not exceed 260°C and the soldering time 
must not be longer than 12 seconds. 
The external heatsink or printed circuit copper 
area must be connected to electrical ground. 



Fig. 32 - Example of P.C. board copper area which is 
used as heatsink 



COPPER AREA 3Sjj THICKNESS 




Fig. 33 - Maximum dissi- 
pable power and junction to 
ambient thermal resistance 
vs. side "2" 











































v 




















N 




















S^ 


















r 


^ 


■^ 














rt^ 


~-~~ 










>-H 


p lol l r ,mb * 70'C1 












— 



































JO 50 



PC. BOARD 



554 



9S 



L5832 



SOLENOID CONTROLLER 



• DRIVES ONE OR TWO EXTERNAL DAR- 
LINGTONS 

• DUAL AND SINGLE LEVEL CURRENT 
CONTROL 

• SWITCHMODE CURRENT REGULATION 

• ADJUSTABLE PEAK DURATION 

• WIDE SUPPLY RANGE (4.75-46V) 

• TTL-COMPATIBLE LOGIC INPUTS 

• THERMAL PROTECTION 

The L5832 Solenoid Controller is designed for 
use with one or two external darlington tran- 
sistors in solenoid and relay driving applications. 
The device is controlled by two logic inputs and 
features switchmode regulation of the load cur- 
rent. A key feature of the L5832 is flexibility. 
It can be used with a variety of darlingtons to 



match the requirements of the load and it allows 
both simple and two level current control More- 
over, the drive waveshape can be adjusted by 
external components. Other features of the 
device include thermal shutdown, a supply volt- 
age range of 4.75-46V and TTL-compatible 
inputs. 

The L5832 is supplied in a 12 + 2 + 2 - lead 
Powerdip package which uses the four center 
pins to conduct heat to the PC board copper. 




Powerdip 
12 + 2 + 2 



ORDERING NUMBER: L5832 



ABSOLUTE MAXIMUM RATINGS 



v s 


DC Supply voltage 


46 


V 


v 8 


(Positive transient voltage at pin 8) 


60 


V 


V en 


Enable input voltage (pin 11) 


7 


V 


Vj 


Input voltage (pin 10) 


7 


V 


Vr 


External reference voltage (pin 2) 


2 


V 


Pd 


Power dissipation (T case = 80°C) 


5 


W 


T stg , Tj 


Storage and junction temperature 


-40 to 150 


°C 



APPLICATION CIRCUIT USING ONE DARLINGTON 




V B AT 



555 



12/86 



L5832 



CONNECTION DIAGRAM 



BLOCK DIAGRAM 



HOLDING 
CURRENT 
CONTROL 

SENSING 
GND 
GNO 
CI 



PNP I 

OUTPUT I 



1 


KJ— 


16 


1 INTERNAL 
1 CLAMPING 


2 




15 


1 NPN 
1 OUTPUT 


3 




14 


| SUPPLY 
1 VOLTAGE 


U 




13 


j GND 


5 




12 


1 GND 


6 




11 


I INHIBIT 


7 




10 


1 INPUT 


8 




9 


1 REFERENCE 

I VOLTAGE 



INPUT - 
INHIBIT- 



CONTROL 
LOGIC 



TIME 

CONSTANT 

GENERATOR 



s 



REGULATOR 



nrrn 



*■ COMPARATOR *■ 



6] 7T9| 2] TT5 

R ref R 2 f R 1 



If n r«f R2 t R1 




THERMAL DATA 



^th j-case Thermal resistance junction-case 
R th i-amb Thermal resistance junction-ambient 



max 
max 



14 
80 



D C/W 



556 



L5832 



PIN FUNCTIONS 



NAME 



FUNCTION 



NC 



Not connected. Must be left open circuit. 



HOLDING CURRENT 
CONTROL 



A voltage applied to this pin sets the holding current 
level. If left open circuit an internal 75 mV reference is 
used and l h = l p /6. 



3 


SENSING 


Connection for load current sense resistor. Value sets the 
maximum load current. I p = 0.45/R s . 


4 


GROUND 


Ground connection. With pins 5, 12 and 13 conducts 
heat to printed circuit board copper. 


5 


GROUND 


See pin 4. 



C1 



A capacitor connected between this pin and ground sets 
the duration of the current peak (t2 in fig. 3). 
If left open, the switchmode control of the peak is 
suppressed. If grounded, the current does not fall to 
the holding level. 



DISCHARGE TIME 
CONSTANT 



A capacitor connected between this pin and ground sets 
the duration of t off (fig. 3). If grounded, switchmode 
control is suppressed. 



PNP DRIVING OUTPUT 



Current drive output for external PNP darlington (for 
recirculation). I = 35 l ref . 



REFERENCE VOLTAGE 



A resistor connected between this pin and ground sets 
the internal current reference, l ref . The recommended 
value is 1.2 kJ7, giving l ref = 1 mA. 



10 
11 



INPUT 



TTL-compatible input. A high level on this pin activates 
the output, driving the load. 



INHIBIT 



TTL-compatible inhibit input. A high level on this input 
disables the output stages and logic circuitry, irrespective 
of the state of pin 10. 



12 


GROUND 


See pin 4. 


13 


GROUND 


See pin 4. 


14 


SUPPLY VOLTAGE 


Supply voltage input. 


15 


NPN DRIVING OUTPUT 


Current drive for external NPN darlington (in series with 
the load). I = 100 l ref . 


16 


INTERNAL CLAMPING 


Internal zener clamp available for fast turnoff. 





557 



L5832 



ELECTRICAL CHARACTERISTICS 

otherwise specified. Refer to Fig. 2) 



(V, (pin 14) = 14V, T a , 



25°C, R r , 



1.2KA, unless 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V s Operating supply voltage (Pin 14) 




4.75 




46 


V 


l s Quiescent current (Pin 14) 


Vpinio = v pinll = Low State 




21 


40 


mA 


V ]n Input voltage (Pin 10) 


Low state 






0.8 


V 


V en Enable input voltage (Pin 11) 


High state 


2.4 






V 


lj n Input current (Pin 10) 


Low state 






100 


MA 


l en Enable input current (Pin 11) 


High state 






10 


ma 


V re f Internal reference voltage (Pin 9) 




1.2 


1.25 


1.3 


V 


'ref Reference current (Pin 9) 


'ref = V ref/ R ref 
R ref = 12KS2 






1300 


MA 


}p d Peak duration control current (Pin 6) 


'pel = 'ref' 8 


110 


130 


180 


MA 


tp d Peak duration time (Pin 6) 


tpd = C1 v th/!pd 

V th = 1.4V Ci = 4.7nF 




500 




MS 


l od Off duration control current (Pin 7) 


'od = 'ref' 8 


110 


130 


180 


ma 


t off Off duration time (Pin 7) 


tod = C2 v th"od 

V th = 1,4V C2 = 4.7nF 




50 




MS 


l dl NPN driving current (Pin 15) 


l dJ = 100 l ref (only present 
during charging phase) 


80 


100 


130 


mA 


l d2 PNP driving current (Pin 8) 


l d2 = 35 l ref 


28 


35 


48 


mA 


lp Peak current (emitter of IMPN 
Darlington) 


lp = 450mV/R sens 
Rsens = 0.ln 


4,2 


4.5 


4.8 


A 


V n Holding current control voltage 


v h = R sens 'h 
l n = Emitter 
current of NPN 
Darlington 


Pin 2 
Floating 


70 


75 


85 


mV 


Pin 2 externally 
biased 






2 


V 


Rj n Holding current control input 
impedance (Pin 2) 




100 


150 


200 


12 


r Peak to hold current ratio 


Pin 2 floating 




5.8 


6 


6.2 




Pin 6 shorted 


0.97 


1 


1.03 




l B Sense input bias current (Pin 3) 








100 


/jA 


V C | amp Internal clamping (Pin 16 to 15) 


I = 200,uA 


14 


16 


18 


V 


V dt Dump protection threshold voltage 
(Pin 1) 




28 


32 


34 


V 


R dt Dump protection threshold input 
impedance (Pin 1 ) 




22 


32 


42 


KO, 


Thermal drift of reference voltage 






0.5 




mV/°C 



558 



L5832 



APPLICATION INFORMATION 

The L5832 solenoid controller is intended for use with one or two external darlington transistors to 
drive inductive loads such as solenoids, relays, electric valves and DC motors. 

Controlled by a logic input and an inhibit input (both TTL compatible), the device drives the external 
darlington(s) to produce a load current waveform as shown in figure 3. This basic waveform shows that 
the device produces an initial current peak followed by a lower holding current. Both the peak and 
holding current levels are regulated by the L5832's switchmode circuitry. 

The duration of the peak, the peak current level and holding current level can all be adjusted by external 

components. 

Moreover, by omitting C1, C2 or both it is possible to realize single-level current control, a transitory 

peak followed by a regulated holding current or a simple peak (figure 1). 



Fig. 1 - Components connected to pins 6 and 7 determine the load current waveshape 



COMPONENTS ON 
PINS 6 AND 7 



LOAD CURRENT 
WAVEFORM 



X 



± 




^1 

1 I 

^Lb S-600 L ^^ 




!■ 





559 



L5832 



APPLICATION INFORMATION (continued) 

The peak current level l p , is set by the sensing resistor, R sens , and is found from: 



l„ 



0.45 



The holding current level, l h , is set by a voltage applied to pin 2. If this pin is left open circuit an in- 
ternal reference of 75 mV supervenes and the holding current is given by: 

I - 'p 
lh ~ 6 



Alternatively, this level may be varied by adding a divider to pin 2 (R1, R2) and suitable values are 
found from: 



max _ 



1 



R2//R in 



0.45V \ R1 + R2//R,, 



Vext + 



R2//R,, 



R x + R2//R,, 



Vx 



where Vx = 3V, Rx = 585017. R in = 150S2 (R in of pin 2) and V ext is the external voltage applied to the 
divider. 



Fig. 2 - Application circuit showing all the optional components. In particular it illustrates how the 
holding current level is adjusted independently of the peak current (with R1, R2, V ext ) and how the 
internal zener clamp is connected. This circuit produces the waveforms shown in Fig. 3. 



I (A) 


Q1 


Q2 


4 


BDX54 


BDX53 


8 


BDW94 


BDW93 


12 


BDV64 


BDV65 




INHIBITO— 



OV s 



L5832 



'REF/oj ^iREf [IF 

X J«REfJ_C2_L 




lREF/8 
5.6 



The drive currents for the two darlingtons and the waveform time constants are all defined by a refer- 
ence current, l ref , which is defined in turn by a resistor between pin 9 and ground. 

The recommended value for l ref is 1 mA which is obtained with a 1.2 kfi resistor. From l ref the dar- 
lington drive currents are given by: 

PNP : I = 35 l ref 

NPN : I = 100 l ref 

The duration of the high current level (t2 in figure 3) is set by a capacitor connected between pin 6 and 
ground. This capacitor, C1, is related to the duration, T, by: 

_ lref T 



C1 



12 



560 



L5832 



Fig. 3 - Waveforms of the typical application circuit of fig. 2. 



<I L ) 
Ip 

'ho 


. 


| ~T} 

/ 1 1 

/ ' ' 
/ 1 . 


r,+ - 




•%- 


i 


v, 






' 


COMPARATOR 


r 


t 1 


>'v 


y ' 


THRESHOLD 
(INTERNAL) 






1 








-60mV — — -A -r 


-r 


^ ! 


i ' > 


Q1 


„i J. 


! 




DRIVING 
CONDITION 




, 












Q2 

DRIVING 


100 


A 


J 


i'i 


i * 


CONDITION 
OFF 












































- ^ 


!>M 


, 



The discharge time constant (t off in figure 3) is set by a capacitor between pin 7 and ground and is found 
from: 

t _ 12C2 



The t off and t on times are also related to the current ripple, A I : 



t - LA I . t _ LA I 
toff - — n a nd ton - —r, 

V nff V nn 



where V off = V diode + V CEQ1 + R L l L 

V on = V s -V CEQ2 -V RS -R L l L 
L = load inductance 
R L = load resistance 
A I = load current ripple. 

Note that t off is the same for both the peak and holding currents. 



561 



L5832 



Fig. 4 - When pin 6 in grounded, as shown here, the load current is regulated at a single level. 



I (A) 


Q1 


Q2 


4 

8 

10 


BDX54 
BDW94 
BDV64 


BDX53 
BDW93 
BDV65 





Fig. 5 - In this application circuit, pin 6 is left open to give a single peak followed by a regulated holding 
current. 



•o(A) 


Q1 


Q2 


4 

8 

16 


BDX54 
BDX54 
BDW94 


BDX53 
BDX53 
BDV65 




- r ^).». 



I kz^ t*-- 



k i e ,6 
L 58.32 15 

7 ^ 5 12 13 3 



E^E 



RE F L RER8 
2 



1 o. - 




562 



L5832 



Fig, 6 - Switchmode control of the current can be suppressed entirely by leaving pin 6 open and ground- 
ing pin 7. The peak current is still controlled. 



I (A) 


Q1 


Q2 


4 

8 

10 


BDX54 
BDW94 
BDV64 


BDX53 
BDW93 
BDV65 




2 \l> 




15 


*^n 


L 5832 




15 


--^r- V^2 


6 3 7 


i 512 


13 3 


Jikh v 


1 JL : RE- 








K.fLO n REF 






Jb 



For fast turnoff an internal zener clamp is available on pin 16. 

This is used with an external divider, R8 R9, as shown in figure 2. Suitable values can be found from: 

Vpm is s 15V +V BEQ2 +VRsense 
R9 + R8 



V CQ2 - V pin 16 



R8 



(V CQ2 is the voltage at the collector of Q2). 

To ensure stability, a small capacitor (about 200 pF) must be connected between the base and collector 
of Q2 when pin 16 is used. 

For the application circuit of figure 7 t off == 12C2/l ref , as before, and the current ripple is given by: 

L In (l LP - A I) ■ R L + V L 



tnff ~~ 



i lp • R L +v L 



where V L is the voltage across the inductor during recirculation. 
Note that if the load is a motor V L = Eg + V D . 



563 



L5832 



Normally A I is a design parameter therefore C2 can be calculated directly from: 

- I ref • L ln(l LP -A I) R L +V L 



C2 : 



12R L 



Lp " r l + V L 



This application is particularly important because it allows the use of inductive loads with the lowest 
possible series resistance (compatible with constructional requirements) and therefore reduces notably 
the power dissipation. 

For example, an electric valve driven from 24V which draws 2A has a series resistance of 1257 and dissi- 
pates 48W. Using this circuit a valve with a 2fl series resistance can be used and the power dissipation is: 



where 



therefore: 



Pd = R L l L 2 +V D l L (1-6) +V sat • l L 5 +R S I L 2 5 

R L = resistance of valve = 2£2 
V D = drop across diode, V D = 1V 
Vsat = saturation voltage of Q2, = 1 V 
R s = R11 = 220 mil 
8 = duty cycle = 20% 



Pd 



8 + 1.6 +0.4 +0.16= 10.16W 



This given two advantages: the size (and cost) of the valve is reduced and the drive current is reduced 

from 2A to about 0.4A. 

The same consideration is also true for DC motors. 

Fig. 7 - Application circuit using only one darlington. The resistor and zener shown dotted activate the 
load when power is applied. 



skh^-sokh 



f~--o- 



P->* «";> 





564 



Fig. 8 - P.C. board and component layout of the circuit of fig. 7(1:1 scale) 



L5832 



R2 



\ 



D2 



r> n n n n n n n 



Q2 



15832 < R10 



uuu uuuuu' 
R5 



© ® ® © ® © 




© 



o 



o 

OND 

o o 

GND V, 



cc 



'BAT 



BAT ^ 

LOAD 



Fig. 9 - Application circuit showing how two separate supplies can be used. 



'O-T- 



^^~ 




565 



L5832 



The application circuit of figure 9 is very similar to figure 2 except that it shows the use of two supplies 
— one for the control circuit, one for the power stage. 

Choose R6 so that the voltage on pin 8 does not exceed 46V DC. This can be done simply bearing in 
mind that the pin 8 current is 35 l ref . 

R6 must not be too high if a very low supply voltage is used because: 

Vsmin = R6 • 16 +4.75 

therefore V smin = 750 • 35 • 1CT 3 +4.75 = 31V 

The zener diode DZ can not exceed 62V because when Q1 is off and DZ triggered - the fast recir- 
culation — the voltage on pin 8 may not exceed 60V. 



566 



^^^^^^® 



L6100 
L6101 
L6102 



ADVANCE DATA 



100V-1A, QUAD DMOS POWER SWITCH 



The L6100, L6101 and L6102 are DMOS quad 
transistor array realized with a new process called 
Multipower-BCD which allows the integration 
of multiple isolated DMOS transistors - plus 
bipolar linear and CMOS logic circuits on a 
single chip. 

Each of the four power DMOS transistors is a 
parallel combination of one thousand elementary 
cells with a packing density in excess of 1600 
cells/mm 2 . 

The device is assembled in three package: 12+3+3 
lead powerdip; 11 -lead Multiwatt® and 15-lead 
Multiwatt®. 



MultiPower BCD Technology 



Powerdip 12 + 3 + 3 

L6100 




Multiwatt-11 

L6101 



Multiwatt-15 
L6102 



ABSOLUTE MAXIMUM RATINGS 



V D s 


Drain-source voltage 


100 


V 


Vdgr 


Drain-gate voltage (R GS = 14Kfl) 


100 


V 


Vgs 


Gate-source voltage 


+ 14 to -0.6 


V 


Id 


Drain current 








— DC operation 


1 


A 




- Pulsed (300/js, 1%duty cycle) 


2.5 


A 


Tag. Tj 


Storage and junction temperature range 


-40 to +150 


C 



SCHEMATIC DIAGRAM 

[HI 




This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

567 12/86 



L6100 
L6101 
L6102 



CONNECTION DIAGRAMS 

(Top view) 

L6100 
(Powerdip) 



G2 
5 2 



1 

2 


\J 


18 
17 


3 




16 


U 




15 


5 




U 


6 
7 




13 
12 


a 




11 


9 




10 ' 



S4 
G4 



L6101 
(Multiwatt-11) 



L6102 

(Multiwatt-15) 



/^ 


1 


, <t> 


11 
10 
9 
8 
7 
6 
5 
u 

3 
2 
1 




/ 


: i } »j 








II 5 111 








II ■j s:t-s? 








II -> G 1 








^ 


II 3 ill 


/ " 








V -1 


J 




V 


II 3 1)1 








II } CI 








1 1 3 S4-S1 














\ 


II 3 1)4 


\ 


\ 





.Tab connected to pi n 6 




1^ 


~1 
















































































































T> 



03 

G 3 

S 3 

S 2 

G 2 

D 2 

N.C. 

GND 

N.C. 

D1 

G1 

S1 

S4 

G4 

04 



-Tab connected to pin 



THERMAL DATA 


Powerdip 


Multiwatt-11 


Multiwatt-15 


Rthj-amb Thermal resistance junction-ambient max 
f^thj-case Thermal resistance junction-case max 


65°C/W 
11°C/W 


35°C/W 
3°C/W 


35°C/W 
3°C/W 



568 



L6100 
L6101 
L6102 



ELECTRICAL CHARACTERISTICS (T ase = 25°C unless otherwise specified) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


BVqss Drain-source breakdown voltage 


@ l D = 1mA 
Vgs = OV 


100 






V 


Y<36 (TH) Threshold voltage 


<s> l D = 1mA 
Vqs = V DS 


2 




4 


V 


'gss Gate-source leakage 


<S> V GSS = 10V 






1 


MA 


Rqs (ON) Static drain-source on-state 
resistance 


@> V GS = 10V 
l D = 1A 






1.2 


n 



Fig. 1 - Saturation charac- 
teristics 





; : W yH 


i >^/^^ v 


■ ' \y<&^ 


\ i J&C^— 




/v^ 


6V 




yg>~- h — 






r 


5¥ 






^^ ' ' ' 



Fig. 2 - Normalized ON-re- 
sistance vs. temperature 





— 






I 






i 






















- 


/ 


— 












Iq = 0,5A 

I 































































2 3 



- 100 -50 50 100 T j CO 



Fig. 3 - Transconductance 
vs. drain current 




Fig. 4 - Capacitance vs. 
drain to source voltage 









I l 

! i 






I j 








I 














.... 


T — 


— 




















tiss 










j 








I 








c n „ 








c r , s 


■■ 

















569 



^^^^^^s> 



L6202 



ADVANCE DATA 



1.5A DMOS FULL BRIDGE DRIVER 



• POWER SUPPLY VOLTAGE UP TO 52V 

• TOTAL DC CURRENT UP TO 1.5A 

• LOW SATURATION VOLTAGE 

• LOW POWER DISSIPATION 

• NO CROSS CONDUCTION 

• TTL COMPATIBLE INPUTS 

• OVERTEMPERATURE PROTECTION 

Realized with mixed bipolar/CMOS/DMOS tech- 
nology, the L6202 is a full bridge driver for motor 
control applications. Delivering up to 1.5A 
output current at motor supply voltages up to 
52V, the device uses DMOS output transistors 
to obtain very high efficiency and fast switching 
speed. 

Each channel (half-bridge) of the device is con- 
trolled by a separate logic input, while a common 
enable input controls both channels. All inputs 
are TTL, CMOS and u,C-compatible. 



The L6202 is assembled in a Powerdip 12 + 3 + 3 
package an 18-lead DIP using the six center pins 
to conduct heat to the PCB. Thanks to the very 
high efficiency of the DMOS output stage no 
external heatsink is necessary, even when oper- 
ating at the full rated current and voltage. 



Multi Power BCD Technology 




Powerdip 12 + 3 + 3 



ORDERING NUMBER: L6202 



BLOCK DIAGRAM 



OUT 1 0UT2 

O O 

BOOT! i C BOOT 2 



f — Hh 



VOLTAGE 
REFERENCE 




CHARGE 
PUMP 






THERMAL 
SHUTDOWN 



"X 



i, 5, 6, 13, 14.15 



Note: suggested value for CgoOT 1 2 : 10 nF 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

571 12/86 



L6202 



ABSOLUTE MAXIMUM RATINGS 



*sens 
Ptot 
T stg- T j 



Power supply 

Input or enable voltage 

Peak output current 

— non repetitive 

— DC operation 
Sensing voltage 

Total power dissipation (J a 



Storage and junction temperature 



= 75°C) 





60 


V 




-0.3 to 7 


V 




5 


A 




1.5 


A 




-1 to 4 


V 




6 


W 




-40 to 150 


°C 



CONNECTION DIAGRAM 

(Top view) 









w 




SENSE 




1 




18 


ENABLE [ 


2 




17 


N.C. 




3 




16 


GNO 




4 




15 


GND 




5 




U 


GND 


[ 


6 




13 


N.C. 


[ 


7 




12 


OUT 2 


[ 


8 




11 


V S 


[ 


9 




10 



"REF 

BOOT 2 

IN 2 

GNO 

GND 

GNO 

INI 

BOOT1 

OUT1 



THERMAL DATA 



'th j-plns 
^thj-amb 



Thermal resistance junction-pins 
Thermal resistance junction-ambient 



max 
max 



12 
65 



C/W 
°C/W 



572 



L6202 



PIN FUNCTIONS 



11 



17 



NAME 



SENSE 



ENABLE 



NOT CONNECTED 



GROUND 



BOOT 1 



BOOT 2 



FUNCTION 



A resistance R^k,, connected to this pin, allows motor 
current control. 



Enable Input. 

A logic low level on this pin switches off the DMOS 

POWER transistors. 



Common ground terminal. 



5 


GROUND 


Common ground terminal. 


6 


GROUND 


Common ground terminal. 


7 


NOT CONNECTED 




8 


OUT 2 


Output of the half bridge. 


9 


V s 


Supply voltage. 


10 


OUT 1 


Output of the half bridge. 



A capacitor C BOOT 2 , connected to this terminal allows 
the upper DMOS transistor driving for high switching 
frequencies. 



12 


IN 1 


Input from the controller device. 


13 


GND 


Common ground terminal. 


14 


GND 


Common ground terminal 


15 


GND 


Common ground terminal. 


16 


IN 2 


Input from the controller device. 



A capacitor Ce OOT 2, connected to this terminal, allow 
the upper DMOS transistor driving for high switching 
frequencies. 



Internal reference voltage. 



573 



L6202 



ELECTRICAL CHARACTERISTICS |V S = 42V, t = 25°C) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V s Supply voltage 


Operating condition 


12 (*) 




52 


V 


V re f Reference voltage 






10.5 




V 


l s Quiescent supply current 


V E N= H V m = L 




7 




mA 


l L =0 V IN =H 




7 




V EN = L 




6 




V|mL Input low voltage 




-0.3 




0.8 


V 


V| N H Input high voltage 




2 




7 


V 


Vi^jL Input low current 








-10 


MA 


l|[SjH Input high current 






30 




/rA 


V^rslL Enable low voltage 




-0.3 




0.8 


V 


VgfsjH Enable high voltage 




2 




7 


V 


lr£rs|l- Enable low current 








-10 


MA 


Ir^isjH Enable high current 






30 




mA 


R DS (ON) 






0.3 




S2 


^'DS(sat) Saturation voltage 


l L = 1A 




0.3 




V 


l L = 1.2A 




0.45 




t^ (Vj) Source current turn-off delay 






300 




ns 


t? (Vj) Source current fall time 






200 




ns 


t3 (Vj) Source current turn-on delay 






400 




ns 


t £i (Vj) Source current nse time 






200 




ns 


t^ (V,l Sink current turn-off delay 






300 




ns 


\q (Vj) Sink current fail time 






200 




ns 


ty (Vj) Sink current turn-on delay 






400 




ns 


t & (Vj) Sink current rise time 






200 




ns 


F c Commutation frequency 


L = 1.2A 




50 


100 


KHz 



(*) If V s -i 12V, V ref = V s -2V B 



574 



L6202 



CIRCUIT OPERATION 



The L6202 is a monolithic full bridge switching 
motor driver realized in the new Multipower- 
BCD technology which allows the integration 
of multiple, isolated DMOS power transistors 
plus mixed CMOS/bipolar control circuits. 

The power stage of the L6202 consists of four 



N-channel DMOS transistors with an R 



DS (ON) 



= 0.3ST2 over whole current range. Each tran- 
sistor has an intrinsic drain-source diode. During 
recirculation the behaviour of these diodes 
depends on the operating mode. 

When one of the POWER DMOS transistor is 
ON it behaves almost symmetrically in terms of 
current - like, in fact, a resistor with the value 



^ds (on; 



in parallel with the drain-source diode. 

During recirculation with the ENABLE input 
high, the voltage drop across the transistor is 
Rds (on) x 'l for voltages less than 0.7V and is 
clamped at a voltage depending on the charac- 
teristics of the diode for greater voltages. 

When the ENABLE input is low, the POWER 
MOS is OFF and the diode carry the whole 
recirculation. 

Although the device guarantees the absence of 
cross-conduction, the presence of the intrinsic 
diodes in the POWER DMOS structure causes 
the generation of current spikes on the sensing 
terminals due to charge-discharge phenomena in 
the capacitors C1 & C2 associated with the 
drain source junctions (Fig. 1 ). When the output 
switches from high to low a current spike is 
generated associated with the capacitor C1. On 
the low-to-high transition a spike of the same 
polarity is generated by C2, preceded by a spike 
of the opposite polarity due to the charging of 
the input capacity of the lower POWER DMOS 
transistor. (Fig. 2) 

To ensure that the POWER DMOS transistors 
are driven correctly a gate-source voltage of 
about 10V must be guaranteed for all of the 
N-channel DMOS transistors. While there is no 
problem in driving the lower POWER DMOS 
devices (their source terminals are referred to 
ground) it is necessary to provide a gate voltage 
higher than the positive supply for the upper 
transistors because they have the drain connected 
to the supply itself. 

This obtained by a system that combines a 
charge pump circuit, which assures correct DC 
operation, with a boostrapping technique suit- 
able for high switching frequencies. 



In the boostrap circuit the external Cg capacitors 
are charged to a voltage of about 10V when the 
upper power transistor is OFF and the lower one 
is ON. To guarantee efficient driving of the upper 
power transistor in the conduction condition the 
value of C B must be greater than the value of the 
input capacitance, C| N , of the power transistor 
itself. Since the estimated value of the input ca- 
pacity is about InF, C B should be > = 10nF 
to guarantee correct operation. 

An ON-OFF synchronisation circuit provides a 
dead time (the period in which all four power 
transistors are OFF) of 40ns, sufficient to 
prevent simultaneous conduction with obvious 
advantages in terms of power dissipation and of 
spurious signals on the ground and in the sensing 
resistors. 

A thermal protection circuit has been included 
that will disable the device if the junction tem- 
perature reaches 150°C. When the temperature 
has fallen to a safe value the device restarts 
under the control of the input and enable signals. 

Fig. 1 - Intrinsic structures in the POWER DMOS 
transistors i> 



r; * j" 



— O v out 



-'-1=1 f *■ 

r-y- - 



Fig. 2 - Current typical spikes on the sensing pin 



V 5 = 42V 
l p: =0.5A 
T = 100ns 





575 



L6202 



Fig. 3 - Rds(on) vs - tem- 
perature typical values 



Fig. 4 - Quiescent current 
vs. frequency 



DSlon) 

(ill 






















































1.5 - 
























v &s =iov 






^_\ 








J 






~* 


1 - 














t~~ 





















■s I 

.0 ■ L 1 — -i- — > ■ f— — 



-50 -25 25 50 75 100 125 TCC) 

' Normalized at 25°C 



50 



150 200 f 



SWITCHING TIMES TEST CIRCUITS 

Fig. 5 - Source current delay times vs. input or enable chopper 

v^42v 



It 1L 




90-/. 



L R=35A 
T 10"/. 



•J£ 



'3 )U' 




NOTE: for INPUT chopper SET EN = H 



Fig. 6 - Sink current delay times vs. input or enable chopper 

v s ^i2V 

R-3SA 




NOTE: for INPUT chopper SET EN = H 



576 



L6202 



Fig. 7 - Bidirectional DC motor control 



,J~L » 




:tt 





INPUTS 


FUNCTION 


Ven = 


H 


IN1 = H 


IN2= L 


Turn r ; ght 


IN1 = L 


IN2 = H 


Turn left 


IN1 = IN2 


Fast motor stop 


Ven = 


L 


IN1 = X 


IN1 = IN2 


Free running motor stop 



H = High 



X = Don't care 



Fig. 8 - Application circuit 



XT 



GNOT 



C W-'CWW 

C LOCK | 

H AL f F ULL 

rese t > 

ENABLE 



2 16 ■! 



♦ v s 


9 




11 


i " 1 IBnF 


1 


12 
16 




10 


°L tl B 


1 , -. 


I 
1 


L6202 


e 


02 


^ - ' r 




_B 1 | 

1NH1 ! ' 




4.5,6. UK 


s 


"i" 






1 








CONTROL SYNC HOME 



577 



^^^^^^^^r<$ 



L6203 



ADVANCE DATA 



3A DMOS FULL BRIDGE DRIVER 



OPERATING SUPPLY VOLTAGE UP TO 
52 V 

TOTAL DC CURRENT UP TO 3A 

LOW SATURATION VOLTAGE 

LOW POWER DISSIPATION 

NO CROSS CONDUCTION 

TTL COMPATIBLE INPUTS 

OVER TEMPERATURE PROTECTION 



Realized with mixed bipolar/CMOS/DMOS tech- 
nology, the L6203 is a full bridge driver for 
motor control applications. Delivering up to 3A 
output current at motor supply voltages up to 
52V, the device uses DMOS output transistors to 
obtain very high efficiency and fast switching 
speed. 



Each channel (half-bridge) of the device is con- 
trolled by a separate logic input, while a common 
enable input controls both channels. All inputs 
are TTL, CMOS and MC-compatible. 

The L6203 is assembled in a 1 1 -lead Multiwatt® 
package. 



Multi Power BCD Technology 




& 



Multiwatt-11 



ORDERING NUMBER: L6203 



BLOCK DIAGRAM 



ENABLE 

11 



OUT 1 0UT2 
9 9 



VOLTAGE 
REFERENCE 



".h 



=fD-D> 



* 



=f€>C^ 



THERMAL 
SHUTDOWN 




CHARGE 
PUMP 



H^fCfi 



KKt- 



6_L GNO 



IN 2 
7 



(*) Suggested value for C b qoti an ^ CboOT2 : 10nF 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 



579 



12/86 



L6203 



ABSOLUTE MAXIMUM RATINGS 



V 5 


Power supply 


60 


V 


Vin, Ven 


Input or enable voltage 


-0.3 to 7 


V 


lo 


Output current 








— peak non repetitive 


5 


A 




— DC operation 


3 


A 


Vsens 


Sensing voltage 


-1 to 4 


V 


^tot 


Total power dissipation (T case = 75 C) 


25 


W 


T stg- Tj 


Storage and junction temperature 


-40 to 150 


u c 



CONNECTION DIAGRAM 

(Top view) 




3 



ENABLE 
SENSE 
V REF 
BOOT. 2 
IN 2 
GNO 
IN1 

BOOT. 1 
OUT 1 

V S 
OUT 2 



Tab connected to pin 6 



THERMAL DATA 



Mh J-case 
Mh j-amb 



Thermal resistance junction-case 
Thermal resistance junction-ambient 



max 
max 



3 
35 



°C/W 

°c/w 



580 



L6203 



PIN 


FUNCTIONS 




N° 


NAME 


FUNCTION 


1 


OUT 2 


Output of the half bridge. 


2 


V s 


Supply voltage. 


3 


OUT 1 


Output of the half bridge. 



BOOT. 1 



BOOT. 2 



A capacitor C B i, connected to this terminal allows the 
upper DMOS transistor driving for high switching fre- 
quencies. 



5 


IN 1 


Input from the controller device. 


6 


GND 


Common ground terminal. 


7 


IN 2 


Input from the controller device. 



A capacitor C B2 , connected to this terminal allows the 
upper DMOS transistor driving for high switching 
frequencies. 



9 
10 



Internal reference voltage. 



SENSE 



A resistance Rsense- connected to this terminal, allows 
motor current control. 



11 



ENABLE 



Enable input. 

A logic low level on this pin switches off the DMOS 

power transistors. 



581 



L6203 



ELECTRICAL CHARACTERISTICS <V 5 = 42V, T, = 25°C) 



Parameter 


Test Conditions 


Mvn. 


Typ. 


Max. 


Unit 


V s Supply voltage 


Operating condition 


12 (*) 




52 


V 


V re f Reference voltage 






10.5 




V 


l s Quiescent supply current 


v E n=h v in =l 




7 




mA 


l L =0 V IN =H 




7 




V EN = L 




6 




V|(sj L Input low voltage 




-0.3 




0.8 


V 


V|jsjH Input high voltage 




2 




7 


V 


V|f^L Input low current 








-10 


MA 


l||\jH Input high current 






30 




ma 


V^n L Enable low voltage 




-0.3 




0.8 


V 


VenH Enable high voltage 




2 




7 


V 


IeisjL Enable low current 








-10 


ma 


IejsjH Enable high current 






30 




ma 


R DS (ON) 






0.3 




n 


^OS (sat) Saturation voltage 


l L = 1A 




0.3 




V 


l L = 3A 




0.9 




ti (Vj) Source current turn-off delay 






300 




ns 


t 2 (Vj) Source current fall time 






200 




ns 


t3 (Vj) Source current turn-on delay 






400 




ns 


t4 (Vj) Source current rise time 






200 




ns 


t5 (Vj) Sink current turn-off delay 






300 




ns 


t 6 (Vj) Sink current fall time 






200 




ns 


X-/ (Vj) Sink current turn-on delay 






400 




ns 


t 8 (Vj) Sink current rise time 






200 




ns 


F c Commutation frequency 


l L = 3A 




50 


100 


KHz 



(*) If V s < 12V, V ref = V S -2V BE 



582 



L6203 



CIRCUIT OPERATION 

The L6203 is a monolithic full bridge switching 
motor driver realized in the new Multipower- 
BCD technology which allows the integration of 
multiple, isolated DMOS power transistors plus 
mixed CMOS/bipolar control circuits. 

The power stage of the L6203 consists of four 
N-channel DMOS transistors with an R DS (ON) 
= 0.3fi over the whole current range. Each 
transistor has an intrinsic drain source diode. 
During recirculation the behaviour of these 
diodes depends on the operating mode. 

When one of the POWER DMOS transistors is 
ON it bahaves almost symmetrically in terms 
of current like, in fact, a resistor with the value 
Rds (on) i n parallel with the drain-source diode. 

During recirculation with the ENABLE input 
high, the voltage drop across the transistor is 
R DS (ON) x l L for voltages less than 0.7V and 
is clamped at a voltage depending on the charac- 
teristics of the diode for greater voltages. 

When the enable input is low, the POWER MOS 
is off and the diode carry the whole recirculation. 

Although the device guarantees the absence of 
cross-conduction, the presence of the intrinsic 
diodes in the POWER MOS structure causes 
the generation of current spikes on the sensing 
pin due to charge-discharge phenomena in the 
reverse capacitor, C1 & C2 associated with the 
drain-source junctions (Fig. 1). When the output 
switches from high to low, a current spike is 
generated associated with the capacitor C1. On 
the low-to-high transition, a spike of the same 
polarity is generated by C2, preceded by a 
spike of the opposite polarity due to the charging 
of the input capacity of the lower POWER 
DMOS transistor (Fig. 2). 

To ensure that the POWER DMOS transistors are 
driven correctly a gate-source voltage of about 
10V must be guaranteed for all of the N-channel 
DMOS transistors. While there is no problem in 
driving the lower POWER DMOS devices (their 
source terminals are referred to ground) it is 
necessary to provide a gate voltage higher than 
the positive supply for the upper transistors 
because they have the drain connected to the 
supply itself. 

This is obtained by a system that combines a 
charge pump circuit, which assures correct DC 
operation, with a boostrapping technique suit- 
able for high switching frequencies. 

In the boostrap circuit the external C B capa- 
citors are charged to a voltage of about 10V 
when the upper power transistor is OFF and the 



lower one is ON. To guarantee efficient driving 
of the upper power transistor in the conduction 
condition, the value of C B must be greater than 
the value of the input capacitance, Cin, of the 
power transistor itself. Since the estimated value 
of the input capacity is about 1nF, C B should 
be > = 10nF to guarantee correct operation. 

An ON-OFF synchronization circuit provides a 
dead time (the period in which all four power 
transistors are OFF) of 40ns, sufficient to pre- 
vent simultaneous conduction with obvious 
advantages in terms of power dissipation and 
of spurious signals on the ground and in the 
sensing resistors. 

A thermal protection circuit has been included 
that will disable the device if the junction tem- 
perature reaches 150 C. When the temperature 
has fallen to a safe value the device restarts 
under the control of the input and enable signals. 

Fig. 1 - Intrinsic structures in the POWER DMOS 
transistors v. 




Fig. 2 - Typical current spikes on the sensing pin 




583 



L6203 



Fig. 3 - R DS (ON) vs. tem- 
perature _„ , 







1 

.4 




































\ y 






»»-'"" 




^y 






r\ 





























-SO -25 25 50 ?S 100 125 H'Cl 

* Normalized at 25°C 



Fig. 4 - Quiescent current 
vs. frequency s _,„ 






bO 100 150 200 I [I 



SWITCHING TIMES TEST CIRCUITS 

Fig. 5 - Source current delay time vs. input or enable chopper 




, 


IL 










'maxi3A 
90% 


r^ 


\ 




/ 


t — 


4fl 




\ 




/ 




10'/. 




-^ 


k ~7 


' 




v in 


i' 1 


'2 


<3 


u 


1 ^- 

1 


{- 




1!— 






50'/. 


--> 




^- 



NOTE: for INPUT chopper SET EN = H 



Fig. 6 - Sink current delay time vs. input or enable chopper 

9 „ ,,„ 



IN C 
ENC 



11L 




1/2 
L6203 



l mi ,=3A 
90'/. 



'6 



•7 



i 



NOTE: for INPUT chopper SET EN = H 



584 



L6203 



Fig. 7 - Bidirectional DC motor control 



_TL -^ 



,_r 




:i_r 



INPUTS 


FUNCTION 


V E N = 


= H 


IN1 = H 


IN2 = L 


Turn right 


INI = L 


IN2 = H 


Turn left 


IN1 = IN2 


Fast motor stop 


Ven = 


= L 


IN1 = X 


IN1 = IN2 


Free running motor stop 



H = High 



X = Don't care 



Fig. 8 - Application circuit 



GNOP 



CWCWW 
CLOCK 



RESET | 

ENABLE 



I '6 12 



20 L.297 



.X 



"!?£ a 



1 



i R " 



"X, 



CONTROL SYNC HOME 



585 



^^^^^^s 



L6207 



ADVANCE DATA 



DUAL FULL BRIDGE DRIVER 



• POWER SUPPLY VOLTAGE UP TO 46V 

• LOW SATURATION VOLTAGE 

• OVERTEMPERATURE PROTECTION 

• LOGIC "0" INPUT VOLTAGE UP TO 1.5V 
(HIGH NOISE IMMUNITY) 

The L6207 is an integrated monolithic circuit 
in a 15-lead multiwatt package. It is a high cur- 
rent dual full-bridge driver designed to accept 
standard TTL logic levels and drive inductive 
load such as relays, solenoids, DC and stepper 
motors. 

Two inhibit inputs are provided to disable the 
device independently of the input signals. The 



emitters of the lower transistors of each bridge 
are connected togheter and the corresponding 
external terminal can be used for the connection 
of an external sensing resistor. An additional 
supply input is provided so that the logic works 
at a lower voltage. 







Multiwatt 15 



ORDERING NUMBER: L6207 



BLOCK DIAGRAM 




This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

587 12/86 



L6207 



ABSOLUTE MAXIMUM RATINGS 



V s 


Power supply 


50 


V 


Vss 


Logic supply voltage 


7 


V 


v„ v EN 


Input and enablet voltage 


0.3 to 7 


V 


"o 


Peak output current (each channel) 








— non repetitive (t = IOOjUs) 


1.8 


A 




- repetitive (80% on 20% off; t on = 10ms) 


1.5 


A 




— DC operation 


1.25 


A 


''sens 


Sensing voltage 


-1 to 2.3 


V 


Pfot 


Total power dissipation (T ase = 75°C) 


25 


W 


T stg. T i 


Storage and junction temperature 


-40 to 150 


u c 



CONNECTION DIAGRAM 

(Top view) 




CURRENT SENSING B 

OUTPUT 4 

OUTPUT 3 

INPUT4 

ENABLE B 

INPUT 3 

LOGIC SUPPLY VOLTAGE Vce 

GROUND 

INPUT 2 

ENABLE A 

INPUT 1 

SUPPLY VOLTAGE V s 

OUTPUT 2 

OUTPUT I 

CURRENT SENSING A 



-Tab connected to pin8 



THERMAL DATA 



'th J-case 



Thermal resistance junction-case 
Thermal resistance junction-ambient 



max 
max 



3 
35 



C/W 

°c/w 



588 



L6207 



Fig. 1 - Switching times test circuit Fig. 1a - Source current delay times vs. input chopper 



V SS =5V V S =«V 

? ? 



INPUT 
O 



ENABLE 
O 




R L -.33A 



1 



Vj (4V) 
50*/. 




r 



note: For INPUT chopper, set EN = H 



Fig. 2 - Switching time test circuits 



"SS.5V % = "" 




R L =33A 



Fig. 2a - Sink current delay times vs. input chopper 
! l A 





.- -_>> 


, 


s 






\ 


/ 




■ 




V J 


t 




T5 


T6 




T7 


T6 


















50*/. - 


± N 


\ 


*■ 



note: For INPUT chopper, set EN = H 



589 



L6207 



E LECTRICAL CHARACTERISTICS (For each channel, V s = 42V, V ss = 5V), T, = 25°C) 









s -J" 1, 


j 


>w 


Parameter 


Test Conditions 

Operative condition 


Min. 

Vj H + 2.5 


Typ. 


Max. 


Unit 


V s Supply voltage (pin 4) * 


46 


V 


V ss Logic supply voltage (pin 9) 




4.5 




7 


V 


l 5 Quiescent supply current 
(pin 4) 

(1) 


V EN = H V, = L 




3 


7 


mA 


'L = V, = H 




15 


20 


mA 


Ven = L 







1 


mA 


I ss Quiescent current from V ss 
(pin 9) 

(1) 


V EN = H Vj = L 


5 


10 


mA 


>L = Vj = H 




1.5 


3 


mA 


Ven = L 




1 


1.5 


mA 


Vj (_ Input low voltage 
(pins 5, 7, 10, 12) 




-0.3 




1.5 


V 


Vj H Input high voltage 
(pins 5, 7, 10, 12) 




2.3 




v ss 


V 


!j [_ Low voltage input current 
(pins 5, 7, 10, 12) 


Vj = L 






-10 


MA 


I; |_) High voltage input current 
(pins 5, 7, 10, 12) 


V, = H < V ss - 0.6V 




30 


100 


mA 


Veim l Enable low voltage 
(pins 6, 11 




-0.3 




1.5 


V 


V EN H Enable High voltage 
(pins 6, 11) 




2.3 




Vss 


V 


Ienl Low voltage enable current 
(pins 6, 11) 


V EN = L 


-10 


MA 


l E IM h High voltage enable current 
(pins, 6, 11) 


Ven = H < V ss -0.6V 




30 


100 


mA 


VcE(sat) H Source saturation voltage 


l L = 1.25A 
l L = 1.25A 


— 


1.5 

1.5 


2.3 


V 


VcE(sat)L Sink saturation voltage 


2.3 


V 


v CE(sat) Total drip 


l L = 1.25A 






4.4 


V 


V sens Sensing voltage (pins 1,15) 


0.5 Vj to 0.9 l L (**) 


-1 (*) 




2 


V 


T1 (Vj) Source current turn off delay 




1.7 




MS 


T2 (V f ) Source current fail time 


0.9 l L to 0.1 l L (**) 




0.2 




MS 


T3 (Vj) Source current turn on delay 


0.5 V, to 0.1 l L (**) 
0.1 l L to 0.9 l L (**) 




2.5 




MS 


T4 (Vj) Dource current rise time 




0.35 




MS 



590 



L6207 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


T5 (V|) 


Sink current turn-off delay 


0.5 V, to 0.9 l L (***) 




0.7 




MS 


T6 (V,) 


Sink current fall time 


0.9 l L to 0.1 l L (***) 




0.2 




MS 


T7 (V,) 


Sink current turn on delay 


0.5 V, to 0.1 l L (***) 
0.1 l L to 0.9 l L (***) 




1.5 
0.2 




MS 


T8 (V,) 


Sink current rise time 




MS 


fc 


Commutation frequency 


l L = 1.25A 




25 


40 


KHz 



(*) Sensing voltage can be -1V for t < 50ms; in steady state V sen smin > -0.5V; (**) See fig. 1a; (***) See fig. 2a 

(1 ) The value of the current is related to only one channel 

• The correct sequence for power on is: 1. V s5 ON with EN = L for power off is : 1. EN = L 

2. V s ON 2. V s ON 

3. EN = H 3. V ss OFF 



Fig. 3 - Bidirectional DC motor control 
,v s 




TO CONTROL 
CIRCUIT 



TRUTH TABLE 





INPUTS 


FUNCTION 


Ven = 


= H 


C = 


H D = 


L 


Turn right 


c = 


L D = 


H 


Turn left 


c = 


D 




Fast motor stop 


V E N = 


L 


c = 


X D = 


X 


Free running motor stop 



Low 



H = High 



Don't care 



591 



L6207 



Fig. 4 - Two phase bipolar stepper motor control circuit 

This circuit drives bipolar stepper motors with winding currents up to 1.25A. 
The diodes are fast 1 A types. 

rr n^ u q 36v 



3.3 nF H 
GNP|~ | 

CW/CCW 



CLOCK 
HALF/FULL 



L297 



^Li 



a a n a 




STEPPER 

MOTOR 

WINDINGS 



K 51 K 52 

D1 toD8 = 2AFAST DIODES 



Fig. 5 - Suggested printed circuit board layout for the circuit of fig. 4 (1.1 scale) 



UJO p I* 
o 7 -e. < y js ,YX — — o 



GS 



6 6 6Td 

02 03 Ot V<-,&ND 




- — ^v— ■ 


3 

6 , ': 




.? : ?■ ■■;: 


% 


': :: N :: 


j( "teKii 




XT 



592 



^^^^^^® 



L6209 



ADVANCE DATA 



3A FULL BRIDGE DRIVER WITH DIODES 



• SUPPLY VOLTAGE UP TO 46V 

• OUTPUT CURRENT UP TO 3A (4A PEAK) 

• SEPARATE CONNECTIONS FOR SUPPLIES 
AND DIODES 

• CONNECTION FOR EXTERNAL SENSE 
RESISTOR 

• LOW SATURATION VOLTAGE (3.5V TYP 
AT 3A) 

• THERMAL SHUT DOWN WITH HYSTER- 
ESIS 

• MP COMPATIBLE LOGIC INPUTS W'TH 
HIGH NOISE IMMUNITY 

• LOW LEAKAGE FAST RECOVERY DIODES 

• NO CURRENT FROM HIGH VOLTAGE 
SUPPLIES WHEN ENABLE PIN IS LOW 



The L6209 is a high voltage, high current full- 
bridge driver with internal fast recovery diodes. 

The cathodes of the upper recirculation diodes 
and the anodes of the lower ones are externally 
available to allow flexibility in application. 

The device is designed to accept standard TTL 

logic levels and drive inductive loads such as 

relays, solenoids, DC motors and stepping 
motors. 



An enable input allows all four transistors of 
the bridge to be switched off independently 
of the input commands. 

Each half bridge can be connected to an ex- 
ternal sense resistor and have a separate high 
voltage supply. 

An additional supply input is provided so that 
the logic can operate at a lower voltage, reducing 
dissipation. 

The device is equipped with a thermal protection 
which, switches off the input and output stages 
when the temperature reaches 150°C and switches 
on with hysteresis when the temperature de- 
creases. 

Another important feature is the switching 
speed (less than 1.5ns). 

The L6209 is supplied in a 15-lead Multiwatt® 
package. 




4*N 



Multiwatt-15 



ORDERING NUMBER: L6209 



BLOCK DIAGRAM 



X-k 



OUT I OUT J >->H2 

9 9 9 



LOGIC 
SUPPLY 

VOLTAGE REG. 



;^x 




T 



6 

dl2 sense; 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

593 12/86 



L6209 



ABSOLUTE 


MAXIMUM RATINGS 






Vsi- V S2 


Power supply 


46 


V 


Vss 


Logic supply voltage 


7 


V 


V|N» ^EN 


Input and enable voltage 


-0.3 to 7 


V 


lo 


Peak output current 








— non repetitive (t = 100jUs) 


5 


A 




- repetitive (80% on -20% off; t on = 10ms) 


4.5 


A 




— DC operation 


4 


A 


^sens 


Sensing voltage 


-1 to 2.3 


V 


Ptot 


Total power dissipation (T^ = 75°C) 


25 


W 


T stg. T j 


Storage and junction temperature 


-40 to 150 


"C 


Vqh 


Maximum recirculation voltage 


46 


V 



CONNECTION 

(Top view) 



DIAGRAM 




1 V 


-5 


LOWER OIOOE I 






















"3 


























V S2 










IN 2 








-s 












■3 














V SS 






















V S1 










UPPER OIOOE 1 
































3 


LOWER DIODE 1 



-Tab connected to pin 



THERMAL DATA 



'th j-case 
">th j-amb 



Thermal resistance junction-case 
Thermal resistance junction-ambient 



max 
max 



3 
35 



°C/W 

°c/w 



594 



L6209 



Fig. 1 - Switching times test circuits 

? ? 




Note: For INPUT chopper, set EN = H 



Fig. 1a - Source current delay times vs. input chopper 



ImaxOA) -j— 
90'/. -|- - 



Vj (5V) 
507. 




£ 



Fig. 2 - Switching times test circuits 




Note: For INPUT chopper, set EN = H 



Fig. 2a - Sink current delay times vs. input chopper 

'Li 



90 •/. - L - 



V| (5V> 
50 V. 




?L 



Fig. 3 - Switching times test circuits 




Note: For enable chopper in this 

configuration, set, INPUT = H 



Fig. 3a - Source current delay times vs. enable chopper. 



Imax(3A) 
90*/. 





Til T!2 



■£. 



595 



L6209 



Fig. 4 - Switching times test circuits 

9 9 




Note: For enable chopper in this 
configuration, set INPUT = L 



Fig. 4a - Sink current delay times vs. enable chopper 




ELECTRICAL CHARACTERISTICS (for each channel, V s = 


42V, V ss = 5V, Tj = 25° C) 


Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V s Supply voltage (pin 5, 11) 


Operative condition 


9 




42 


V 


V ss Logical supply voltage (pin 7) 




4.5 




5.5 


V 


l s Quiescent supply current 
(pin 5, 11) 


V EN = H V| N = L 
li = 







1 


mA 


V| N = H 




3 


10 


V EN = L 







1 


l ss Quiescent current from V S5 
(pin 7) 


Vein = H V !N = L 




40 




mA 


V| N = H 




20 




Ven = L 




7 




V|n |_ Input low voltage (pins 10, 6) 




-0.3 




0.8 


V 


Vjn h Input high voltage (pins 10, 6) 




2 




Vss 


l|l\ll_ Low voltage input current 
(pins 10,6) 


Vin = L 




-20 


-50 


MA 


IjfMH High voltage input current 
(pins 10,6) 


V|N = H 






50 


Ven l Enable low voltage (pin 9) 




-0.3 




0.8 


V 


V Ei si h Enable high voltage (pin 9) 




2 




Vss 


'en L Low voltage enable current 
(pin 9) 


Ven = L 




-20 


-50 


MA 


l E N H High voltage enable current 
(pin9) 


Ven = H < V S5 






50 


VcEsat(H) Source saturation voltage 


l L = 1A 




1.1 




V 


l L = 3A 




2 





596 



L6209 



ELECTRICAL CHARACTERISTICS (continued) 


Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


VcE sat (L) Saturation voltage 


l L = 1A 




1 




V 


l L = 3A 








v CEsat Totai dr °P 


l L = 1A 




2.1 


3 


V 


l L = 3A 




.3.5 


4.5 


Vp Diode forward voltage drop 


lo = 1A 




1 




V 


lo = 3A 




1.5 




t rr Diode reverse recovery time 


If = 1A dl f /dt = -50A/ms 
l RM = 2.5A V R = 42V 




100 




ns 


tf r Diode forward recovery time 


If = 1A dlf/dt = lOOA/us 
Measured at V F = 1V 




100 




ns 


T1 (V|n) Source current turn-off delay 


0.5 Vj to 0.9 l L (2) 




750 




ns 


T2 < V | rxj ) Source current fall time 


0.9 l L to 0.1 l L (2) 




430 




ns 


T3 (V[(s() Source current turn-on delay 


0.5 V, to 0.1 l L (2) 




1.1 




U.S 


T4 (V| N ) Source current rise time 


0.1 l L to0.9 l L (2) 




500 




ns 


T5 (V|n) Sink current turn-off delay 


0.5 V, to 0.9 l L (3) 




700 




ns 


T6 (V|rs|) Sink current fall time 


0.9 l L to 0.1 l L (3) 




500 




ns 


T7 (V|rvj) Sink current turn-on delay 


0.5 V, to 0.1 l L (3) 




950 




ns 


T8 (V| N ) Sink current rise time 


0.1 l L to 0.9 l L (3) 




400 




ns 


T9 (V|r\j) Source current turn-off delay 


0.5 V, to 0.9 l L (4) 




450 




ns 


T10 (V| N ) Source current fall time 


0.9 l L to 0.1 l L (4) 




250 




ns 


T1 1 (V|pg) Source current turn-on delay 


0.5 V, to 0.1 l L (4) 




550 




ns 


T12 (V|j\j) Source current rise time 


0.1 l L to 0.9 l L (4) 




250 




ns 


T13 (V|r\|) Sink current turn-off delay 


0.5 Vj to 0.9 l L (5) 




350 




ns 


T14 (V ]N ) Sink current fall time 


0.9 l u to 0.1 l L (5) 




200 




ns 


T15 (V|r\i) Sink current turn-on delay 


0.5 V, to 0.1 l L (5) 




800 




ns 


T16 (Vifvj) Sink current rise time 


0.1 l L to 0.9 l L (5) 




200 




ns 


f c Commutation frequency 


l L = 3A 




35 


60 


KHz 



NOTE : (1 ) Sensing voltage can be -1 V for t < 50ms; in steady state V sens min > -0.5V 

(2) See fig. la. (INPUT chopper) 

(3) See fig. 2a. (INPUT chopper) 

(4) See fig. 3a. (ENABLE chopper) 

(5) See fig. 4a. (ENABLE chopper) 



597 



L6209 



Fig. 5 - Bidirectional DC motor control 




TO CONTROL 
CIRCUIT 



TRUTH TABLE 





INPUTS 


FUNCTION 


Vein = 


= H 


INA = H 


INB = 


L 


Turn right 


INA = L 


INB = 


H 


Turn left 


INA = INB 


Fast motor stop 


v E n = 


L 


INA = X 


INB = 


X 


Free running motor stop 



L = Low H = High X = Don't care 



598 



SGS 



L6210 



ADVANCE DATA 



DUAL SCHOTTKY DIODE BRIDGE 



• MONOLITHIC ARRAY OF EIGHT 
SCHOTTKY DIODES 

• HIGH EFFICIENCY 

• 4A PEAK CURRENT 

• LOW FORWARD VOLTAGE 

• FAST RECOVERY TIME 

• TWO SEPARATED DIODE BRIDGES 

The L6210 is a monolithic IC containing eight 
Schottky diodes arranged as two separated 
diode bridges. 

This diodes connection makes this device versa- 
tile in many applications. 

They are used particular in bipolar stepper motor 
applications, where high efficient operation, 



due to low forward voltage drop and fast reverse 
recovery time, are required. 

The L6210 is available in a 16 Pin Powerdip 
Package (12 + 2 + 2) designed for the to 70°C 
ambient temperature range. 



%p 



Powerdip 12 + 2 + 2 

(V6P2) 



ORDERING NUMBER: L6210 



ABSOLUTE MAXIMUM RATINGS 



If 


Repetitive forward current peak 


2 


A 


v r 


Peak reverse voltage (per diode) 


50 


V 


'amb 


Operating ambient temperature 


70 


°C 


Utg 


Storage temperature range 


-55 to 150 


°C 



BLOCK DIAGRAM 




S- 9320/1 



4,5,12,13 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

599 12/86 



L6210 



THERMAL DATA 



^thj-case Thermal impedance junction-case max 

^thj-amb Thermal impedance junction-ambient without external heatsink max 



14 
65 



C/W 
D C/W 



CONNECTION DIAGRAM 

(Top view) 







w 






K [ 


1 




16 


] K 


ouii r 


2 




15 


]0UT 4 


A [ 


3 




U 


] A 


GNO [ 


4 




13 


] GND 


GND [ 


5 




12 


] GND 


A [ 


6 




11 


] A 


OUT 2 [ 


7 




10 


]0UT 3 


K [ 


8 




9 


1 K 



ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Vf 


Forward voltage drop 


l f = 500mA 




0.8 


1 


V 


l f - 1A 




1 


1.2 


V 


t rr 


Reverse recovery time 


0.5A forward to 0.5A reverse 




15 


60 


ns 
ns 


tfr 

II 


Forward recovery time 


1 A forward to 1.1V recovery 




30 


90 


Leakage current 


Vr = 40V T amb = 25°C 






100 


MA 



NOTE : At forward currents of greater than 1A, a parasitic current of approximately 1 mA may be collected by adiacent 
diodes. 



600 



L6210 



Fig. 1 - Reverse current vs. 
voltage 



Fig. 2 - Forward voltage vs. 
current 


















































- 




















































































































































- - 7*/2* 








— 






- 




-~ — 


Ij =25"C -v 
















— 










■ I / 
, i // 



















MOUNTING INSTRUCTIONS 



The Rthi-amb °f tne L6210 can be reduced by 
soldering the GND pins to a suitable copper 
area of the printed circuit board as shown in 
figure 3 or to an external heatsink (Figure 4). 



During soldering the pin temperature must not 
exceed 260°C and the soldering time must not 
be longer then 12s. The external heatsink or 
printed circuit copper area must be connected 
to electrical ground. 



Fig. 3 - Example of P.C. board copper area 
which is used as heatsink 



Fig. 4 - Example of an 
external heatsink 







r 

c 
c 




] 










IPPP 




///'/// '■'// 


--I 




c 
c 
c 


pi 
] 


0/A 






















\ P. C . BOA 


RD 














601 



as 



L6212 



ADVANCE DATA 



HIGH CURRENT SOLENOID DRIVER 



• HIGH VOLTAGE OPERATION (UP TO 50V) 

• HIGH OUTPUT CURRENT CAPABILITY 
(UP TO 6A) 

• LOW SATURATION VOLTAGE 

• TTL-COMPATIBLE INPUT 

• OUTPUT SHORT CIRCUIT PROTECTION 
(TO GROUND, TO SUPPLY AND ACROSS 
THE LOAD) 

• THERMAL SHUTDOWN 

• OVERDRIVING PROTECTION 

• LATCHED DIAGNOSTIC OUTPUT 

The L6212 is a monolithic switch-mode solenoid 
driver designed for fast, high-current applications 



such as hammer driving in printers and electronic 
typewriters. Power dissipation is reduced by ef- 
ficient switch-mode operation. An extra feature 
of the L6212 is a latched diagnostic output 
which indicates when the output is short circuit. 

The L6212 is supplied in an 15-lead Multiwatt 
plastic power package. 



*ft 



^ 



Multiwatt-15 



ORDERING NUMBER: L6212 



BLOCK DIAGRAM 



DIAG. OUT * V SS 

O Q 



THERMAL 

PROTECTION 




j 







SHORT CIR. 

PROTECTION 

AND 

DIAGNOSTIC 
OUTPUT 




~1 

Id. 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

603 12/86 



L6212 



ABSOLUTE MAXIMUM RATINGS 

V s Power supply voltage 

V 5S Logic supply voltage 

V EN Enable voltage 

V| Input voltage 

l p Peak output current (repetitive) 

Ptot Total power dissipation (at T ca5e = 

T s tg/ T. Storage and junction temperature 



75 C) 



50 

7 

7 

7 

6.5 

25 

-40 to 150 



V 
V 
V 
V 
A 
W 
°C 



CONNECTION DIAGRAM 

(Top view) 



-.- 15 1 




































10 






9 


































































-j 



SINK OUTPUT 

CURRENT SENSING 

AMPLIFIER INPUT 

ENABLE 

N.C. 

TIMING 

INPUT VOLTAGE 

GND 

DIAGNOSTIC OUTPUT 

DIAGNOSTIC SUPPLY VOLTAGE 

N.C. 

ON TIME LIMITER 

N.C. 

SOURCE OUTPUT 

POWER SUPPLY VOLTAGE 



Tab connected to pin 8 



THERMAL DATA 



Thermal resistance junction-case 
Thermal resistance junction-ambient 




604 



L6212 



ELECTRICAL CHARACTERISTICS (Refer to the test circuit, V s = 37V, V ss 
25°C, unless otherwise specified) 



5V, T„ 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


Vs 


Power supply voltage (Pin 1 ) 




12 




46 


V 


Id 


Quiescent drain current 


v E n = H 




20 


30 


mA 


V, > 0.6V V EN = L 




70 




mA 


Vss 


Logic supply voltage (Pin 6) 




4.5 




7 


V 


'ss 


Quiescent logic supply current 


V D | AG = L 




5 


8 


mA 


r 

DIAG Output at high 
impedance 




10 


100 


,uA 


Vj 


Input voltage (Pin 9) 


Operating output 


0.6 






V 


Non-operative output 






0.45 


V 


l| input current (Pin 9) 


V, > 0.6V 
V, < 0.45V 






-2 
-5 


HA 
MA 


V ENABLE 


Enable input current (Pin 12) 


Low level 
High leve 


-0.3 
2.4 




0.8 


V 


'enable 


Enable input current 


V EN = L Vj = 0.8V 
V EN " H V e = 2.4V 






-100 
100 


M A 


V sat H 


Source output saturation volt. 


lp - 5.5A 




2.5 


V 


VsatL 


Sink output saturation volt. 


'out = 5.5A 






2.5 


V 


v sat H + V sat l 


Total saturation voltage 


'out = 5.5A 






4.5 


V 


'leakage 


Output leakage current source 
PNP 


V s = 45V 
Vi «t 0.45V 




2 


mA 


' leakage 


Output leakage current sink 
NPN 


V s = 45V 
Vj < 0.45V 






2 


mA 


K 


On time limiter constant { *) 


V EN = L 




120 


j 


V DIAG 


Diagnostic saturation voltage 
(Pin 7) 


'diag = 1 ° m A 






0.4 


V 


'diag 


Diagnostic leakage current 
(Pin 7) 


V D IAG = 40V 






10 


MA 


VpinlO 
Vpinl3 


OP AMP DC voltage gain 


v pinl3 = 100 to 800mV 




5 




i 


VpinlO 


'pinlO = 1mA 


4.5 






V 


'pinlO 


VpinlO= 4 V V 9 = V 13 =0 
Vp,nlO=2V V 13 = 0.9V 


1 




10 
1.5 


MA 
mA 


'sense 


Input bias current (Pin 13) 






-1 




MA 


Vsense 


Sensing voltage (Pin 14) (**) 








0.9 


V 



(*} After a time interval t max = KC 2 , the output stages are disabled. 

(**} Allowed range of V sense without the intervention of the short circuit protection. 



605 



L6212 



Fig. 2 - Test and typical application circuit 




C2 R1rk _[ci 

47nF~ 33 = 



D2: 6A fast diode 
D1 : 2A fast diode 



trr st 200ns 



Fig. 3 - Peak output current 
vs. input voltage 



R3 = OPE-j 



Fig. 4 - Peak output current 
vs. input voltage 











! 


















i 












v s . iov 

R2.10OA 

R3*33KJ1 

Rs.o.ian 




| 












; 






















t S 


/ 




























1 y 












1 
























i/1 







Fig. 5 - Peak output current 
vs. supply voltage 



! . ! 








V; = 3.5V 

r? -mc a 

R3 ^ 31 K-fi 




1 


_L_lll. , : . 


4 






-L ' : 

! 






■ 


~^ 



0.5 5 1.5 2 25 3 3.5 



□ 0.5 1 1.5 2 2.5 3 3-5 



606 



L6212 



CIRCUIT OPERATION 

The L6212 works as a transconductance ampli- 
fier: it can supply an output current directly pro- 
portional to an input voltage level (V,). Further- 
more, it allows complete switching control of 
the output current waveform (see Fig. 1). 

The following explanation refers to the Block 
Diagram, to Fig. 1 and to the typical applica- 
tion circuit of Fig. 2. 

The to n time is fixed by the width of the Enable 
input signal (TTL compatible): it is active low 
and enables the output stages "source" and 
"sink". At the end of to n , the load current l load 
recirculates through D1 and D2, allowing fast 
current turn-off. 

The rise time t r depends on the load charac- 
teristics, on Vj and on the supply voltage value 
!V s ,pin 1). 

During the t on time, l ]oad is converter into a 
voltage signal by means of the external sensing 
resistance R s connected to pin 13. This signal, 
amplified by the op amp charges the external 
RC network at pin 10 (R1, C1). The voltage 
at this pin is sensed by the inverting input of 
a comparator. The voltage on the non-inverting 
input of this one is fixed by the external voltage 
Vj (pin 9). 

After, t r , the comparator switches and the out- 
put stage "source" is switched off. The com- 
parator output is confirmed by the voltage on 
the non-inverting input, which decreases of a 
constant fraction of V, (1/10), allowing hysteresis 
operation. The current in the load now flows 
through D2. 

Two cases are possible: the time constant of the 
recirculation phase is higher than R1, C1; the 
time constant is lower than R1, CI. In the first 
case, the voltage sensed on the non-inverting 
input of the comparator is just the value pro- 
portional to l| 0a( ]. In the second case, when the 
current decreases too quickly, the comparator 
senses the voltage signal stored in the R1, C1 
network. 

In the first case tj depends on the load charac- 
teristics, while in the second case it depends 
only on the value of R1, C1. 

In other words, R1, CI fixed the minimum value 
of tj (tj > 1/10 R1 x C1. Note that C1 should 



be chosen in the range 2.7 to 10nF for stability 
reasons of the op amp). 

After t x , the comparator switches again: the 
output is confirmed by the voltage on the non- 
inverting input, which reaches V, again (hys- 
teresis). 

Now the cycle starts again: t 2 , t 4 and t 6 have 
the same characteristics as t r , while t 3 and t 5 
are similar to tj. The peak current l p depends 
on V; as shown in the typical transfer function 
of Fig, 3. 

It can be seen that for V, lower than 450mV 
the device is not operating. 

For Vj included between 450 and 600mV, the 
operation is not guaranteed. 

The other parts of the device have protection 
and diagnostic functions. At pin 4 is connected 
an external capacitor C2, charged at constant 
current when the Enable is low, 

After a time interval equal to K • C1 (K is 
defined in the table of Electrical Characteristics 
and has the dimensions of Q.) the output stages 
are switched off independently by the Input 
signal. 

This avoids the load being driven in conduction 
for an excessive period of time (overdriving 
protection). 

The action of this protection is shown in Fig. 
1b. Note that the voltage ramp at pin 4 starts 
whenever the Enable signal becomes active (low 
state), regardless of the Input signal. To reset 
pin 4 and to restore the normal conditions, pin 
12 must return high. This protection can be 
disabled by grounding pin 4. 

In order to keep constant the energy delivered 
to the load, when the supply voltage changes, 
it's possible to modify the output maximum 
peak current (l p ) by means the external voltage 
divider R2 and R3 which "senses" the supply 
voltage. 

I p is given by : 



lr 



Vj (R s + R2 + R3) - 5V S (R2+ R s 
5 R3 R~ 



607 



L6212 



CIRCUIT OPERATION (continued) 

R2 + R, 

Al„ = - 



R3 R 5 

The thermal protection included in the L6212 
has a hysteresis. 

It switches off the output stages whenever the 
junction temperature increases too much. After 
a fall of about 20°C, the circuit starts again. 

Finally, the device is protected against any type 
of short circuit at the outputs: to ground, to 
supply and across the load. 

When the source stage current is higher than 
7A and/or when the pin 13 voltage is higher 



then 1V (i.e. for a sink current greater than 
1V/R S ) the output stages are switched off and 
the device is inhibited. 



This condition is indicated at the open-collector 
output DIAG (pin 7); the internal flip-flop F/F 
changes and forces the output transistor into 
saturation. The F/F must be supplied inde- 
pendently through V ss (pin 6). The DIAG signal 
is reset and the output stages made operative 
by switching off the supply voltage at pin 1 and 
then by switching the device on again. After 
that, two cases are possible: the reason for the 
"bad operation" is still present and the protec- 
tion acts again; the reason has been removed 
and the device starts to work properly. 



Fig. 1 - Output current waveforms 




608 



^I^9^^F® 



L6217 



ADVANCE DATA 



STEPPER MOTOR DRIVER 



MICROSTEPPING 

BIPOLAR OUTPUT 
400mA 



CURRENT UP TO 



• LOW SATURATION VOLTAGE 

• BUILT-IN FAST RECOVERY DIODES 

• OUTPUT CURRENT DIGITALLY PRO- 
GRAMMABLE 

• 6 BIT D/A CONVERTERS SET OUTPUT 
CURRENT 

• THERMAL SHUTDOWN 

The L6217 is a monolithic IC that controls and 
drives both phases of a Bipolar Stepper Motor 
with PWM control of the phase current. The 
output current level of each phase is programmed 
by a 6 bit D/A converter so that the device may 
be used in full-step, half-step and micro-step ap- 
plications. The inputs for the D/A converters and 
the phase inputs to select the direction of current 
flow are latched to minimize the interface to a 
microprocessor. 



The power section of the device is a dual H- 
Bridge drive with internal clamp diodes for 
current recirculation. To maintain the degree 
of accuracy required for micro-stepping, the 
motor current is internally sensed and compared 
to the output of the D/A converter. 

A monostable, programmed by and RC network 
sets the motor current decay time. 

The L6217 is supplied in a 44 pin PLCC with 1 1 
of the 44 pins used for heatsinking. 






PLCC 44 
(Plastic Chip-Carrier) 



ORDERING NUMBER: L6217 



BLOCK DIAGRAM 






; s-:,"D 



'■5-- "O- 



INTERFACES 



Tc-Lrj- 



T 


10 










OUTPUT 
H-BBIOGE 1 


1>- 








STABLE 








r 



_0P-AMPy 

TEST B 



X 



7t>- 



<-*--* 





2 


r 


— -■ 




POWER 

ON 
RESET 


_S_. 






18-28 



<- 



,, j- 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 



609 



12/86 



L6217 



ABSOLUTE MAXIMUM RATINGS 



v„ 


Logic supply voltage 


7 


V 


Vsp 


Motor supply voltage 


18 


V 


v i 


Logic input voltage 


6 


V 


V ref 


Reference input voltage 


v„ 


V 


lo 


Output peak current 


500 


mA 


T| 


Operating junction temperature 


150 


U C 


'stg 


Storage temperature 


-55 to + 150 


"C 



CONNECTION DIAGRAM 

(Top view) 



I 




Im 


o 












a. 


< 


u 





/ 6 


5 


4 


3 


2 


1 


44 


43 


42 


41 


40 




v th^ 


7 




















39 


P DO 


MRST C 


B 




















38 


□ D1 


MRSTDLC 


9 




















37 


]D2 


ptaC 


10 




















36 


JD3 


ptbC 


11 




















35 


U D4 


v s bC 


12 




















34 


U D5(MSB) 


vs A C 


13 




















33 


2 PH 


digfC 


H 




















32 


Dv SP Cis> 


OUT A2C 


15 




















31 


30UTB1 


OUT A 1C 


16 




















30 


DOUT B2 


R 5 A C 


17. 




















29 


H R S B 




18 


19 


20 


21 


22 


23 


24 


25 


26 


27 


28 






u 


U 


U 


TJUU 


u 


U U U 


U 
— »- 





THERMAL DATA 



Mh j-case 

'th j-amb 



Thermal impedance junction-case 
Thermal impedance junction-ambient 



max 
max 



10 
80 



"C/W 
= C/W 



610 



L6217 



PIN FUNCTION DESCRIPTION 



NAME FUNCTION 



Active low input resets the D/A latches to and disables the 
output. 



38,39 DO - D5 Data inputs for the D/A converter. (DO = LSB) 

For a data input of 00, the corresponding outputs are held in the 
off state. 



44 


A/B 


Channel select for input data. Pin A/B selects channel A when 
high. 


33 


PH 


Logic input selects direction of current flow in output bridge 
from A1 (B1) to A2 (B2) for PH = 1. 








42 


Strobe 


Active low input latches input data (DO - D5 and PH) into 
input latch. 



MRST DL The capacitor on this pin programs the power on reset delay ac- 

cording to the formula: 

t d = (0.35) (C) 10 6 



8 MRST Power-on reset circuit output. (Micro reset signal). 

This output remains low from power on until the delay capacitor 
has charged past the delay threshold. 

10 Pt A Pulse time A, an external parallel RC network tied to ground 

defines t off time for channel A. (t off = 0.69 R2C2). 

1 1 P t B Pulse time B, an external parallel RC network tied to ground 

defines toll time for channel B. (t off = 0.69 R3C3). 

5 V ref ln Voltage applied to this point sets the reference for the D/A con- 

verter and threfore sets the maximum output current. 
(See equation 1 , next two pages). 



18 to 28 


Gnd 


Ground connection and also conducts heat to the P.C. board. 


40 


GndO 


Pin must be connected to ground. 


2 


V sl 


Logic supply voltage 


32 


Vsp 


Motor supply voltage 





611 



L6217 



PIN FUNCTION DESCRIPTION (continued) 


N° 


NAME 


FUNCTION 


16, 15 
31, 30 


Out A1-A2 
B1-B2 


H-Bridge outputs. 


43, 41 


CSO, CS1 


Chip select inputs CSO is active high, CS1 is active low. 


17, 29 


R S A - R S B 


Sense resistor from this pin to ground set the peak output current. 


13, 12 


V 5 A - V S B 


Analog inputs for sensing motor current, Separate inputs are 
provides to allow filtering of the sense voltage if required. 


3, 4 


Test A & B 


These pins are for testing of D/A outputs. 


6 


Vref out 


2.5V band gap reference. 


7 


v th 


Reset threshold voltage 


14 


DIGF 


Can be used to modify the internal comparator lockout time. In 
the typical application this pin is left open. 



ELECTRICAL CHARACTERISTICS (V cc = 5.0V, T, = 25°C unless otherwise specif ied noted) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V sp Motor supply voltage 




8 




16 


V 


V S | Logic supply voltage 




4.75 




5.25 


V 



LOGIC INPUTS (D0-D5, CSO, CS1, Reset and A/B) 



Vj l_ Input low voltage 








0.8 


V 


V] h Input high voltage 




2 




V 5 | 


V 


l[L_ Input low current 


V, = 0.4V 






-400 


MA 


lj |_) Input high current 


V; = 2.4V 
1 






10 


m a 



CURRENT CONTROL AND D TO A SECTION 














V ref Reference voltage 


v C c = 


5.0V 


2.45 


2.50 


2.55 


V 


V r | n Reference input range 




2.0 




3.0 


V 


Monotonicity of D to A 




-0.5 




+ 0.5 


LSB 


Linearity of D to A 




-1 




+ 1 


lsb 


l op Peak Output Current 
(Gain of current loop) 


Vref = 
"sense 
Data = 


2.40V 

= 2n 

3F (Hex) 


225 


252 


277 


mA 


l Output matching 


Vref = 


2.40V 






5 


% 



612 



L6217 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test Conditions 


Min. Typ. 


Max. 


Unit 



MONOSTABLE 



t off Cutoff time 


R t = 56Kn 
C t = 820pF 


27 




37 


MS 


t^ Turn-off delay 








2 


MS 


l ff Output leakage current 


Data = 00 (Hex) 






100 


MA 



RESET CIRCUITRY 



V th Reset threshold voltage 




3.9 


4.1 


4.3 


V 


Reset threshold hysteresis 




70 


100 




mV 


l so Delay capacitor charging current 


V c = 2.5V 


7 


10 


14 


M 


l S j Delay capacitor discharge current 


V c = 2,5V 


10 






mA 


V dtn Delay threshold voltage 




3.25 


3.5 


3.75 


V 


Vdhys Hysteresis voltage on delay threshold 




70 


100 




mV 


l D l Output leakage current 


V = 5V 






200 


MA 


v sat Output saturation of reset out 


l = 2mA 






0.4 


V 



SOURCE DIODE-TRANSISTOR PAIRS 














V sat Saturation voltage 


lo = 


= 400mA 




1.3 


1.8 


V | 


Vf Diode forward voltage 


to - 


= 400mA 




0.8 


1.2 


V J 



SINK DIODE-TRANSISTOR PAIRS 



V sat Saturation voltage 


l = 400mA 




1.1 


1.5 


V 


V f Diode Forward voltage 


l = 400mA 




0.6 


1.0 | V 



AC CHARACTERISTICS 



t s Set-up time 








100 


ns 


t n Hold time 








500 


ns 


t w Minimum input pulse width 






600 


ns 



CIRCUIT OPERATION 



The current control section of the L6217 is a 
pulse width modulated control that senses the 
motor current. When the motor current reaches 
the peak programmed current the comparator 
will trigger the monostable turning off the upper 
transistors. After the t off time equal to 0.69 RC 
the upper drivers are enabled again. 

The peak current is given by the equation : 



When the input data is 00, the output stages 
are disabled by internal logic so that the output 
current decays rapidly to zero. 
An internal generated lockout time avoids the 
use of an external RC network between the sens- 
ing resistor (R S A, R S B) and the corresponding 
input (V S A, V 5 B), by disabling the comparator 
sensing during the lockout time. This time is 
typically 2.5ms. 



V, 



ref 



D 



4.69 • R„ 



'sense 
Input data (0-63) 



64 



613 



L6217 



Fig. 1 - Typical application 




2.5mH /0| 



Fig. 2 - Microcomputer interface timing 

DATA \ ^ 



STROBE CS1 



"\ 



•s , *h T 



L i * W 



J k_ 



Fig. 3- t off DELAY 



V S A(V S B)' 



p T A(P T B)- 





614 



L6217 



Fig. 4 - Motor current (half step mode) 



Fig. 5 - Monostable voltage and motor current 
repetitive steps. 





Fig. 6 - Reset waveforms 




RESET OUT 



615 



^^^^^^8 



L6217A 



ADVANCE DATA 



STEPPER MOTOR DRIVER 

• MICROSTEPPING 

• BIPOLAR OUTPUT CURRENT UP TO 
400mA 

• LOW SATURATION VOLTAGE 

• BUILT-IN FAST RECOVERY DIODES 

• OUTPUT CURRENT DIGITALLY PRO- 
GRAMMABLE 

• 7 BIT D/A CONVERTERS SET OUTPUT 
CURRENT 

• THERMAL SHUTDOWN 

The L6217A is a monolithic IC that controls and 
drives both phases of a Bipolar Stepper Motor 
with PWM control of the phase current. The 
output current level of each phase is programmed 
by a 7 bit D/A converter so that the device may 
be used in full-step, half-step and micro-step ap- 
plications. The inputs for the D/A converters and 
the phase inputs to select the direction of current 
flow are latched to minimize the interface to a 
microprocessor. 

BLOCK DIAGRAM 



The power section of the device is a dual H- 
Bridge drive with internal clamp diodes for 
current recirculation. To maintain the degree 
of accuracy required for microstepping, the 
motor current is internally sensed and compared 
to the output of the D/A converter. 

A monostable, programmed by and RC network 
sets the motor current decay time. 

The L6217A is supplied in a 44 pin in PLCC with 
11 of the 44 pins used for heatsinking. 



'% 



? r 



PLCC 44 
(Plastic Chip-Carrier) 

ORDERING NUMBER: L6217A 



N^* 



10' 

MONO- 
STABLE 





OUTPUT 


<]- 


J 


3 S 

5* 



OUTPUT A2 



9 ,.._MRSTDL 




to-Lq 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

617 12/86 



L6217A 



ABSOLUTE MAXIMUM RATINGS 



V,i 


Logic supply voltage 


7 


V 


Vsp 


Motor supply voltage 


18 


V 


v, 


Logic input voltage 


6 


V 


v ref 


Reference input voltage 


V S | 


V 


lo 


Output peak current 


500 


mA 


I. 


Operating junction temperature 


150 


°C 


'stg 


Storage temperature 


-55 to +150 


°C 



CONNECTION DIAGRAM 

(Top view) 



nnnnnnnrinnn 



MRST C B 

MRSTDLC 9 

PTAC 10 

PTBC 'I 

V S BC 12 

V S aC '3 

DIGFC h 

OUT A2Q 15 

OUT A IE 16 

BcA C " 



6 5 4 3 2 1 44 43 42 41 40 



18 19 20 21 22 23 24 25 26 27 29 
UUUUUUUUUUU 



39 


Dai 


38 


3 D2 


37 


3 D3 


36 


HD4 


35 


IID5 


34 


3 D6(MSB) 


33 


3PH 


32 


DV Sp M6) 


31 


30UTB1 


30 


30UTB2 



U R s B 



THERMAL DATA 



^thj-case Thermal impedance junction-case 

^thj-amb Thermal impedance junction-ambient 



max 
max 



10 
80 



C/W 
= C/W 



618 



L6217A 



PIN FUNCTION DESCRIPTION 



40, 34 



44 



33 



42 



10 



11 



18 to 28 



32 



16, 15 
31, 30 



NAME 



DO- D6 



A/B 



PH 



Strobe 



Gnd 



Out A1-A2> 
B1-B2 



FUNCTION 



Active low input resets the D/A latches to and disables the 
output. 



Data inputs for the D/A converter. (DO = LSB) 

For a data input of 00, the corresponding outputs are held in the 

off state. 



Channel select for input data. Pin A/B selects channel A when 
high. 



Logic input selects direction of current flow in output bridge 
from A1 (B1) to A2 (B2) for PH = 1. 

Active low input latches input data (DO - D5 and PH) into 
input latch. 



MRST DL The capacitor on this pin programs the power on reset delay ac- 

cording to the formula : 

t d = (0.35) (C) 10 6 



MRST Power-on reset circuit output. (Micro reset signal). 

This output remains low from power on until the delay capacitor 
has charged past the delay threshold. 

P t A Pulse time A, an external parallel RC network tied to ground 

defines t off time for channel A. (t off = 0.69 R2C2). 



Pulse time B, an external parallel RC network tied to ground 
defines t off time for channel B. (t off = 0.69 R2C2) 



Voltage applied to this point sets the reference for the D/A con- 
verter and threfore sets the maximum output current. 
(See equation 1 , next two pages). 



Ground connection and also conduct heat to the P.C. board. 



Logic supply voltage 



Motor supply voltage 



H-Bridge outputs. 



619 



L6217A 



PIN FUNCTION DESCRIPTION (continued) 



43, 41 



17, 29 



13, 12 



3, 4 



14 



NAME 



CSO, CS1 



R<A - R<B 



V.A - V,B 



Test A & B 



"ref out 



DIGF 



FUNCTION 



Chip select inputs CSO is active high, CS1 is active low. 



Sense resistor from this pin to ground set the peak output current. 



Analog inputs for sensing motor current, Separate inputs are 
provides to allow filtering of the sense voltage if required. 



These pins are for testing of D/A outputs. 



2.5V band gap reference. 



Reset threshold voltage 



Can be used to modify the internal comparator lockout time. In 
the typical application this pin is left open. 



ELECTRICAL CHARACTERISTICS (V cc = 5.0V, Tj = 25°C unless otherwise specified noted) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V sp Motor supply voltage 




8 




16 


V 


V S | Logic supply voltage 




4.75 




5.25 


V 



LOGIC INPUTS (D0-D6, CSO, CS1, PH, RST and A/5) 










V| L Input low voltage 








0.8 


V 


V iH Input high voltage 




2 




Vsl 


V 


lj l Input low current 


V, = 0.4V 






-400 


ma 


l iH Input high current 


V, = 2.4V 






10 


ma 



CURRENT CONTROL AND D TO A SECTION 



V ref Reference voltage 


V CC = 5.0V 


2.45 


2.50 


2.55 


V 


V rjn Reference input range 




2.0 




3.0 


V 


Monotonicity of D to A 




-0.5 




+ 0.5 


LSB 


Linearity of D to A 




-1 




+ 1 


LSB 


l op Peak Output Current (Gain of current loop) 


V ref = 2.38V 

"sense ~ ^ 
Data = 7F (Hex) 


225 


252 


277 


mA 


l Output matching 


V ref = 2.38V 






5 


% 



620 



L6217A 



ELECTRICAL CHARACTERISTICS (continued) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 



MONOSTABLE 



t off Cutoff time 


R t = 56Kn 
C t = 820pF 


27 




37 


MS 


t d Turn-off delay 








2 


MS 


1 -ff Output leakage current 


Data = 00 (Hex) 






100 


MA 



RESET CIRCUITRY 



V th Reset threshold voltage 




3.9 


4.1 


4.3 


V 


Reset threshold hysteresis 




70 


100 




mV 


t so Delay capacitor charging current 


V c = 2.5V 


7 


10 


14 


MA 


l 5 l Delay capacitor discharge current 


V c = 2.5V 


10 






mA 


V dth Delay threshold voltage 




3.25 


3.5 


3.75 


V 


V dnys Hysteresis voltage on delay threshold 




70 


100 




mV 


f 0( Output leakage current 


V = 5V 






200 


MA 


^sat Output saturation of reset out 


l = 2mA 






0.4 


V 



SOURCE DIODE-TRANSISTOR PAIRS 



V 5at Saturation voltage 


l D = 400mA 


1.3 


1.8 


V 


Vf Diode forward voltage 


l = 400mA ) 


0.8 


1.2 


V 


SINK DIODE-TRANSISTOR PAIRS 




V sat Saturation voltage 


l = 400mA 




1.1 


1.5 


V 


Vf Diode Forward voltage 


l = 400mA 




0.6 


1.0 


V 



AC CHARACTERISTICS 



t s Set-up time 








100 


ns 


t n Hold time 








500 


ns 


t w Minimum input pulse width 








600 


ns 



CIRCUIT OPERATION 



The current control section of the L6217A is a 
pulse width modulated control that senses the 
motor current. When the motor current reaches 
the peak programmed current the comparator 
will trigger the monostable turning off the upper 
transistors. After the t off time equal to 0.69 RC 
the upper drivers are enabled again. 



The peak current is given by the equation : 



V, 



When the input data is 00, the output stages 
are disabled by internal logic so that the output 
current decays rapidly to zero. 
An internal generated lockout time avoids the 
use of an external RC network between the sens- 
ing resistor (R S A, R S B) and the corresponding 
input (V S A, V,.B), by disabling the comparator 
sensing during the lockout time. This time is 
typically 2.5ms. 



ref 



4.69 • R, 



128 



Input data (0 -7F H) 



621 



L6217A 



Fig. 1 - Typical application 




25mH ( M 
20ilTyp. 



Fig. 2 - Microcomputer interface timing 



Fig. 3- t off DELAY 



S.TROBE CS1 



<=> 



J 



y~ 



V S A(V S B) 



P t a (Pt B > 




622 



L6217A 



Fig. 4 •• Motor current (half step mode) 



Fig. 5 - Monostable voltage and motor current 
for repetitive steps. 



fit HI mtt- 

W\a /WW, 




Fig. 6 - Reset waveforms 




RESET OUT 



623 



^^^^^^® 



L6221A 
L6221N 



ADVANCE DATA 



QUAD DARLINGTON SWITCHES 



• OUTPUT VOLTAGE TO 50V 

• OUTPUT CURRENT TO 1.8A 

• VERY LOW SATURATION VOLTAGE 

• TTL COMPATIBLE INPUTS 

• INTEGRAL FAST RECIRCULATION DIODES 

The L6221 monolithic quad darlington switch 
is designed for high current, high voltage switch- 
ing applications. Each of the four switches is 
controlled by a logic input and all four are con- 
trolled by a common enable input. All inputs 
are TTL-compatible for direct connection to 
logic circuits. 

Each switch consists of an open-collector darling- 
ton transistor plus a fast diode for switching 
applications with inductive loads. The emitters 

BLOCK DIAGRAMS 




L6221N 
Multiwatt 



of the four switches are commoned. Any number 
of inputs and outputs of the same device may be 
paralleled. 

Two versions are available: the L6221A mounted 
in a Powerdip 12 + 2+ 2 package and the L6221N 
mounted in a 15-lead Multiwatt package. 




Multiwatt 15 



Powerdip 12 + 2 + 2 

(V6P2) 



ORDERING NUMBER : 

L6221N L6221A 




L6221A 
Powerdip 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

625 12/86 



L6221A 
L6221N 



ABSOLUTE MAXIMUM RATINGS 



Vo 


Output voltage 








50 


V 


Vss 


Logic supply voltage 








7 


V 


Vj 


Input voltage 








Vss 




lc 


Collector current 








1.8 


A 


"c 


Collector peak current (repetitive, duty cycle = 1% t on = 


= 10ms) 






2.5 


A 


lc 


Collector peak current (non repetitive, t= 10/js) 








3.2 


A 


'op 


Operating temperature range (junction) 




-40 


to 


+ 150 


°C 


"^stg 


Storage temperature range 




-55 


to 


+ 150 


°C 


'sub 


Output substrate current 








350 


mA 



THERMAL DATA 



R'hj-amb Thermal resistance junction-ambient 
Rthj-case Thermal resistance junction-case 



max 
max 



Powerdip 



80 C/W 
14°C/W 



Multiwatt 



35 C/W 
3° C/W 



TRUTH TABLE 



Enable 


Input 


Power out 


H 

H 
L 


H 

L 
X 


ON 

OFF 

OFF 



For each input : H = High level 
L = Low level 
X = Don't care 



626 



L6221A 
L6221N 



PIN FUNCTIONS 



L6221N 
Multiwatt 


L6221A 
Powerdip 


Name 


Function 


4 


9 


IN 1 


Input to driver 1 


5 


10 


IN 2 


Input to driver 2 


3 


8 


OUT 1 


Output of driver 1 


1 


6 


OUT 2 


Output of driver 2 


2 


7 


CLAMP A 


Diode clamp to driver 1 and driver 2 


11 


15 


IN 3 


Input to driver 3 


12 


16 


IN 4 


Input to driver 4 


15 


3 


OUT 3 


Output of driver 3 


13 


1 


OUT 4 


Output of driver 4 


14 


2 


CLAMP B 


Diode clamp to driver 3 and driver 4 


9 


14 


ENABLE 


Enable input to all drivers 


7 


11 


V ss 


Logic supply voltage 


8 


4 


GND 


Ground 


- 


5 


GND 


Ground 


- 


12 


GND 


Ground 


- 


13 


GND 


Ground 


6 


- 


NC 


Not connected 


10 


- 


NC 


Not connected 



627 



L6221A 
L6221 N 



ELECTRICAL CHARACTERISTICS (V ss = 5V, T amb = 25° C unless otherwise specified) 



Parameter 


Test Conditions 


Mjn. 


Typ. 


Max. 


Unit 


V SS Logic supply voltage 




4.5 




7 


V 


v CE(sus) Output sustaining voltage 


V, N = 0.8V V EN = 5V 
l c = 100mA 


46 






V 


'cex Output leakage current 


V CE = 50V 

V, N = 0.8V V E m = 5V 






1 


mA 


v CE(sat) Collector emitter saturation 
voltage 

(One input on; all other 
inputs off.) 


l c = 0.6A 


V ss = 4.5V 
VlN = 2V 
V EN = 4.5V 






1 


V 


l C = 1A 






1.2 


V 


l c = 1.8A 






1.8 


V 


Vjl Input low voltage 








0.8 


V 


1 1 l_ Input low current 


V, N = 0.4V 






-100 


HA 


V 1 1— i Input high voltage 




2.0 






V 


l|H Input high current 


V|N = 2.0V 






i 10 


MA 


l s Logic supply current 




All outputs ON 
l c = 0.7A 






20 


mA 


All outputs OFF 






20 


mA 


Ir Clamp diode leakage current 


V R = 50V 

V, N = 0.8V V EN = 5V 






100 


MA 


Vp Clamp diode forward voltage 


l F = 1A 






1.6 


V 


l F = 1.8A 






2.0 


V 


t on Turn on time 


v s = 5v r l = ion 






2 


MS 


t D ff Turn off time 


V s = 5V R L = ion 






5 


MS 


A l s Logic supply current 
variation 


V, N = 5V, V EN = 5V, V ss = 5V 
l out = - 300mA for each channel 






120 


mA 



628 



^^^^^^® 



L6222 



ADVANCE DATA 



QUAD TRANSISTOR SWITCH 

• OUTPUT VOLTAGE TO 50V 

• OUTPUT CURRENT TO 1.2A 

• VERY LOW SATURATION VOLTAGE 

• TTL COMPATIBLE INPUTS 

• INTEGRAL SUPPRESSION DIODE 

The L6222 monolithic quad transistor switch 
is designed for high current, high voltage switch- 
ing applications. 

Each of the four switches is controlled by a logic 
input and all four are controlled by a common 
enable input. All inputs are TTL-compatible for 
direct connection to logic circuits. Each switch 
consists of an open-collector transistor plus a 
clamp diode for applications with inductive loads. 



The emitters of the four switches are commoned. 
Any number of inputs and outputs of the same 
device may be paralleled. 

This device is intended to drive coils such as 
relays, solenoids, unipolar stepper motors, 
LED, etc. 



*fypi 



Powerdip 12 + 2 + 2 

(V6P2) 



ORDERING NUMBER: L6222 



Fig. 1 - Unipolar stepper motor drive 




This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

629 12/86 



L6222 



ABSOLUTE MAXIMUM RATINGS 



v s 


Output voltage 


50 


V 


V ss 


Logic supply voltage 


7 


V 


V,N 


Input voltage 


15 


V 


lc 


Collector current (PEAK) 


1.2 


A 


' op 


Operating temperature range (junction) 


-40 to +150 


"C 


'stg 


Storage temperature range 


-55 to + 150 


°C 



CONNECTION DIAGRAM 

(Top view) 



TRUTH TABLE 



OUT I 
CLAMPA 
OUT 2 
GND 
GND 
OUT 3 
CLAMPB 
OUT 4 



"v_/ 



16 


] IN 1 


15 


] IN 2 


U 


] ENABLE 


13 


] GND 


12 


] GND 


1 ' 


1 v ss 


10 


] IN3 


9 


j IN A 



Enable 


Input 


Power out 


H 
H 
L 


H 
L 
X 


ON 

OFF 

OFF 



For each input : H = High level 
L = Low level 
X = Don't care 



THERMAL DATA 



R t , 



Thermal resistance junction-ambient 



Rthi-case Thermal resistance junction-case 



max 
max 



80 
14 



C/W 
°C/W 



630 



L6222 



ELECTRICAL CHARACTERISTICS (T amb = 25°C, unless otherwise specified) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V ss Logic supply voltage 




4.50 




7 


V 


Vce(sus) Output sustaining voltage 


V, N = 0.8V 
l c = 100mA 


46 






V 


'cex Output leakage current 


V CE = 50V 
V| N = 0.8V 






I 


mA 


^CE(sat) Collector emitter saturation 
voltage 


V, N > 2.0V 


l c = 0.1A 






0.2 


V 


l c = 0.4A 






0.5 


l c = 0.7A 






0.9 


V|[_ Input low voltage 








0.8 


V 


IjL Input low current 


V, N = 0.4V 






-100 


MA 


V|h Input high voltage 




2.0 






V 


f|H Input high current 


V, N > 2.0V 






± 10 


MA 


Is Logic supply current 


V ss = 5V 


All outputs ON 
l c = 0.7A 




50 


85 


mA 


All outputs OFF 




8 




mA , 


Ir Clamp diode leakage current 


V R = 50V 






100 


M 


Vp Clamp diode forward voltage 


l F = 0.7A 






1.6 


V 


l F = 1.2A 






2.0 



631 



SS 



L6230 



ADVANCE DATA 



BIDIRECTIONAL THREE 
DC MOTOR DRIVER 



-PHASE BRUSHLESS 



• 3A OUTPUT CURRENT, CONTROLLED IN 
LINEAR MODE 

• SUPPLY VOLTAGE UP TO 18V 

• COMPATIBLE WITH ANI F-TO-V CON- 
VERTER AND PLL SPEED CONTROL 
SYSTEM 

• SLEW RATE LIMITING FOR EMI REDUC- 
TION 

• CONNECTS DIRECTLY TO HALL EFFECT 
CELLS 

• THERMAL SHUTDOWN WITH HYSTERESIS 

• THREE-STATE OPERATION ALLOWS 
NEGLIGIBLE POWER DISSIPATION DUR- 
ING 1/3f CYCLE 

• INTERNAL PROTECTION DIODES 

• FEW EXTERNAL COMPONENTS 

The L6230 is a single-chip driver for three-phase 
brushless DC motors capable of delivering 3A 
output current with supply voltages to 18V. 
Designed to accept differential input from the 
Hail effect senso's, the device drives the three 
phases of a brushless DC motor and includes 
all the commutation logic required for a three 
phase bidirectional drive. Both delta and wye 
configurations may be used. 

To limit EMI esmission the L6230 operates in a 
linear mode and controls the rise and fall times 



of the output stage. In addition the device is 
designed to limit power dissipation: during 
recirculation the output stage is switched to an 
off state, reducing dissipation to a very low value 
and minimizing torque ripple. 

A speed control input controls the base current 
to the lower transistors to limit the motor cur- 
rent and hence control the speed. Any type of 
speed control system, including F to V and PLL 
systems, may be used with the L6230 by pro- 
viding an analog signal at this input. The motor 
current may be sensed by an external resistor 
connected to a sensing pin on the device. 

The power stage of the device is designed to eli- 
minate the possibility of simultaneous conduc- 
tion of the upper and lower power transistors of 
one output driver, when operating in the right 
loop. 



Multiwatt-15 

(Horizontal) 



ORDERING NUMBER: L6230H 




BLOCK DIAGRAM 



r _J_J' 9V £ 



(.6230 

50pr 



"rfer 



— -K i- 1 



;f^l_^C 



-L- 



* 



SHUT 
DOWN 



50pF 



X 



■t 



i in 



~K . "I 



F=F 



This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 

633 12/86 



L6230 



CONNECTION DIAGRAM 

(Top view) 



/ 


i] 

) i 

i 


o 
o 


15 

u 

13 

12 
1 i 
10 
9 
8 
7 
6 
5 
U 
3 
2 
1 








c 











> 


' — -——> 
















, _ ___ 




, __3 






|—_ ______ ^ 











OUT 2 
CURRENT 
OUT 3 



h ; 



-) 



GND 
H3 (» 
H2 (-) 
H2(+ 
H1 (-. 
HI (♦ 
INDE X 
FWO/REV 



T ab connected to pin 8 



ABSOLUTE MAXIMUM RATINGS 



V s 


Supply voltage 


lo 


Peak output current each channel 




— non repetitive (100jUs) 




— repetitive (t = 10ms) 




— DC operation 


v, 


Logic and analogic inputs 


•tot 


Total power dissipation T case = 7 


' op 


Operating temperature range 


Tj.T stg 


Storage and junction temperature 



75'C 



20 



4 


A 


3.5 


A 


3 


A 


V s 




25 


W 


Oto 70 


°C 


40 to 150 


°C 



THERMAL DATA 



'th j-case 



Thermal resistance junction-case 



C/W 



634 



PIN FUNCTIONS 



L6230 



NAME 



I/O 



FUNCTION 



FWD/REV 



Direction Control. When this pin is low, the motor will 
run in the forward direction. A high will drive the motor 
in the reverse direction. Direction is defined by the 
position of the sensors in the motor. 



13 
14 
15 



INDEX 



OUT2 



Signal pulse proportional to the motor speed. In PLL 
speed control applications, this is the feedback to the 
PLL. One pulse per electrical rotation. This is an open 
collector output. 



3 


H1 ( + ) 


I 


Positive input of differential amplifier on channel 1. 
Interfaces with Hall Effect sensor, S1, from motor. 


4 


H1 (-) 


I 


Negative input of differential amplifier on channel 1. 
Interfaces with Hall Effect sensor, S1, from motor. 


5 


H2 ( + ) 


I 


Same as pin 3 for channel 2. 


6 


H2 (-) 


I 


Same as pin 4 for channel 2. 


7 


H3 ( + ) 


I 


Same as pin 3 for channel 3. 


8 


GND 




Ground connection. 


9 


H3 (-) 


I 


Same as pin 4 for channel 3. 


10 


V c 


I 


Speed control input. Connected to output of PLL in 
PLL speed control applications. 


11 


OUT3 





Output motor drive for phase 3. 


12 


SENSE 


I 


Current Sensing. Input for load current sense voltage for 
output stage. 



Output motor drive for phase 2. 



Motor supply voltage. 



OUT1 



Output motor drive for phase 1. 



635 



L6230 



ELECTRICAL CHARACTERISTICS (T amb = 25°C; V s = 12V unless otherwise specified) 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Unit 


V s Supply voltage 




10 


12 


18 


V 


l s Quiescent supply current 






60 | 100 


mA 



HALL AMPLIFIERS 



V CM Common mode voltage range 









10 


V 


Vj Input offset voltage 


V, = 6V 




2 


10 


mV 


Ijb Input bias current 


V, = 6V 




2 


10 


,uA 


l| Input offset current 


V, = 6V 




0.1 




,uA 



SP EED CO NTROL INPUT (V c ) 
Vj input voltage range 



Input bias current 



Vic 



Input clamping voltage 



5.9 



FWD/REVERSE INPUT 



OUTPUT POWER STAGE 



V|H 


Input nigh voltage 






. ~"T~" 


-L Vs J 


V 


V|L 


Input tow voltage 




I 

r- ! 


-■ -\ — i 

] 0.8 


V 


! IH 


input high current 






! 


10 


M A 


l|L 


Input low current 




i I ... 


-50 


M 



HALL LOGIC OUTPUT 








V l q Low output voltage 


I = 5mA [ 


| 0.8 


V 


l L Leakage current 


V CE = 12V j 


{ 1 10 


1 
MA 



V sat 


Tota! saturation voltage 


lo = 1A 
lo = 2A 
lo = 3A 




2.7 
3.6 
4,2 


I" 


3.7 
4.5 


V 


V OSR 


Output voltage slew-rate 






100 : 
i 


V./ms 


^ sens 


Sens voltage range 









! 


0.7 


V 



THERMAL SHUTDOWN 



Junction temperature 
Hysteresis 



30 



°C 
°C 



636 



DESCRIPTION 



L6230 



The L6230 is a three-phase brushiess motor 
driver IC containing ail the power stages and 
commutation logic required for a three-phase 
bidirectional drive. 

Logic signals from the motor's Hall effect sensors 
are decoded to generate the correct driving 
sequence according to the truth-table of Fig. 1, 

The direction of rotation is controlled by the 
forward/reverse input (pin 1). When this pin is 
at a low level the motor rotates in the forward 
direction. 

When one of the push-pull output drivers is 
activated the upper transistor Is always in sa- 
turation jvhile the lower transistor Is controlled 
in linear mode to set the desired speed In steady 
state conditions. 

In PLL speed control applications the device 
provides a signal proportional to the motor 
speed at pin 2 (it is the buffered H1 input). The 
output of the PLL is connected to the speed 
control input on the device at pin 10, V c . 

In addition, a 1V offset is added to the speed 
demand voltage to match the minimum output 
of the PLL. 

An external resistor, R s , senses the output stage 
current. The sensing voltage across this resistor is 
amplified in the device by a factor of 7 to allow 
a reduction in the voltage drop in the resistor. 

The amplified sensing voltage is then compared 
with the speed demand signal from the PLL and 
the resulting error signal sets the amplifier output 
accordingly. 



The output current is related to the speed con- 
trol voltage by: 

l Q = (V c -1)/7 R s 

The value of the sensing resistor is given by: 

Rs = (Vx-D/(7 l max ) 

where V x is the full scale voitage of V c (see 
fig. 2). 

In this way the V c /l out characteristics can be 
modified as shown in Fig. 2. Note that V x max 
is clamped at 5.9V. 

The most important feature of the L6230 is 
slew rate control. With this device a typical value 
of 0.1V/;us is achieved, reducing EMI to a very 
low value. 

In a delta configuration a key feature is three- 
state operation, when the current is recirculating 
the corresponding phase driver is switched off 
and power dissipation is negligible. Current re- 
circulates through the integrated free-wheeling 
diodes in the acceleration phase and through the 
motor in steady -state conditions. Torque ripple 
is also minimized. 

The L6230 can also operate with a brushiess 
motor connected in a star configuration, leaving 
the center floating. 

The Hal! inputs are ground compatible com- 
parators and can work with direct active digital 
Hall signals on three terminals (of the same 
polarity) and a TTL level on the other three 
terminals. 



Fig. 1 - TRUTH TABLE FOR FORWARD ROTATION 



HALL EFFECT 
DIFF. INPUT 



1 ^ POSITIVE 
= NEGATIVE 



H1 



1 
1 




1 




o 





1 


1 1 








1 I 








I 



UPPER DRIVER 
STATUS 



ON 
OFF 



UD1 UD2 



UD3 



LOWER DRIVER 
STATUS 



1 = ON 
= OFF